1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/i2c_smbus.h>
4 #include <device/i2c.h>
5 #include <device/smbus_host.h>
6 #include <southbridge/intel/bd82x6x/pch.h>
7 #include "sc16is7xx_init.h"
8
9 /*
10 * Datasheet - SC16IS740/750/760, Rev. 7 - 9 June 2011
11 * https://web.archive.org/web/20210612105830/https://www.nxp.com/docs/en/data-sheet/SC16IS740_750_760.pdf
12 */
13
14 // Bits [6:3] of the subaddress is to address device internal registers
15 #define INTERNAL_REG_SUB_ADDR_SHIFT 3
16
17 #define REG_THR 0x00 // Transmit Holding Register
18 #define REG_LCR 0x03 // Line Control Register
19
20 // Special Register Set is accessible only when LCR[7] is logic 1
21 #define REG_DLL 0x00 // divisor latch LSB
22 #define REG_DLH 0x01 // divisor latch MSB
23
24 #define LCR_WORD_LEN_BIT_0 BIT(0)
25 #define LCR_WORD_LEN_BIT_1 BIT(1)
26 #define LCR_STOP_BIT BIT(2)
27 #define LCR_PARITY_BIT_0 BIT(3)
28 #define LCR_PARITY_BIT_1 BIT(4)
29 #define LCR_PARITY_BIT_2 BIT(5)
30 #define LCR_BREAK_CTL_BIT BIT(6)
31 #define LCR_SPEC_REG_SET_EN BIT(7)
32
33 #define UART_8_N_1 (LCR_WORD_LEN_BIT_0 | LCR_WORD_LEN_BIT_1)
34
35 /*
36 * UART configuration: 8 bit word length, No parity, 1 stop bit (8-N-1)
37 * Divisor value set here is calculated for 115200 baud rate
38 * in 14.7MHz clock input to chip.
39 */
40
41 #define BAUD_115200_DLL 0x08
42 #define BAUD_115200_DLH 0x00
43
sc16is7xx_write_byte(uint8_t reg,unsigned char c)44 void sc16is7xx_write_byte(uint8_t reg, unsigned char c)
45 {
46 do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE,
47 CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, reg, c);
48 }
49
sc16is7xx_init(void)50 void sc16is7xx_init(void)
51 {
52 // Configure 8-N-1 and enable special register set
53 sc16is7xx_write_byte(REG_LCR << INTERNAL_REG_SUB_ADDR_SHIFT,
54 (UART_8_N_1 | LCR_SPEC_REG_SET_EN));
55
56 sc16is7xx_write_byte(REG_DLL << INTERNAL_REG_SUB_ADDR_SHIFT, BAUD_115200_DLL);
57 sc16is7xx_write_byte(REG_DLH << INTERNAL_REG_SUB_ADDR_SHIFT, BAUD_115200_DLH);
58
59 // Disable special register set
60 sc16is7xx_write_byte(REG_LCR << INTERNAL_REG_SUB_ADDR_SHIFT,
61 (UART_8_N_1 & ~LCR_SPEC_REG_SET_EN));
62 }
63