1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 /* 4 * NOTE: The layout of the global_nvs structure below must match the layout 5 * in soc/intel/apollolake/acpi/globalnvs.asl !!! 6 * 7 */ 8 9 #ifndef _SOC_APOLLOLAKE_NVS_H_ 10 #define _SOC_APOLLOLAKE_NVS_H_ 11 12 #include <stdint.h> 13 14 struct __packed global_nvs { 15 /* Miscellaneous */ 16 uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ 17 uint8_t ppcm; /* 0x01 - Max PPC State */ 18 uint8_t lids; /* 0x02 - LID State */ 19 uint8_t unused_was_pwrs; /* 0x03 - AC Power State */ 20 uint8_t dpte; /* 0x04 - Enable DPTF */ 21 uint32_t unused_was_cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ 22 uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ 23 uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ 24 uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ 25 uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ 26 uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ 27 uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ 28 uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */ 29 uint8_t uior; /* 0x2B - UART debug controller init on S3 30 resume */ 31 }; 32 33 #endif /* _SOC_APOLLOLAKE_NVS_H_ */ 34