xref: /aosp_15_r20/external/coreboot/src/soc/nvidia/tegra124/sdram.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <soc/addressmap.h>
7 #include <soc/clock.h>
8 #include <soc/emc.h>
9 #include <soc/mc.h>
10 #include <soc/pmc.h>
11 #include <soc/sdram.h>
12 #include <symbols.h>
13 
sdram_patch(uintptr_t addr,uint32_t value)14 static void sdram_patch(uintptr_t addr, uint32_t value)
15 {
16 	if (addr)
17 		write32((uint32_t *)addr, value);
18 }
19 
writebits(uint32_t value,uint32_t * addr,uint32_t mask)20 static void writebits(uint32_t value, uint32_t *addr, uint32_t mask)
21 {
22 	clrsetbits32(addr, mask, (value & mask));
23 }
24 
25 /* PMC must be configured before clock-enable and de-reset of MC/EMC. */
sdram_configure_pmc(const struct sdram_params * param,struct tegra_pmc_regs * regs)26 static void sdram_configure_pmc(const struct sdram_params *param,
27 				struct tegra_pmc_regs *regs)
28 {
29 	/* VDDP Select */
30 	write32(&regs->vddp_sel, param->PmcVddpSel);
31 	udelay(param->PmcVddpSelWait);
32 
33 	/* Set DDR pad voltage */
34 	writebits(param->PmcDdrPwr, &regs->ddr_pwr, PMC_DDR_PWR_VAL_MASK);
35 
36 	/* Set package and DPD pad control */
37 	writebits(param->PmcDdrCfg, &regs->ddr_cfg,
38 		  (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK |
39 		   PMC_DDR_CFG_XM0_RESET_TRI_MASK |
40 		   PMC_DDR_CFG_XM0_RESET_DPDIO_MASK));
41 
42 	/* Turn on MEM IO Power */
43 	writebits(param->PmcNoIoPower, &regs->no_iopower,
44 		  (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK));
45 
46 	write32(&regs->reg_short, param->PmcRegShort);
47 }
48 
sdram_start_clocks(const struct sdram_params * param)49 static void sdram_start_clocks(const struct sdram_params *param)
50 {
51 	u32 is_same_freq = (param->McEmemArbMisc0 &
52 			    MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0;
53 
54 	clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider,
55 		    param->PllMSelectDiv2, param->PllMSetupControl,
56 		    param->PllMPDLshiftPh45, param->PllMPDLshiftPh90,
57 		    param->PllMPDLshiftPh135, param->PllMKVCO,
58 		    param->PllMKCP, param->PllMStableTime,
59 		    param->EmcClockSource, is_same_freq);
60 }
61 
sdram_deassert_clock_enable_signal(const struct sdram_params * param,struct tegra_pmc_regs * regs)62 static void sdram_deassert_clock_enable_signal(const struct sdram_params *param,
63 					       struct tegra_pmc_regs *regs)
64 {
65 	clrbits32(&regs->por_dpd_ctrl,
66 		  PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK);
67 	udelay(param->PmcPorDpdCtrlWait);
68 }
69 
sdram_deassert_sel_dpd(const struct sdram_params * param,struct tegra_pmc_regs * regs)70 static void sdram_deassert_sel_dpd(const struct sdram_params *param,
71 				   struct tegra_pmc_regs *regs)
72 {
73 	clrbits32(&regs->por_dpd_ctrl,
74 		  (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK |
75 		   PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK));
76 	/*
77 	 * Note NVIDIA recommended to always do 10us delay here and ignore
78 	 * BCT.PmcPorDpdCtrlWait.
79 	 * */
80 	udelay(10);
81 }
82 
sdram_set_swizzle(const struct sdram_params * param,struct tegra_emc_regs * regs)83 static void sdram_set_swizzle(const struct sdram_params *param,
84 			      struct tegra_emc_regs *regs)
85 {
86 	write32(&regs->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg);
87 	write32(&regs->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0);
88 	write32(&regs->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1);
89 	write32(&regs->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2);
90 	write32(&regs->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3);
91 	write32(&regs->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg);
92 	write32(&regs->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0);
93 	write32(&regs->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1);
94 	write32(&regs->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2);
95 	write32(&regs->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3);
96 }
97 
sdram_set_pad_controls(const struct sdram_params * param,struct tegra_emc_regs * regs)98 static void sdram_set_pad_controls(const struct sdram_params *param,
99 				   struct tegra_emc_regs *regs)
100 {
101 	/* Program the pad controls */
102 	write32(&regs->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl);
103 	write32(&regs->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2);
104 	write32(&regs->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3);
105 	write32(&regs->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4);
106 	write32(&regs->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5);
107 
108 	write32(&regs->xm2dqspadctrl, param->EmcXm2DqsPadCtrl);
109 	write32(&regs->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2);
110 	write32(&regs->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3);
111 	write32(&regs->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4);
112 	write32(&regs->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5);
113 	write32(&regs->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6);
114 
115 	write32(&regs->xm2dqpadctrl, param->EmcXm2DqPadCtrl);
116 	write32(&regs->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2);
117 	write32(&regs->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3);
118 
119 	write32(&regs->xm2clkpadctrl, param->EmcXm2ClkPadCtrl);
120 	write32(&regs->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2);
121 
122 	write32(&regs->xm2comppadctrl, param->EmcXm2CompPadCtrl);
123 
124 	write32(&regs->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl);
125 	write32(&regs->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2);
126 	write32(&regs->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3);
127 
128 	write32(&regs->ctt_term_ctrl, param->EmcCttTermCtrl);
129 }
130 
sdram_trigger_emc_timing_update(struct tegra_emc_regs * regs)131 static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs)
132 {
133 	write32(&regs->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE);
134 }
135 
sdram_init_mc(const struct sdram_params * param,struct tegra_mc_regs * regs)136 static void sdram_init_mc(const struct sdram_params *param,
137 			  struct tegra_mc_regs *regs)
138 {
139 	/* Initialize MC VPR settings */
140 	write32(&regs->display_snap_ring, param->McDisplaySnapRing);
141 	write32(&regs->video_protect_bom, param->McVideoProtectBom);
142 	write32(&regs->video_protect_bom_adr_hi,
143 		param->McVideoProtectBomAdrHi);
144 	write32(&regs->video_protect_size_mb, param->McVideoProtectSizeMb);
145 	write32(&regs->video_protect_vpr_override,
146 		param->McVideoProtectVprOverride);
147 	write32(&regs->video_protect_vpr_override1,
148 		param->McVideoProtectVprOverride1);
149 	write32(&regs->video_protect_gpu_override_0,
150 		param->McVideoProtectGpuOverride0);
151 	write32(&regs->video_protect_gpu_override_1,
152 		param->McVideoProtectGpuOverride1);
153 
154 	/* Program SDRAM geometry paarameters */
155 	write32(&regs->emem_adr_cfg, param->McEmemAdrCfg);
156 	write32(&regs->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0);
157 	write32(&regs->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1);
158 
159 	/* Program bank swizzling */
160 	write32(&regs->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0);
161 	write32(&regs->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1);
162 	write32(&regs->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2);
163 	write32(&regs->emem_bank_swizzle_cfg3,
164 		param->McEmemAdrCfgBankSwizzle3);
165 
166 	/* Program external memory aperature (base and size) */
167 	write32(&regs->emem_cfg, param->McEmemCfg);
168 
169 	/* Program SEC carveout (base and size) */
170 	write32(&regs->sec_carveout_bom, param->McSecCarveoutBom);
171 	write32(&regs->sec_carveout_adr_hi, param->McSecCarveoutAdrHi);
172 	write32(&regs->sec_carveout_size_mb, param->McSecCarveoutSizeMb);
173 
174 	/* Program MTS carveout (base and size) */
175 	write32(&regs->mts_carveout_bom, param->McMtsCarveoutBom);
176 	write32(&regs->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi);
177 	write32(&regs->mts_carveout_size_mb, param->McMtsCarveoutSizeMb);
178 
179 	/* Program the memory arbiter */
180 	write32(&regs->emem_arb_cfg, param->McEmemArbCfg);
181 	write32(&regs->emem_arb_outstanding_req,
182 		param->McEmemArbOutstandingReq);
183 	write32(&regs->emem_arb_timing_rcd, param->McEmemArbTimingRcd);
184 	write32(&regs->emem_arb_timing_rp, param->McEmemArbTimingRp);
185 	write32(&regs->emem_arb_timing_rc, param->McEmemArbTimingRc);
186 	write32(&regs->emem_arb_timing_ras, param->McEmemArbTimingRas);
187 	write32(&regs->emem_arb_timing_faw, param->McEmemArbTimingFaw);
188 	write32(&regs->emem_arb_timing_rrd, param->McEmemArbTimingRrd);
189 	write32(&regs->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre);
190 	write32(&regs->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre);
191 	write32(&regs->emem_arb_timing_r2r, param->McEmemArbTimingR2R);
192 	write32(&regs->emem_arb_timing_w2w, param->McEmemArbTimingW2W);
193 	write32(&regs->emem_arb_timing_r2w, param->McEmemArbTimingR2W);
194 	write32(&regs->emem_arb_timing_w2r, param->McEmemArbTimingW2R);
195 	write32(&regs->emem_arb_da_turns, param->McEmemArbDaTurns);
196 	write32(&regs->emem_arb_da_covers, param->McEmemArbDaCovers);
197 	write32(&regs->emem_arb_misc0, param->McEmemArbMisc0);
198 	write32(&regs->emem_arb_misc1, param->McEmemArbMisc1);
199 	write32(&regs->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle);
200 	write32(&regs->emem_arb_override, param->McEmemArbOverride);
201 	write32(&regs->emem_arb_override_1, param->McEmemArbOverride1);
202 	write32(&regs->emem_arb_rsv, param->McEmemArbRsv);
203 
204 	/* Program extra snap levels for display client */
205 	write32(&regs->dis_extra_snap_levels, param->McDisExtraSnapLevels);
206 
207 	/* Trigger MC timing update */
208 	write32(&regs->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE);
209 
210 	/* Program second-level clock enable overrides */
211 	write32(&regs->clken_override, param->McClkenOverride);
212 
213 	/* Program statistics gathering */
214 	write32(&regs->stat_control, param->McStatControl);
215 }
216 
sdram_init_emc(const struct sdram_params * param,struct tegra_emc_regs * regs)217 static void sdram_init_emc(const struct sdram_params *param,
218 			   struct tegra_emc_regs *regs)
219 {
220 	/* Program SDRAM geometry parameters */
221 	write32(&regs->adr_cfg, param->EmcAdrCfg);
222 
223 	/* Program second-level clock enable overrides */
224 	write32(&regs->clken_override, param->EmcClkenOverride);
225 
226 	/* Program EMC pad auto calibration */
227 	write32(&regs->auto_cal_interval, param->EmcAutoCalInterval);
228 	write32(&regs->auto_cal_config2, param->EmcAutoCalConfig2);
229 	write32(&regs->auto_cal_config3, param->EmcAutoCalConfig3);
230 	write32(&regs->auto_cal_config, param->EmcAutoCalConfig);
231 	udelay(param->EmcAutoCalWait);
232 }
233 
sdram_set_emc_timing(const struct sdram_params * param,struct tegra_emc_regs * regs)234 static void sdram_set_emc_timing(const struct sdram_params *param,
235 				 struct tegra_emc_regs *regs)
236 {
237 	/* Program EMC timing configuration */
238 	write32(&regs->cfg_2, param->EmcCfg2);
239 	write32(&regs->cfg_pipe, param->EmcCfgPipe);
240 	write32(&regs->dbg, param->EmcDbg);
241 	write32(&regs->cmdq, param->EmcCmdQ);
242 	write32(&regs->mc2emcq, param->EmcMc2EmcQ);
243 	write32(&regs->mrs_wait_cnt, param->EmcMrsWaitCnt);
244 	write32(&regs->mrs_wait_cnt2, param->EmcMrsWaitCnt2);
245 	write32(&regs->fbio_cfg5, param->EmcFbioCfg5);
246 	write32(&regs->rc, param->EmcRc);
247 	write32(&regs->rfc, param->EmcRfc);
248 	write32(&regs->rfc_slr, param->EmcRfcSlr);
249 	write32(&regs->ras, param->EmcRas);
250 	write32(&regs->rp, param->EmcRp);
251 	write32(&regs->r2r, param->EmcR2r);
252 	write32(&regs->w2w, param->EmcW2w);
253 	write32(&regs->r2w, param->EmcR2w);
254 	write32(&regs->w2r, param->EmcW2r);
255 	write32(&regs->r2p, param->EmcR2p);
256 	write32(&regs->w2p, param->EmcW2p);
257 	write32(&regs->rd_rcd, param->EmcRdRcd);
258 	write32(&regs->wr_rcd, param->EmcWrRcd);
259 	write32(&regs->rrd, param->EmcRrd);
260 	write32(&regs->rext, param->EmcRext);
261 	write32(&regs->wext, param->EmcWext);
262 	write32(&regs->wdv, param->EmcWdv);
263 	write32(&regs->wdv_mask, param->EmcWdvMask);
264 	write32(&regs->quse, param->EmcQUse);
265 	write32(&regs->quse_width, param->EmcQuseWidth);
266 	write32(&regs->ibdly, param->EmcIbdly);
267 	write32(&regs->einput, param->EmcEInput);
268 	write32(&regs->einput_duration, param->EmcEInputDuration);
269 	write32(&regs->puterm_extra, param->EmcPutermExtra);
270 	write32(&regs->puterm_width, param->EmcPutermWidth);
271 	write32(&regs->puterm_adj, param->EmcPutermAdj);
272 	write32(&regs->cdb_cntl_1, param->EmcCdbCntl1);
273 	write32(&regs->cdb_cntl_2, param->EmcCdbCntl2);
274 	write32(&regs->cdb_cntl_3, param->EmcCdbCntl3);
275 	write32(&regs->qrst, param->EmcQRst);
276 	write32(&regs->qsafe, param->EmcQSafe);
277 	write32(&regs->rdv, param->EmcRdv);
278 	write32(&regs->rdv_mask, param->EmcRdvMask);
279 	write32(&regs->qpop, param->EmcQpop);
280 	write32(&regs->ctt, param->EmcCtt);
281 	write32(&regs->ctt_duration, param->EmcCttDuration);
282 	write32(&regs->refresh, param->EmcRefresh);
283 	write32(&regs->burst_refresh_num, param->EmcBurstRefreshNum);
284 	write32(&regs->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt);
285 	write32(&regs->pdex2wr, param->EmcPdEx2Wr);
286 	write32(&regs->pdex2rd, param->EmcPdEx2Rd);
287 	write32(&regs->pchg2pden, param->EmcPChg2Pden);
288 	write32(&regs->act2pden, param->EmcAct2Pden);
289 	write32(&regs->ar2pden, param->EmcAr2Pden);
290 	write32(&regs->rw2pden, param->EmcRw2Pden);
291 	write32(&regs->txsr, param->EmcTxsr);
292 	write32(&regs->txsrdll, param->EmcTxsrDll);
293 	write32(&regs->tcke, param->EmcTcke);
294 	write32(&regs->tckesr, param->EmcTckesr);
295 	write32(&regs->tpd, param->EmcTpd);
296 	write32(&regs->tfaw, param->EmcTfaw);
297 	write32(&regs->trpab, param->EmcTrpab);
298 	write32(&regs->tclkstable, param->EmcTClkStable);
299 	write32(&regs->tclkstop, param->EmcTClkStop);
300 	write32(&regs->trefbw, param->EmcTRefBw);
301 	write32(&regs->odt_write, param->EmcOdtWrite);
302 	write32(&regs->odt_read, param->EmcOdtRead);
303 	write32(&regs->fbio_cfg6, param->EmcFbioCfg6);
304 	write32(&regs->cfg_dig_dll, param->EmcCfgDigDll);
305 	write32(&regs->cfg_dig_dll_period, param->EmcCfgDigDllPeriod);
306 
307 	/* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */
308 	write32(&regs->fbio_spare, param->EmcFbioSpare & 0xfffffffd);
309 
310 	write32(&regs->cfg_rsv, param->EmcCfgRsv);
311 	write32(&regs->dll_xform_dqs0, param->EmcDllXformDqs0);
312 	write32(&regs->dll_xform_dqs1, param->EmcDllXformDqs1);
313 	write32(&regs->dll_xform_dqs2, param->EmcDllXformDqs2);
314 	write32(&regs->dll_xform_dqs3, param->EmcDllXformDqs3);
315 	write32(&regs->dll_xform_dqs4, param->EmcDllXformDqs4);
316 	write32(&regs->dll_xform_dqs5, param->EmcDllXformDqs5);
317 	write32(&regs->dll_xform_dqs6, param->EmcDllXformDqs6);
318 	write32(&regs->dll_xform_dqs7, param->EmcDllXformDqs7);
319 	write32(&regs->dll_xform_dqs8, param->EmcDllXformDqs8);
320 	write32(&regs->dll_xform_dqs9, param->EmcDllXformDqs9);
321 	write32(&regs->dll_xform_dqs10, param->EmcDllXformDqs10);
322 	write32(&regs->dll_xform_dqs11, param->EmcDllXformDqs11);
323 	write32(&regs->dll_xform_dqs12, param->EmcDllXformDqs12);
324 	write32(&regs->dll_xform_dqs13, param->EmcDllXformDqs13);
325 	write32(&regs->dll_xform_dqs14, param->EmcDllXformDqs14);
326 	write32(&regs->dll_xform_dqs15, param->EmcDllXformDqs15);
327 	write32(&regs->dll_xform_quse0, param->EmcDllXformQUse0);
328 	write32(&regs->dll_xform_quse1, param->EmcDllXformQUse1);
329 	write32(&regs->dll_xform_quse2, param->EmcDllXformQUse2);
330 	write32(&regs->dll_xform_quse3, param->EmcDllXformQUse3);
331 	write32(&regs->dll_xform_quse4, param->EmcDllXformQUse4);
332 	write32(&regs->dll_xform_quse5, param->EmcDllXformQUse5);
333 	write32(&regs->dll_xform_quse6, param->EmcDllXformQUse6);
334 	write32(&regs->dll_xform_quse7, param->EmcDllXformQUse7);
335 	write32(&regs->dll_xform_quse8, param->EmcDllXformQUse8);
336 	write32(&regs->dll_xform_quse9, param->EmcDllXformQUse9);
337 	write32(&regs->dll_xform_quse10, param->EmcDllXformQUse10);
338 	write32(&regs->dll_xform_quse11, param->EmcDllXformQUse11);
339 	write32(&regs->dll_xform_quse12, param->EmcDllXformQUse12);
340 	write32(&regs->dll_xform_quse13, param->EmcDllXformQUse13);
341 	write32(&regs->dll_xform_quse14, param->EmcDllXformQUse14);
342 	write32(&regs->dll_xform_quse15, param->EmcDllXformQUse15);
343 	write32(&regs->dll_xform_dq0, param->EmcDllXformDq0);
344 	write32(&regs->dll_xform_dq1, param->EmcDllXformDq1);
345 	write32(&regs->dll_xform_dq2, param->EmcDllXformDq2);
346 	write32(&regs->dll_xform_dq3, param->EmcDllXformDq3);
347 	write32(&regs->dll_xform_dq4, param->EmcDllXformDq4);
348 	write32(&regs->dll_xform_dq5, param->EmcDllXformDq5);
349 	write32(&regs->dll_xform_dq6, param->EmcDllXformDq6);
350 	write32(&regs->dll_xform_dq7, param->EmcDllXformDq7);
351 	write32(&regs->dll_xform_addr0, param->EmcDllXformAddr0);
352 	write32(&regs->dll_xform_addr1, param->EmcDllXformAddr1);
353 	write32(&regs->dll_xform_addr2, param->EmcDllXformAddr2);
354 	write32(&regs->dll_xform_addr3, param->EmcDllXformAddr3);
355 	write32(&regs->dll_xform_addr4, param->EmcDllXformAddr4);
356 	write32(&regs->dll_xform_addr5, param->EmcDllXformAddr5);
357 	write32(&regs->acpd_control, param->EmcAcpdControl);
358 	write32(&regs->dsr_vttgen_drv, param->EmcDsrVttgenDrv);
359 	write32(&regs->txdsrvttgen, param->EmcTxdsrvttgen);
360 	write32(&regs->bgbias_ctl0, param->EmcBgbiasCtl0);
361 
362 	/*
363 	 * Set pipe bypass enable bits before sending any DRAM commands.
364 	 * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured.
365 	 */
366 	writebits(param->EmcCfg, &regs->cfg,
367 		  (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK |
368 		   EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK |
369 		   EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK));
370 }
371 
sdram_patch_bootrom(const struct sdram_params * param,struct tegra_mc_regs * regs)372 static void sdram_patch_bootrom(const struct sdram_params *param,
373 				struct tegra_mc_regs *regs)
374 {
375 	if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) {
376 		uintptr_t addr = ((param->BootRomPatchControl &
377 				  BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >>
378 				  BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT);
379 		addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2);
380 		write32((uint32_t *)addr, param->BootRomPatchData);
381 		write32(&regs->timing_control, 1);
382 	}
383 }
384 
sdram_set_dpd3(const struct sdram_params * param,struct tegra_pmc_regs * regs)385 static void sdram_set_dpd3(const struct sdram_params *param,
386 			   struct tegra_pmc_regs *regs)
387 {
388 	/* Program DPD request */
389 	write32(&regs->io_dpd3_req, param->PmcIoDpd3Req);
390 	udelay(param->PmcIoDpd3ReqWait);
391 }
392 
sdram_set_dli_trims(const struct sdram_params * param,struct tegra_emc_regs * regs)393 static void sdram_set_dli_trims(const struct sdram_params *param,
394 				struct tegra_emc_regs *regs)
395 {
396 	/* Program DLI trims */
397 	write32(&regs->dli_trim_txdqs0, param->EmcDliTrimTxDqs0);
398 	write32(&regs->dli_trim_txdqs1, param->EmcDliTrimTxDqs1);
399 	write32(&regs->dli_trim_txdqs2, param->EmcDliTrimTxDqs2);
400 	write32(&regs->dli_trim_txdqs3, param->EmcDliTrimTxDqs3);
401 	write32(&regs->dli_trim_txdqs4, param->EmcDliTrimTxDqs4);
402 	write32(&regs->dli_trim_txdqs5, param->EmcDliTrimTxDqs5);
403 	write32(&regs->dli_trim_txdqs6, param->EmcDliTrimTxDqs6);
404 	write32(&regs->dli_trim_txdqs7, param->EmcDliTrimTxDqs7);
405 	write32(&regs->dli_trim_txdqs8, param->EmcDliTrimTxDqs8);
406 	write32(&regs->dli_trim_txdqs9, param->EmcDliTrimTxDqs9);
407 	write32(&regs->dli_trim_txdqs10, param->EmcDliTrimTxDqs10);
408 	write32(&regs->dli_trim_txdqs11, param->EmcDliTrimTxDqs11);
409 	write32(&regs->dli_trim_txdqs12, param->EmcDliTrimTxDqs12);
410 	write32(&regs->dli_trim_txdqs13, param->EmcDliTrimTxDqs13);
411 	write32(&regs->dli_trim_txdqs14, param->EmcDliTrimTxDqs14);
412 	write32(&regs->dli_trim_txdqs15, param->EmcDliTrimTxDqs15);
413 
414 	write32(&regs->ca_training_timing_cntl1,
415 		param->EmcCaTrainingTimingCntl1);
416 	write32(&regs->ca_training_timing_cntl2,
417 		param->EmcCaTrainingTimingCntl2);
418 
419 	sdram_trigger_emc_timing_update(regs);
420 	udelay(param->EmcTimingControlWait);
421 }
422 
sdram_set_clock_enable_signal(const struct sdram_params * param,struct tegra_emc_regs * regs)423 static void sdram_set_clock_enable_signal(const struct sdram_params *param,
424 					  struct tegra_emc_regs *regs)
425 {
426 	volatile uint32_t dummy = 0;
427 	clrbits32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
428 			       EMC_PIN_CKE_MASK));
429 	/*
430 	 * Assert dummy read of PIN register to ensure above write to PIN
431 	 * register went through. 200 is the recommended value by NVIDIA.
432 	 */
433 	dummy |= read32(&regs->pin);
434 	udelay(200 + param->EmcPinExtraWait);
435 
436 	/* Deassert reset */
437 	setbits32(&regs->pin, EMC_PIN_RESET_INACTIVE);
438 	/*
439 	 * Assert dummy read of PIN register to ensure above write to PIN
440 	 * register went through. 200 is the recommended value by NVIDIA.
441 	 */
442 	dummy |= read32(&regs->pin);
443 	udelay(500 + param->EmcPinExtraWait);
444 
445 	/* Enable clock enable signal */
446 	setbits32(&regs->pin, EMC_PIN_CKE_NORMAL);
447 	/*
448 	 * Assert dummy read of PIN register to ensure above write to PIN
449 	 * register went through. 200 is the recommended value by NVIDIA.
450 	 */
451 	dummy |= read32(&regs->pin);
452 	udelay(param->EmcPinProgramWait);
453 
454 	if (!dummy) {
455 		die("Failed to program EMC pin.");
456 	}
457 
458 	/* Send NOP (trigger) */
459 	writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) |
460 		   (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)),
461 		  &regs->nop,
462 		  EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK);
463 
464 	/* Write mode registers */
465 	write32(&regs->emrs2, param->EmcEmrs2);
466 	write32(&regs->emrs3, param->EmcEmrs3);
467 	write32(&regs->emrs, param->EmcEmrs);
468 	write32(&regs->mrs, param->EmcMrs);
469 
470 	if (param->EmcExtraModeRegWriteEnable) {
471 		write32(&regs->mrs, param->EmcMrwExtra);
472 	}
473 }
474 
sdram_init_zq_calibration(const struct sdram_params * param,struct tegra_emc_regs * regs)475 static void sdram_init_zq_calibration(const struct sdram_params *param,
476 				      struct tegra_emc_regs *regs)
477 {
478 	if ((param->EmcZcalWarmColdBootEnables &
479 	     EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) {
480 		/* Need to initialize ZCAL on coldboot. */
481 		write32(&regs->zq_cal, param->EmcZcalInitDev0);
482 		udelay(param->EmcZcalInitWait);
483 
484 		if ((param->EmcDevSelect & 2) == 0) {
485 			write32(&regs->zq_cal, param->EmcZcalInitDev1);
486 			udelay(param->EmcZcalInitWait);
487 		}
488 	} else {
489 		udelay(param->EmcZcalInitWait);
490 	}
491 }
492 
sdram_set_zq_calibration(const struct sdram_params * param,struct tegra_emc_regs * regs)493 static void sdram_set_zq_calibration(const struct sdram_params *param,
494 				     struct tegra_emc_regs *regs)
495 {
496 	/* Start periodic ZQ calibration */
497 	write32(&regs->zcal_interval, param->EmcZcalInterval);
498 	write32(&regs->zcal_wait_cnt, param->EmcZcalWaitCnt);
499 	write32(&regs->zcal_mrw_cmd, param->EmcZcalMrwCmd);
500 }
501 
sdram_set_refresh(const struct sdram_params * param,struct tegra_emc_regs * regs)502 static void sdram_set_refresh(const struct sdram_params *param,
503 			      struct tegra_emc_regs *regs)
504 {
505 	/* Insert burst refresh */
506 	if (param->EmcExtraRefreshNum > 0) {
507 		uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1;
508 		writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED |
509 			   (refresh_num << EMC_REF_NUM_SHIFT) |
510 			   (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)),
511 			  &regs->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK |
512 				       EMC_REF_NUM_MASK |
513 				       EMC_REF_DEV_SELECTN_MASK));
514 	}
515 
516 	/* Enable refresh */
517 	write32(&regs->refctrl,
518 		(param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED));
519 
520 	write32(&regs->dyn_self_ref_control, param->EmcDynSelfRefControl);
521 	write32(&regs->cfg, param->EmcCfg);
522 	write32(&regs->sel_dpd_ctrl, param->EmcSelDpdCtrl);
523 
524 	/* Write addr swizzle lock bit */
525 	write32(&regs->fbio_spare, param->EmcFbioSpare);
526 
527 	/* Re-trigger timing to latch power saving functions */
528 	sdram_trigger_emc_timing_update(regs);
529 }
530 
sdram_enable_arbiter(const struct sdram_params * param)531 static void sdram_enable_arbiter(const struct sdram_params *param)
532 {
533 	/* TODO(hungte) Move values here to standalone header file. */
534 	uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0);
535 	setbits32(AHB_ARBITRATION_XBAR_CTRL,
536 		  param->AhbArbitrationXbarCtrlMemInitDone << 16);
537 }
538 
sdram_lock_carveouts(const struct sdram_params * param,struct tegra_mc_regs * regs)539 static void sdram_lock_carveouts(const struct sdram_params *param,
540 				 struct tegra_mc_regs *regs)
541 {
542 	/* Lock carveouts, and emem_cfg registers */
543 	write32(&regs->video_protect_reg_ctrl,
544 		param->McVideoProtectWriteAccess);
545 	write32(&regs->emem_cfg_access_ctrl,
546 		MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED);
547 	write32(&regs->sec_carveout_reg_ctrl,
548 		param->McSecCarveoutProtectWriteAccess);
549 	write32(&regs->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl);
550 }
551 
sdram_init(const struct sdram_params * param)552 void sdram_init(const struct sdram_params *param)
553 {
554 	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
555 	struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE;
556 	struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE;
557 
558 	printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n",
559 		param->MemoryType, clock_get_pll_input_khz() *
560 		param->PllMFeedbackDivider / param->PllMInputDivider /
561 		(1 + param->PllMSelectDiv2));
562 	if (param->MemoryType != NvBootMemoryType_Ddr3)
563 		die("Unsupported memory type!\n");
564 
565 	sdram_configure_pmc(param, pmc);
566 	sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1);
567 
568 	sdram_start_clocks(param);
569 	sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3);
570 
571 	sdram_deassert_sel_dpd(param, pmc);
572 	sdram_set_swizzle(param, emc);
573 	sdram_set_pad_controls(param, emc);
574 	sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5);
575 
576 	sdram_trigger_emc_timing_update(emc);
577 	sdram_init_mc(param, mc);
578 	sdram_init_emc(param, emc);
579 	sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7);
580 
581 	sdram_set_emc_timing(param, emc);
582 	sdram_patch_bootrom(param, mc);
583 	sdram_set_dpd3(param, pmc);
584 	sdram_set_dli_trims(param, emc);
585 	sdram_deassert_clock_enable_signal(param, pmc);
586 	sdram_set_clock_enable_signal(param, emc);
587 	sdram_init_zq_calibration(param, emc);
588 	sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9);
589 
590 	sdram_set_zq_calibration(param, emc);
591 	sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11);
592 
593 	sdram_trigger_emc_timing_update(emc);
594 	sdram_set_refresh(param, emc);
595 	sdram_enable_arbiter(param);
596 	sdram_lock_carveouts(param, mc);
597 
598 	sdram_lp0_save_params(param);
599 }
600 
sdram_get_ram_code(void)601 uint32_t sdram_get_ram_code(void)
602 {
603 	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
604 	return ((read32(&pmc->strapping_opt_a) &
605 		 PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
606 		PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
607 }
608 
609 /* returns total amount of DRAM (in MB) from memory controller registers */
sdram_size_mb(void)610 int sdram_size_mb(void)
611 {
612 	struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE;
613 	static int total_size = 0;
614 
615 	if (total_size)
616 		return total_size;
617 
618 	/*
619 	 * This obtains memory size from the External Memory Aperture
620 	 * Configuration register. Nvidia confirmed that it is safe to assume
621 	 * this value represents the total physical DRAM size.
622 	 */
623 	total_size = (read32(&mc->emem_cfg) >>
624 			MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK;
625 
626 	printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size);
627 	return total_size;
628 }
629 
sdram_max_addressable_mb(void)630 uintptr_t sdram_max_addressable_mb(void)
631 {
632 	return MIN(((uintptr_t)_dram/MiB) + sdram_size_mb(), 4096);
633 }
634