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Searched defs:sdram_params (Results 1 – 17 of 17) sorted by relevance

/aosp_15_r20/external/coreboot/src/soc/nvidia/tegra210/include/soc/
H A Dsdram_param.h56 struct sdram_params { struct
58 uint32_t MemoryType;
63 uint32_t PllMInputDivider;
65 uint32_t PllMFeedbackDivider;
67 uint32_t PllMStableTime;
69 uint32_t PllMSetupControl;
71 uint32_t PllMPostDivider;
73 uint32_t PllMKCP;
75 uint32_t PllMKVCO;
77 uint32_t EmcBctSpare0;
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/aosp_15_r20/external/coreboot/src/soc/nvidia/tegra124/include/soc/
H A Dsdram_param.h53 struct sdram_params { struct
55 uint32_t MemoryType;
60 uint32_t PllMInputDivider;
62 uint32_t PllMFeedbackDivider;
64 uint32_t PllMStableTime;
66 uint32_t PllMSetupControl;
68 uint32_t PllMSelectDiv2;
70 uint32_t PllMPDLshiftPh45;
72 uint32_t PllMPDLshiftPh90;
74 uint32_t PllMPDLshiftPh135;
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/aosp_15_r20/external/coreboot/src/soc/mediatek/mt8188/include/soc/
H A Ddramc_param.h23 struct sdram_params { struct
25 u32 rank_num;
26 u32 dram_cbt_mode;
28 u16 delay_cell_timex100;
29 u8 u18ph_dly;
32 s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
33 s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
34 s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
35 s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP4 + 1];
36 s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
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/aosp_15_r20/external/coreboot/src/soc/mediatek/mt8183/include/soc/
H A Demi.h15 struct sdram_params { struct
16 u16 source; /* DRAMC_PARAM_SOURCE */
17 u16 frequency;
18 u32 rank_num;
19 u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */
20 u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
23 s8 duty_clk_delay[CHANNEL_MAX];
24 s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER];
27 u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
28 u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
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/aosp_15_r20/external/coreboot/src/soc/mediatek/mt8195/include/soc/
H A Ddramc_param.h18 struct sdram_params { struct
19 u32 rank_num;
20 u16 num_dlycell_perT;
21 u16 delay_cell_timex100;
24 s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
25 s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
26 s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
27 s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
28 s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
31 u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
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/aosp_15_r20/external/coreboot/src/soc/mediatek/mt8186/include/soc/
H A Ddramc_param.h18 struct sdram_params { struct
24 u32 rank_num;
25 u16 num_dlycell_perT;
26 u16 delay_cell_timex100;
29 s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
30 s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
31 s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
32 s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
35 u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
36 u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
[all …]
/aosp_15_r20/external/coreboot/src/soc/mediatek/mt8192/include/soc/
H A Ddramc_param.h18 struct sdram_params { struct
19 u32 rank_num;
20 u16 num_dlycell_perT;
21 u16 delay_cell_timex100;
24 s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
25 s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
26 s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
27 s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
28 s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
31 u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
[all …]
/aosp_15_r20/external/trusty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c185 struct rk3399_sdram_params *sdram_params, in data_training()
430 struct rk3399_sdram_params *sdram_params, in set_ddrconfig()
453 struct rk3399_sdram_params *sdram_params) in dram_all_config()
490 struct rk3399_sdram_params *sdram_params) in pctl_cfg()
547 struct rk3399_sdram_params *sdram_params) in dram_switch_to_next_index()
588 struct rk3399_sdram_params *sdram_params) in pctl_start()
696 struct rk3399_sdram_params *sdram_params = &sdram_config; in dmc_suspend() local
785 struct rk3399_sdram_params *sdram_params = &sdram_config; in dmc_resume() local
Ddfs.c181 struct rk3399_sdram_params *sdram_params, in sdram_timing_cfg_init()
/aosp_15_r20/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c185 struct rk3399_sdram_params *sdram_params, in data_training()
430 struct rk3399_sdram_params *sdram_params, in set_ddrconfig()
453 struct rk3399_sdram_params *sdram_params) in dram_all_config()
490 struct rk3399_sdram_params *sdram_params) in pctl_cfg()
547 struct rk3399_sdram_params *sdram_params) in dram_switch_to_next_index()
588 struct rk3399_sdram_params *sdram_params) in pctl_start()
696 struct rk3399_sdram_params *sdram_params = &sdram_config; in dmc_suspend() local
785 struct rk3399_sdram_params *sdram_params = &sdram_config; in dmc_resume() local
H A Ddfs.c181 struct rk3399_sdram_params *sdram_params, in sdram_timing_cfg_init()
/aosp_15_r20/external/coreboot/src/soc/mediatek/mt8173/
H A Ddramc_pi_basic_api.c25 const struct mt8173_sdram_params *sdram_params) in is_dual_rank()
292 void mem_pll_init(const struct mt8173_sdram_params *sdram_params) in mem_pll_init()
392 void dramc_pre_init(u32 channel, const struct mt8173_sdram_params *sdram_params) in dramc_pre_init()
431 const struct mt8173_sdram_params *sdram_params) in dramc_set_mrs_value()
447 void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) in dramc_init()
677 const struct mt8173_sdram_params *sdram_params) in dramc_runtime_config()
H A Ddramc_pi_calibration_api.c17 const struct mt8173_sdram_params *sdram_params) in sw_impedance_cal()
46 void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params) in ca_training()
129 void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params) in write_leveling()
342 const struct mt8173_sdram_params *sdram_params) in rx_dqs_gating_cal()
396 const struct mt8173_sdram_params *sdram_params) in dual_rank_rx_dqs_gating_cal()
427 const struct mt8173_sdram_params *sdram_params) in dramc_rankinctl_config()
652 const struct mt8173_sdram_params *sdram_params) in dual_rank_rx_datlat_cal()
695 const struct mt8173_sdram_params *sdram_params) in rx_datlat_cal()
H A Demi.c32 static void emi_init(const struct mt8173_sdram_params *sdram_params) in emi_init()
66 static void do_calib(const struct mt8173_sdram_params *sdram_params) in do_calib()
104 static void init_dram(const struct mt8173_sdram_params *sdram_params) in init_dram()
164 void mt_set_emi(const struct mt8173_sdram_params *sdram_params) in mt_set_emi()
H A Dmemory.c12 void mt_mem_init(const struct mt8173_sdram_params *sdram_params) in mt_mem_init()
H A Dpll.c425 void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params) in mt_mem_pll_config_pre()
/aosp_15_r20/external/coreboot/src/soc/rockchip/rk3288/
H A Dsdram.c580 const struct rk3288_sdram_params *sdram_params) in pctl_cfg()
630 static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) in phy_cfg()
803 const struct rk3288_sdram_params *sdram_params) in data_training()
911 const struct rk3288_sdram_params *sdram_params) in dram_cfg_rbc()
924 static void dram_all_config(const struct rk3288_sdram_params *sdram_params) in dram_all_config()
951 void sdram_init(const struct rk3288_sdram_params *sdram_params) in sdram_init()