1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _AMD_FW_TOOL_H_ 4 #define _AMD_FW_TOOL_H_ 5 6 #include <commonlib/bsd/compiler.h> 7 #include <commonlib/bsd/helpers.h> 8 #include <openssl/sha.h> 9 #include <stdint.h> 10 #include <stdbool.h> 11 12 #define ERASE_ALIGNMENT 0x1000U 13 #define TABLE_ALIGNMENT 0x1000U 14 #define BLOB_ALIGNMENT 0x100U 15 #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) 16 #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) 17 18 enum platform { 19 PLATFORM_UNKNOWN, 20 PLATFORM_CARRIZO, 21 PLATFORM_STONEYRIDGE, 22 PLATFORM_RAVEN, 23 PLATFORM_PICASSO, 24 PLATFORM_RENOIR, 25 PLATFORM_CEZANNE, 26 PLATFORM_MENDOCINO, 27 PLATFORM_LUCIENNE, 28 PLATFORM_PHOENIX, 29 PLATFORM_GLINDA, 30 PLATFORM_GENOA, 31 }; 32 33 typedef enum _amd_fw_type { 34 AMD_FW_PSP_PUBKEY = 0x00, 35 AMD_FW_PSP_BOOTLOADER = 0x01, 36 AMD_FW_PSP_SECURED_OS = 0x02, 37 AMD_FW_PSP_RECOVERY = 0x03, 38 AMD_FW_PSP_NVRAM = 0x04, 39 AMD_FW_PSP_RTM_PUBKEY = 0x05, 40 AMD_FW_PSP_SMU_FIRMWARE = 0x08, 41 AMD_FW_PSP_SECURED_DEBUG = 0x09, 42 AMD_FW_ABL_PUBKEY = 0x0a, 43 AMD_PSP_FUSE_CHAIN = 0x0b, 44 AMD_FW_PSP_TRUSTLETS = 0x0c, 45 AMD_FW_PSP_TRUSTLETKEY = 0x0d, 46 AMD_FW_PSP_SMU_FIRMWARE2 = 0x12, 47 AMD_DEBUG_UNLOCK = 0x13, 48 AMD_BOOT_DRIVER = 0x1b, 49 AMD_SOC_DRIVER = 0x1c, 50 AMD_DEBUG_DRIVER = 0x1d, 51 AMD_INTERFACE_DRIVER = 0x1f, 52 AMD_HW_IPCFG = 0x20, 53 AMD_WRAPPED_IKEK = 0x21, 54 AMD_TOKEN_UNLOCK = 0x22, 55 AMD_SEC_GASKET = 0x24, 56 AMD_MP2_FW = 0x25, 57 AMD_DRIVER_ENTRIES = 0x28, 58 AMD_FW_KVM_IMAGE = 0x29, 59 AMD_FW_MP5 = 0x2a, 60 AMD_S0I3_DRIVER = 0x2d, 61 AMD_ABL0 = 0x30, 62 AMD_ABL1 = 0x31, 63 AMD_ABL2 = 0x32, 64 AMD_ABL3 = 0x33, 65 AMD_ABL4 = 0x34, 66 AMD_ABL5 = 0x35, 67 AMD_ABL6 = 0x36, 68 AMD_ABL7 = 0x37, 69 AMD_SEV_DATA = 0x38, 70 AMD_SEV_CODE = 0x39, 71 AMD_FW_PSP_WHITELIST = 0x3a, 72 AMD_VBIOS_BTLOADER = 0x3c, 73 AMD_FW_L2_PTR = 0x40, 74 AMD_FW_DXIO = 0x42, 75 AMD_FW_USB_PHY = 0x44, 76 AMD_FW_TOS_SEC_POLICY = 0x45, 77 AMD_FW_DRTM_TA = 0x47, 78 AMD_FW_RECOVERYAB_A = 0x48, 79 AMD_FW_RECOVERYAB_B = 0x4A, 80 AMD_FW_BIOS_TABLE = 0x49, 81 AMD_FW_KEYDB_BL = 0x50, 82 AMD_FW_KEYDB_TOS = 0x51, 83 AMD_FW_PSP_VERSTAGE = 0x52, 84 AMD_FW_VERSTAGE_SIG = 0x53, 85 AMD_RPMC_NVRAM = 0x54, 86 AMD_FW_SPL = 0x55, 87 AMD_FW_DMCU_ERAM = 0x58, 88 AMD_FW_DMCU_ISR = 0x59, 89 AMD_FW_MSMU = 0x5a, 90 AMD_FW_SPIROM_CFG = 0x5c, 91 AMD_FW_MPIO = 0x5d, 92 AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */ 93 AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */ 94 AMD_FW_DMCUB = 0x71, 95 AMD_FW_PSP_BOOTLOADER_AB = 0x73, 96 AMD_RIB = 0x76, 97 AMD_FW_AMF_SRAM = 0x85, 98 AMD_FW_AMF_DRAM = 0x86, 99 AMD_FW_AMF_WLAN = 0x88, 100 AMD_FW_AMF_MFD = 0x89, 101 AMD_FW_MPDMA_TF = 0x8c, 102 AMD_TA_IKEK = 0x8d, 103 AMD_FW_MPCCX = 0x90, 104 AMD_FW_GMI3_PHY = 0x91, 105 AMD_FW_MPDMA_PM = 0x92, 106 AMD_FW_LSDMA = 0x94, 107 AMD_FW_C20_MP = 0x95, 108 AMD_FW_FCFG_TABLE = 0x98, 109 AMD_FW_MINIMSMU = 0x9a, 110 AMD_FW_SRAM_FW_EXT = 0x9d, 111 AMD_FW_UMSMU = 0xa2, 112 AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ 113 AMD_FW_GEC, 114 AMD_FW_XHCI, 115 AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ 116 AMD_FW_SKIP /* This is for non-applicable options. */ 117 } amd_fw_type; 118 119 typedef enum _amd_bios_type { 120 AMD_BIOS_RTM_PUBKEY = 0x05, 121 AMD_BIOS_SIG = 0x07, 122 AMD_BIOS_APCB = 0x60, 123 AMD_BIOS_APOB = 0x61, 124 AMD_BIOS_BIN = 0x62, 125 AMD_BIOS_APOB_NV = 0x63, 126 AMD_BIOS_PMUI = 0x64, 127 AMD_BIOS_PMUD = 0x65, 128 AMD_BIOS_UCODE = 0x66, 129 AMD_BIOS_APCB_BK = 0x68, 130 AMD_BIOS_EARLY_VGA = 0x69, 131 AMD_BIOS_MP2_CFG = 0x6a, 132 AMD_BIOS_PSP_SHARED_MEM = 0x6b, 133 AMD_BIOS_L2_PTR = 0x70, 134 AMD_BIOS_INVALID, 135 AMD_BIOS_SKIP 136 } amd_bios_type; 137 138 typedef enum _amd_addr_mode { 139 AMD_ADDR_PHYSICAL = 0, /* Physical address */ 140 AMD_ADDR_REL_BIOS, /* Relative to beginning of image */ 141 AMD_ADDR_REL_TAB, /* Relative to table */ 142 AMD_ADDR_REL_SLOT, /* Relative to slot */ 143 } amd_addr_mode; 144 145 struct second_gen_efs { /* todo: expand for Server products */ 146 uint32_t gen:1; /* Client products only use bit 0 */ 147 uint32_t reserved:31; 148 } __attribute__((packed)); 149 150 #define EFS_SECOND_GEN 0 151 #define EFS_BEFORE_SECOND_GEN 1 152 153 typedef struct _embedded_firmware { 154 uint32_t signature; /* 0x55aa55aa */ 155 uint32_t imc_entry; 156 uint32_t gec_entry; 157 uint32_t xhci_entry; 158 uint32_t psp_directory; 159 uint32_t new_psp_directory; /* also used as combo_psp_directory */ 160 uint32_t bios0_entry; /* todo: add way to select correct entry */ 161 uint32_t bios1_entry; 162 uint32_t bios2_entry; 163 struct second_gen_efs efs_gen; 164 uint32_t bios3_entry; 165 uint32_t reserved_2Ch; 166 uint32_t promontory_fw_ptr; 167 uint32_t lp_promontory_fw_ptr; 168 uint32_t reserved_38h; 169 uint32_t reserved_3Ch; 170 uint8_t spi_readmode_f15_mod_60_6f; 171 uint8_t fast_speed_new_f15_mod_60_6f; 172 uint8_t reserved_42h; 173 uint8_t spi_readmode_f17_mod_00_2f; 174 uint8_t spi_fastspeed_f17_mod_00_2f; 175 uint8_t qpr_dummy_cycle_f17_mod_00_2f; 176 uint8_t reserved_46h; 177 uint8_t spi_readmode_f17_mod_30_3f; 178 uint8_t spi_fastspeed_f17_mod_30_3f; 179 uint8_t micron_detect_f17_mod_30_3f; 180 uint8_t reserved_4Ah; 181 uint8_t reserved_4Bh; 182 uint32_t reserved_4Ch; 183 } __attribute__((packed, aligned(16))) embedded_firmware; 184 185 typedef struct _psp_directory_header { 186 uint32_t cookie; 187 uint32_t checksum; 188 uint32_t num_entries; 189 union { 190 uint32_t additional_info; 191 struct { 192 uint32_t dir_size:10; 193 uint32_t spi_block_size:4; 194 uint32_t base_addr:15; 195 uint32_t address_mode:2; 196 uint32_t not_used:1; 197 } __attribute__((packed)) additional_info_fields; 198 }; 199 } __attribute__((packed, aligned(16))) psp_directory_header; 200 201 typedef struct _psp_directory_entry { 202 uint8_t type; 203 uint8_t subprog; 204 union { 205 uint16_t rsvd; 206 struct { 207 uint8_t rom_id:2; 208 uint8_t writable:1; 209 uint8_t inst:4; 210 uint8_t rsvd_1:1; 211 uint8_t rsvd_2:8; 212 } __attribute__((packed)); 213 }; 214 uint32_t size; 215 uint64_t addr:62; /* or a value in some cases */ 216 uint64_t address_mode:2; 217 } __attribute__((packed)) psp_directory_entry; 218 219 typedef struct _psp_directory_table { 220 psp_directory_header header; 221 psp_directory_entry entries[]; 222 } __attribute__((packed, aligned(16))) psp_directory_table; 223 224 #define MAX_PSP_ENTRIES 0xff 225 226 typedef struct _psp_combo_header { 227 uint32_t cookie; 228 uint32_t checksum; 229 uint32_t num_entries; 230 uint32_t lookup; 231 uint64_t reserved[2]; 232 } __attribute__((packed, aligned(16))) psp_combo_header; 233 234 typedef struct _psp_combo_entry { 235 uint32_t id_sel; 236 uint32_t id; 237 uint64_t lvl2_addr; 238 } __attribute__((packed)) psp_combo_entry; 239 240 typedef struct _psp_combo_directory { 241 psp_combo_header header; 242 psp_combo_entry entries[]; 243 } __attribute__((packed, aligned(16))) psp_combo_directory; 244 245 #define MAX_COMBO_ENTRIES 2 246 247 typedef struct _bios_directory_hdr { 248 uint32_t cookie; 249 uint32_t checksum; 250 uint32_t num_entries; 251 union { 252 uint32_t additional_info; 253 struct { 254 uint32_t dir_size:10; 255 uint32_t spi_block_size:4; 256 uint32_t base_addr:15; 257 uint32_t address_mode:2; 258 uint32_t not_used:1; 259 } __attribute__((packed)) additional_info_fields; 260 }; 261 } __attribute__((packed, aligned(16))) bios_directory_hdr; 262 263 typedef struct _bios_directory_entry { 264 uint8_t type; 265 uint8_t region_type; 266 int reset:1; 267 int copy:1; 268 int ro:1; 269 int compressed:1; 270 int inst:4; 271 uint8_t subprog; /* b[7:3] reserved */ 272 uint32_t size; 273 uint64_t source:62; 274 uint64_t address_mode:2; 275 uint64_t dest; 276 } __attribute__((packed)) bios_directory_entry; 277 278 typedef struct _bios_directory_table { 279 bios_directory_hdr header; 280 bios_directory_entry entries[]; 281 } bios_directory_table; 282 283 #define MAX_BIOS_ENTRIES 0x2f 284 285 #define BDT_LVL1 (1 << 0) 286 #define BDT_LVL2 (1 << 1) 287 #define BDT_LVL1_AB (1 << 2) 288 #define BDT_LVL2_AB (1 << 3) 289 #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) 290 #define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB) 291 typedef struct _amd_bios_entry { 292 amd_bios_type type; 293 char *filename; 294 int subpr; 295 int region_type; 296 int reset; 297 int copy; 298 int ro; 299 int zlib; 300 int inst; 301 uint64_t src; 302 uint64_t dest; 303 size_t size; 304 int level; 305 } amd_bios_entry; 306 307 typedef struct _ish_directory_table { 308 uint32_t checksum; 309 uint32_t boot_priority; 310 uint32_t update_retry_count; 311 uint8_t glitch_retry_count; 312 uint8_t glitch_higherbits_reserved[3]; 313 uint32_t pl2_location; 314 uint32_t psp_id; 315 uint32_t slot_max_size; 316 uint32_t reserved; 317 } __attribute__((packed)) ish_directory_table; 318 319 #define EMBEDDED_FW_SIGNATURE 0x55aa55aa 320 #define PSP_COOKIE 0x50535024 /* 'PSP$' */ 321 #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ 322 #define PSP2_COOKIE 0x50535032 /* 'PSP2' */ 323 #define BHD_COOKIE 0x44484224 /* 'DHB$ */ 324 #define BHDL2_COOKIE 0x324c4224 /* '2LB$ */ 325 #define BHD2_COOKIE 0x44484232 /* 'DHB2' */ 326 327 #define PSP_LVL1 (1 << 0) 328 #define PSP_LVL2 (1 << 1) 329 #define PSP_LVL1_AB (1 << 2) 330 #define PSP_LVL2_AB (1 << 3) 331 #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) 332 #define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB) 333 334 typedef enum _fwid_type { 335 FWID_TYPE_FWID = 0, 336 FWID_TYPE_UUID, 337 } fwid_type_t; 338 339 #define UUID_LEN_BYTES 16 340 typedef struct _amd_fw_entry_hash { 341 fwid_type_t fwid_type; 342 union { 343 uint16_t fw_id; 344 uint8_t uuid[UUID_LEN_BYTES]; 345 }; 346 uint16_t subtype; 347 uint32_t sha_len; 348 uint8_t sha[SHA384_DIGEST_LENGTH]; 349 } amd_fw_entry_hash; 350 351 typedef struct _amd_fw_entry { 352 amd_fw_type type; 353 char *filename; 354 uint8_t subprog; 355 uint8_t inst; 356 uint64_t dest; 357 size_t size; 358 int level; 359 uint64_t other; 360 /* If the binary is signed and the tool is invoked to keep the signed binaries separate, 361 then this field is populated with the offset of the concerned PSP binary (relative to 362 BIOS or PSP Directory table). */ 363 uint64_t addr_signed; 364 uint32_t file_size; 365 /* Some files that don't have amd_fw_header have to be skipped from hashing. These files 366 include but not limited to: *iKek*, *.tkn, *.stkn */ 367 bool skip_hashing; 368 uint8_t hash_tbl_id; 369 fwid_type_t fwid_type; 370 uint32_t num_hash_entries; 371 amd_fw_entry_hash *hash_entries; 372 bool generate_manifest; 373 } amd_fw_entry; 374 375 /* Most PSP binaries, if not all, have the following header format. */ 376 struct amd_fw_header { 377 uint8_t reserved_0[20]; 378 uint32_t fw_size_signed; 379 uint8_t reserved_18[24]; 380 /* 1 if the image is signed, 0 otherwise */ 381 uint32_t sig_opt; 382 uint32_t sig_id; 383 uint8_t sig_param[16]; 384 uint32_t comp_opt; 385 uint8_t reserved_4c[4]; 386 uint32_t uncomp_size; 387 uint32_t comp_size; 388 /* Starting MDN fw_id is populated instead of fw_type. */ 389 uint16_t fw_id; 390 uint8_t reserved_5a[6]; 391 uint8_t version[4]; 392 uint8_t reserved_64[8]; 393 uint32_t size_total; 394 uint8_t reserved_70[12]; 395 /* Starting MDN fw_id is populated instead of fw_type. fw_type will still be around 396 for backwards compatibility. */ 397 uint8_t fw_type; 398 uint8_t fw_subtype; 399 uint8_t fw_subprog; 400 uint8_t reserved_7f; 401 uint8_t reserved_80[128]; 402 } __packed; 403 404 /* Based on the available PSP resources and increasing number of signed PSP binaries, 405 AMD recommends to split the hash table into 3 parts for now. */ 406 #define MAX_NUM_HASH_TABLES 3 407 struct psp_fw_hash_table { 408 uint16_t version; 409 uint16_t no_of_entries_256; 410 uint16_t no_of_entries_384; 411 /* The next 2 elements are pointers to arrays of SHA256 and SHA384 entries. */ 412 /* It does not make sense to store pointers in the CBFS file */ 413 } __packed; 414 415 typedef struct _amd_cb_config { 416 bool have_whitelist; 417 bool unlock_secure; 418 bool use_secureos; 419 bool load_mp2_fw; 420 bool multi_level; 421 bool s0i3; 422 bool second_gen; 423 bool have_mb_spl; 424 bool recovery_ab; 425 bool recovery_ab_single_copy; 426 bool need_ish; 427 bool use_combo; 428 bool have_apcb_bk; 429 enum platform soc_id; 430 431 uint8_t efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag; 432 uint32_t body_location, efs_location; 433 uint64_t signed_start_addr; 434 char *manifest_file; 435 const char *signed_output_file; 436 char *output, *config; 437 char *combo_config[MAX_COMBO_ENTRIES]; 438 int debug; 439 } amd_cb_config; 440 441 typedef struct _context { 442 char *rom; /* target buffer, size of flash device */ 443 uint32_t rom_size; /* size of flash device */ 444 uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ 445 uint32_t current; /* pointer within flash & proxy buffer */ 446 uint32_t current_pointer_saved; 447 uint32_t current_table; 448 void *amd_psp_fw_table_clean; 449 void *amd_bios_table_clean; 450 struct _combo_apcb { 451 char *filename; 452 uint8_t ins; 453 uint8_t sub; 454 } combo_apcb[MAX_COMBO_ENTRIES], combo_apcb_bk[MAX_COMBO_ENTRIES]; 455 embedded_firmware *amd_romsig_ptr; 456 psp_directory_table *pspdir, *pspdir2, *pspdir2_b; 457 bios_directory_table *biosdir, *biosdir2, *biosdir2_b; 458 psp_combo_directory *psp_combo_dir, *bhd_combo_dir; 459 ish_directory_table *ish_a_dir, *ish_b_dir; 460 } context; 461 462 uint8_t process_config(FILE *config, amd_cb_config *cb_config); 463 void process_signed_psp_firmwares(const char *signed_rom, 464 amd_fw_entry *fw_table, 465 uint64_t signed_start_addr, 466 enum platform soc_id); 467 int find_bios_entry(amd_bios_type type); 468 469 #define EFS_FILE_SUFFIX ".efs" 470 #define TMP_FILE_SUFFIX ".tmp" 471 #define BODY_FILE_SUFFIX ".body" 472 473 void write_or_fail(int fd, void *ptr, size_t size); 474 ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size); 475 ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size); 476 ssize_t write_body(char *output, void *body_offset, ssize_t body_size); 477 ssize_t copy_blob(void *dest, const char *src_file, size_t room); 478 #define OK 0 479 480 #define LINE_EOF (1) 481 #define LINE_TOO_LONG (2) 482 483 int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *ctx); 484 void register_apcb_combo(amd_cb_config *cb_config, int combo_index, context *ctx); 485 486 #endif /* _AMD_FW_TOOL_H_ */ 487