1 /**************************************************************************
2 *
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_vcn_dec.h"
11 #include "radeon_video.h"
12 #include "radeonsi/si_pipe.h"
13 #include "util/u_memory.h"
14 #include "util/u_video.h"
15
16 #include <assert.h>
17 #include <stdio.h>
18
radeon_jpeg_get_decode_param(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)19 static struct pb_buffer_lean *radeon_jpeg_get_decode_param(struct radeon_decoder *dec,
20 struct pipe_video_buffer *target,
21 struct pipe_picture_desc *picture)
22 {
23 struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
24 struct si_texture *chroma, *chromav;
25
26 dec->jpg.bsd_size = align(dec->bs_size, 128);
27 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
28 dec->jpg.dt_chroma_top_offset = 0;
29 dec->jpg.dt_chromav_top_offset = 0;
30
31 switch (target->buffer_format) {
32 case PIPE_FORMAT_IYUV:
33 case PIPE_FORMAT_YV12:
34 case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
35 case PIPE_FORMAT_Y8_U8_V8_440_UNORM:
36 case PIPE_FORMAT_R8_G8_B8_UNORM:
37 chromav = (struct si_texture *)((struct vl_video_buffer *)target)->resources[2];
38 dec->jpg.dt_chromav_top_offset = chromav->surface.u.gfx9.surf_offset;
39 chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
40 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
41 break;
42 case PIPE_FORMAT_NV12:
43 case PIPE_FORMAT_P010:
44 case PIPE_FORMAT_P016:
45 chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
46 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
47 break;
48 default:
49 break;
50 }
51 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
52 dec->jpg.dt_uv_pitch = dec->jpg.dt_pitch / 2;
53
54 return luma->buffer.buf;
55 }
56
57 /* add a new set register command to the IB */
set_reg_jpeg(struct radeon_decoder * dec,unsigned reg,unsigned cond,unsigned type,uint32_t val)58 static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg, unsigned cond, unsigned type,
59 uint32_t val)
60 {
61 radeon_emit(&dec->jcs[dec->cb_idx], RDECODE_PKTJ(reg, cond, type));
62 radeon_emit(&dec->jcs[dec->cb_idx], val);
63 }
64
65 /* send a bitstream buffer command */
send_cmd_bitstream(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)66 static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
67 unsigned usage, enum radeon_bo_domain domain)
68 {
69 uint64_t addr;
70
71 // jpeg soft reset
72 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
73
74 // ensuring the Reset is asserted in SCLK domain
75 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
76 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
77 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
78 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
79 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
80
81 // wait mem
82 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
83
84 // ensuring the Reset is de-asserted in SCLK domain
85 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
86 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
87 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
88
89 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
90 addr = dec->ws->buffer_get_virtual_address(buf);
91 addr = addr + off;
92
93 // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
94 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0,
95 (addr >> 32));
96 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, addr);
97
98 // set jpeg_rb_base
99 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0);
100
101 // set jpeg_rb_base
102 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0);
103
104 // set jpeg_rb_wptr
105 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0, (dec->jpg.bsd_size >> 2));
106 }
107
108 /* send a target buffer command */
send_cmd_target(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)109 static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
110 unsigned usage, enum radeon_bo_domain domain)
111 {
112 uint64_t addr;
113
114 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
115 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0,
116 ((dec->jpg.dt_uv_pitch * 2) >> 4));
117
118 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0);
119 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0);
120
121 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
122 addr = dec->ws->buffer_get_virtual_address(buf);
123 addr = addr + off;
124
125 // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
126 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, TYPE0,
127 (addr >> 32));
128 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, addr);
129
130 // set output buffer data address
131 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0);
132 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, dec->jpg.dt_luma_top_offset);
133 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1);
134 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
135 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0);
136
137 // set output buffer read pointer
138 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0);
139
140 // enable error interrupts
141 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE);
142
143 // start engine command
144 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6);
145
146 // wait for job completion, wait for job JBSI fetch done
147 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
148 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (dec->jpg.bsd_size >> 2));
149 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
150 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
151 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF);
152
153 // wait for job jpeg outbuf idle
154 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
155 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF);
156 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3, 0x00000001);
157
158 // stop engine
159 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4);
160
161 // asserting jpeg lmi drop
162 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
163 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 23 | 1 << 0));
164 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0);
165
166 // asserting jpeg reset
167 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
168
169 // ensure reset is asserted in sclk domain
170 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
171 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
172 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
173
174 // de-assert jpeg reset
175 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
176
177 // ensure reset is de-asserted in sclk domain
178 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
179 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
180 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
181
182 // de-asserting jpeg lmi drop
183 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
184 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
185 }
186
187 /* send a bitstream buffer command */
send_cmd_bitstream_direct(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)188 static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buffer_lean *buf,
189 uint32_t off, unsigned usage,
190 enum radeon_bo_domain domain)
191 {
192 uint64_t addr;
193
194 // jpeg soft reset
195 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 1);
196
197 // ensuring the Reset is asserted in SCLK domain
198 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
199 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10));
200 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
201
202 // wait mem
203 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 0);
204
205 // ensuring the Reset is de-asserted in SCLK domain
206 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10));
207 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
208
209 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
210 addr = dec->ws->buffer_get_virtual_address(buf);
211 addr = addr + off;
212
213 // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
214 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_high, COND0, TYPE0, (addr >> 32));
215 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_low, COND0, TYPE0, addr);
216
217 // set jpeg_rb_base
218 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_base, COND0, TYPE0, 0);
219
220 // set jpeg_rb_base
221 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0);
222
223 // set jpeg_rb_wptr
224 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_wptr, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
225 }
226
227 /* send a target buffer command */
send_cmd_target_direct(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain,enum pipe_format buffer_format)228 static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
229 unsigned usage, enum radeon_bo_domain domain,
230 enum pipe_format buffer_format)
231 {
232 uint64_t addr;
233 uint32_t val;
234 bool format_convert = false;
235 uint32_t fc_sps_info_val = 0;
236
237 switch (buffer_format) {
238 case PIPE_FORMAT_R8G8B8A8_UNORM:
239 format_convert = true;
240 fc_sps_info_val = 1 | (1 << 4) | (0xff << 8);
241 break;
242 case PIPE_FORMAT_A8R8G8B8_UNORM:
243 format_convert = true;
244 fc_sps_info_val = 1 | (1 << 4) | (1 << 5) | (0xff << 8);
245 break;
246 case PIPE_FORMAT_R8_G8_B8_UNORM:
247 format_convert = true;
248 fc_sps_info_val = 1 | (1 << 5) | (0xff << 8);
249 break;
250 default:
251 break;
252 }
253
254 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3 && format_convert) {
255 set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, dec->jpg.dt_pitch);
256 set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, (dec->jpg.dt_uv_pitch * 2));
257 } else {
258 set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
259 set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, ((dec->jpg.dt_uv_pitch * 2) >> 4));
260 }
261
262 set_reg_jpeg(dec, dec->jpg_reg.dec_addr_mode, COND0, TYPE0, 0);
263 set_reg_jpeg(dec, dec->jpg_reg.dec_y_gfx10_tiling_surface, COND0, TYPE0, 0);
264 set_reg_jpeg(dec, dec->jpg_reg.dec_uv_gfx10_tiling_surface, COND0, TYPE0, 0);
265
266 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
267 addr = dec->ws->buffer_get_virtual_address(buf);
268 addr = addr + off;
269
270 // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
271 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_high, COND0, TYPE0, (addr >> 32));
272 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_low, COND0, TYPE0, addr);
273
274 // set output buffer data address
275 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V2) {
276 set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 0);
277 set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
278 set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 1);
279 set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
280 if (dec->jpg.dt_chromav_top_offset) {
281 set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 2);
282 set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
283 }
284 } else {
285 set_reg_jpeg(dec, dec->jpg_reg.jpeg_luma_base0_0, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
286 set_reg_jpeg(dec, dec->jpg_reg.jpeg_chroma_base0_0, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
287 set_reg_jpeg(dec, dec->jpg_reg.jpeg_chromav_base0_0, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
288 if (dec->jpg.crop_width && dec->jpg.crop_height) {
289 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_START, COND0, TYPE0,
290 ((dec->jpg.crop_y << 16) | dec->jpg.crop_x));
291 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_STRIDE, COND0, TYPE0,
292 ((dec->jpg.crop_height << 16) | dec->jpg.crop_width));
293 } else {
294 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_START, COND0, TYPE0,
295 ((0 << 16) | 0));
296 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_STRIDE, COND0, TYPE0,
297 ((1 << 16) | 1));
298 }
299 if (format_convert) {
300 /* set fc timeout control */
301 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_TMEOUT_CNT, COND0, TYPE0,(4244373504));
302 /* set alpha position and packed format */
303 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_SPS_INFO, COND0, TYPE0, fc_sps_info_val);
304 /* coefs */
305 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_R_COEF, COND0, TYPE0, 256 | (0 << 10) | (403 << 20));
306 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_G_COEF, COND0, TYPE0, 256 | (976 << 10) | (904 << 20));
307 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_B_COEF, COND0, TYPE0, 256 | (475 << 10) | (0 << 20));
308 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL0, COND0, TYPE0, 128 | (384 << 16));
309 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL1, COND0, TYPE0, 384 | (128 << 16));
310 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL2, COND0, TYPE0, 128 | (384 << 16));
311 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL3, COND0, TYPE0, 384 | (128 << 16));
312 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL0, COND0, TYPE0, 128 | (384 << 16));
313 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL1, COND0, TYPE0, 384 | (128 << 16));
314 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL2, COND0, TYPE0, 128 | (384 << 16));
315 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL3, COND0, TYPE0, 384 | (128 << 16));
316 } else
317 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_SPS_INFO, COND0, TYPE0, 1 | (1 << 5) | (255 << 8));
318 }
319 set_reg_jpeg(dec, dec->jpg_reg.jpeg_tier_cntl2, COND0, 0, 0);
320
321 // set output buffer read pointer
322 set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_rptr, COND0, TYPE0, 0);
323 set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_cntl, COND0, TYPE0,
324 ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
325
326 // enable error interrupts
327 set_reg_jpeg(dec, dec->jpg_reg.jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE);
328
329 // start engine command
330 val = 0x6;
331 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3) {
332 if (dec->jpg.crop_width && dec->jpg.crop_height)
333 val = val | (0x1 << 24);
334 if (format_convert)
335 val = val | (1 << 16) | (1 << 18);
336 }
337 set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, val);
338
339 // wait for job completion, wait for job JBSI fetch done
340 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
341 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
342 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF);
343
344 // wait for job jpeg outbuf idle
345 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF);
346 set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001);
347
348 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3 && format_convert) {
349 val = val | (0x7 << 16);
350 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0);
351 set_reg_jpeg(dec, vcnipUVD_JPEG_INT_STAT, COND3, TYPE3, val);
352 }
353
354 // stop engine
355 set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, 0x4);
356 }
357
358 /**
359 * send cmd for vcn jpeg
360 */
send_cmd_jpeg(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)361 void send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
362 struct pipe_picture_desc *picture)
363 {
364 struct pb_buffer_lean *dt;
365 struct rvid_buffer *bs_buf;
366
367 bs_buf = &dec->bs_buffers[dec->cur_buffer];
368
369 memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
370 dec->ws->buffer_unmap(dec->ws, bs_buf->res->buf);
371 dec->bs_ptr = NULL;
372
373 dt = radeon_jpeg_get_decode_param(dec, target, picture);
374
375 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V1) {
376 send_cmd_bitstream(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
377 send_cmd_target(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
378 } else {
379 send_cmd_bitstream_direct(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
380 send_cmd_target_direct(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM, target->buffer_format);
381 }
382 }
383