1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "ac_rtld.h"
8 #include "amd_kernel_code_t.h"
9 #include "nir/tgsi_to_nir.h"
10 #include "si_build_pm4.h"
11 #include "si_shader_internal.h"
12 #include "util/u_async_debug.h"
13 #include "util/u_memory.h"
14 #include "util/u_upload_mgr.h"
15 #include "si_tracepoints.h"
16
17 #define COMPUTE_DBG(sscreen, fmt, args...) \
18 do { \
19 if ((sscreen->debug_flags & DBG(COMPUTE))) \
20 fprintf(stderr, fmt, ##args); \
21 } while (0);
22
23 struct dispatch_packet {
24 uint16_t header;
25 uint16_t setup;
26 uint16_t workgroup_size_x;
27 uint16_t workgroup_size_y;
28 uint16_t workgroup_size_z;
29 uint16_t reserved0;
30 uint32_t grid_size_x;
31 uint32_t grid_size_y;
32 uint32_t grid_size_z;
33 uint32_t group_segment_size;
34 uint64_t kernel_object;
35 uint64_t kernarg_address;
36 uint64_t reserved2;
37 };
38
si_compute_get_code_object(const struct si_compute * program,uint64_t symbol_offset)39 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
40 uint64_t symbol_offset)
41 {
42 const struct si_shader_selector *sel = &program->sel;
43
44 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
45 return NULL;
46
47 struct ac_rtld_binary rtld;
48 if (!ac_rtld_open(&rtld,
49 (struct ac_rtld_open_info){.info = &sel->screen->info,
50 .shader_type = MESA_SHADER_COMPUTE,
51 .num_parts = 1,
52 .elf_ptrs = &program->shader.binary.code_buffer,
53 .elf_sizes = &program->shader.binary.code_size}))
54 return NULL;
55
56 const amd_kernel_code_t *result = NULL;
57 const char *text;
58 size_t size;
59 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
60 goto out;
61
62 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
63 goto out;
64
65 result = (const amd_kernel_code_t *)(text + symbol_offset);
66
67 out:
68 ac_rtld_close(&rtld);
69 return result;
70 }
71
code_object_to_config(const amd_kernel_code_t * code_object,struct ac_shader_config * out_config)72 static void code_object_to_config(const amd_kernel_code_t *code_object,
73 struct ac_shader_config *out_config)
74 {
75
76 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
77 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
78 out_config->num_sgprs = code_object->wavefront_sgpr_count;
79 out_config->num_vgprs = code_object->workitem_vgpr_count;
80 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
81 out_config->rsrc1 = rsrc1;
82 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
83 out_config->rsrc2 = rsrc2;
84 out_config->scratch_bytes_per_wave =
85 align(code_object->workitem_private_segment_byte_size * 64, 1024);
86 }
87
88 /* Asynchronous compute shader compilation. */
si_create_compute_state_async(void * job,void * gdata,int thread_index)89 static void si_create_compute_state_async(void *job, void *gdata, int thread_index)
90 {
91 struct si_compute *program = (struct si_compute *)job;
92 struct si_shader_selector *sel = &program->sel;
93 struct si_shader *shader = &program->shader;
94 struct ac_llvm_compiler **compiler;
95 struct util_debug_callback *debug = &sel->compiler_ctx_state.debug;
96 struct si_screen *sscreen = sel->screen;
97
98 assert(!debug->debug_message || debug->async);
99 assert(thread_index >= 0);
100 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
101 compiler = &sscreen->compiler[thread_index];
102
103 assert(program->ir_type == PIPE_SHADER_IR_NIR);
104 si_nir_scan_shader(sscreen, sel->nir, &sel->info);
105
106 if (!sel->info.base.use_aco_amd && !*compiler)
107 *compiler = si_create_llvm_compiler(sscreen);
108
109 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
110 &sel->active_samplers_and_images);
111
112 program->shader.is_monolithic = true;
113 program->shader.wave_size = si_determine_wave_size(sscreen, &program->shader);
114
115 /* Variable block sizes need 10 bits (1 + log2(SI_MAX_VARIABLE_THREADS_PER_BLOCK)) per dim.
116 * We pack them into a single user SGPR.
117 */
118 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
119 (sel->info.uses_variable_block_size ? 1 : 0) +
120 sel->info.base.cs.user_data_components_amd;
121
122 /* Fast path for compute shaders - some descriptors passed via user SGPRs. */
123 /* Shader buffers in user SGPRs. */
124 for (unsigned i = 0; i < MIN2(3, sel->info.base.num_ssbos) && user_sgprs <= 12; i++) {
125 user_sgprs = align(user_sgprs, 4);
126 if (i == 0)
127 sel->cs_shaderbufs_sgpr_index = user_sgprs;
128 user_sgprs += 4;
129 sel->cs_num_shaderbufs_in_user_sgprs++;
130 }
131
132 /* Images in user SGPRs. */
133 unsigned non_fmask_images = u_bit_consecutive(0, sel->info.base.num_images);
134
135 /* Remove images with FMASK from the bitmask. We only care about the first
136 * 3 anyway, so we can take msaa_images[0] and ignore the rest.
137 */
138 if (sscreen->info.gfx_level < GFX11)
139 non_fmask_images &= ~sel->info.base.msaa_images[0];
140
141 for (unsigned i = 0; i < 3 && non_fmask_images & (1 << i); i++) {
142 unsigned num_sgprs = BITSET_TEST(sel->info.base.image_buffers, i) ? 4 : 8;
143
144 if (align(user_sgprs, num_sgprs) + num_sgprs > 16)
145 break;
146
147 user_sgprs = align(user_sgprs, num_sgprs);
148 if (i == 0)
149 sel->cs_images_sgpr_index = user_sgprs;
150 user_sgprs += num_sgprs;
151 sel->cs_num_images_in_user_sgprs++;
152 }
153 sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
154 assert(user_sgprs <= 16);
155
156 unsigned char ir_sha1_cache_key[20];
157 si_get_ir_cache_key(sel, false, false, shader->wave_size, ir_sha1_cache_key);
158
159 /* Try to load the shader from the shader cache. */
160 simple_mtx_lock(&sscreen->shader_cache_mutex);
161
162 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
163 simple_mtx_unlock(&sscreen->shader_cache_mutex);
164
165 shader->complete_shader_binary_size = si_get_shader_binary_size(sscreen, shader);
166
167 if (!si_shader_binary_upload(sscreen, shader, 0))
168 program->shader.compilation_failed = true;
169
170 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
171 si_shader_dump(sscreen, shader, debug, stderr, true);
172 } else {
173 simple_mtx_unlock(&sscreen->shader_cache_mutex);
174
175 if (!si_create_shader_variant(sscreen, *compiler, &program->shader, debug)) {
176 program->shader.compilation_failed = true;
177 return;
178 }
179
180 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
181 ((shader->wave_size == 32 ||
182 sscreen->info.wave64_vgpr_alloc_granularity == 8) ? 8 : 4)) |
183 S_00B848_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
184 S_00B848_MEM_ORDERED(si_shader_mem_ordered(shader)) |
185 S_00B848_FLOAT_MODE(shader->config.float_mode) |
186 /* This is needed for CWSR, but it causes halts to work differently. */
187 S_00B848_PRIV(sscreen->info.gfx_level == GFX11);
188
189 if (sscreen->info.gfx_level < GFX10) {
190 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
191 }
192
193 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) |
194 S_00B84C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
195 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
196 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
197 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
198 S_00B84C_TG_SIZE_EN(sel->info.uses_tg_size) |
199 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
200 ? 2
201 : sel->info.uses_thread_id[1] ? 1 : 0) |
202 S_00B84C_LDS_SIZE(shader->config.lds_size);
203
204 simple_mtx_lock(&sscreen->shader_cache_mutex);
205 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
206 simple_mtx_unlock(&sscreen->shader_cache_mutex);
207 }
208
209 ralloc_free(sel->nir);
210 sel->nir = NULL;
211 }
212
si_create_compute_state(struct pipe_context * ctx,const struct pipe_compute_state * cso)213 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
214 {
215 struct si_context *sctx = (struct si_context *)ctx;
216 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
217 struct si_compute *program = CALLOC_STRUCT(si_compute);
218 struct si_shader_selector *sel = &program->sel;
219
220 pipe_reference_init(&sel->base.reference, 1);
221 sel->stage = MESA_SHADER_COMPUTE;
222 sel->screen = sscreen;
223 simple_mtx_init(&sel->mutex, mtx_plain);
224 sel->const_and_shader_buf_descriptors_index =
225 si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_COMPUTE);
226 sel->sampler_and_images_descriptors_index =
227 si_sampler_and_image_descriptors_idx(PIPE_SHADER_COMPUTE);
228 sel->info.base.shared_size = cso->static_shared_mem;
229 program->shader.selector = &program->sel;
230 program->ir_type = cso->ir_type;
231 program->input_size = cso->req_input_mem;
232
233 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
234 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
235 program->ir_type = PIPE_SHADER_IR_NIR;
236 sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
237 } else {
238 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
239 sel->nir = (struct nir_shader *)cso->prog;
240 }
241
242 if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
243 nir_print_shader(sel->nir, stderr);
244
245 sel->compiler_ctx_state.debug = sctx->debug;
246 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
247 p_atomic_inc(&sscreen->num_shaders_created);
248
249 si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
250 program, si_create_compute_state_async);
251 } else {
252 const struct pipe_binary_program_header *header;
253 header = cso->prog;
254
255 program->shader.binary.type = SI_SHADER_BINARY_ELF;
256 program->shader.binary.code_size = header->num_bytes;
257 program->shader.binary.code_buffer = malloc(header->num_bytes);
258 if (!program->shader.binary.code_buffer) {
259 FREE(program);
260 return NULL;
261 }
262 memcpy((void *)program->shader.binary.code_buffer, header->blob, header->num_bytes);
263
264 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
265 code_object_to_config(code_object, &program->shader.config);
266
267 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32))
268 program->shader.wave_size = 32;
269 else
270 program->shader.wave_size = 64;
271
272 bool ok = si_shader_binary_upload(sctx->screen, &program->shader, 0);
273 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
274
275 if (!ok) {
276 fprintf(stderr, "LLVM failed to upload shader\n");
277 free((void *)program->shader.binary.code_buffer);
278 FREE(program);
279 return NULL;
280 }
281 }
282
283 return program;
284 }
285
si_get_compute_state_info(struct pipe_context * ctx,void * state,struct pipe_compute_state_object_info * info)286 static void si_get_compute_state_info(struct pipe_context *ctx, void *state,
287 struct pipe_compute_state_object_info *info)
288 {
289 struct si_compute *program = (struct si_compute *)state;
290 struct si_shader_selector *sel = &program->sel;
291
292 assert(program->ir_type != PIPE_SHADER_IR_NATIVE);
293
294 /* Wait because we need the compilation to finish first */
295 util_queue_fence_wait(&sel->ready);
296
297 uint8_t wave_size = program->shader.wave_size;
298 info->private_memory = DIV_ROUND_UP(program->shader.config.scratch_bytes_per_wave, wave_size);
299 info->preferred_simd_size = wave_size;
300 info->simd_sizes = wave_size;
301 info->max_threads = si_get_max_workgroup_size(&program->shader);
302 }
303
si_bind_compute_state(struct pipe_context * ctx,void * state)304 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
305 {
306 struct si_context *sctx = (struct si_context *)ctx;
307 struct si_compute *program = (struct si_compute *)state;
308 struct si_shader_selector *sel = &program->sel;
309
310 sctx->cs_shader_state.program = program;
311 if (!program)
312 return;
313
314 /* Wait because we need active slot usage masks. */
315 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
316 util_queue_fence_wait(&sel->ready);
317
318 si_set_active_descriptors(sctx,
319 SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
320 sel->active_const_and_shader_buffers);
321 si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
322 sel->active_samplers_and_images);
323
324 sctx->compute_shaderbuf_sgprs_dirty = true;
325 sctx->compute_image_sgprs_dirty = true;
326
327 if (unlikely((sctx->screen->debug_flags & DBG(SQTT)) && sctx->sqtt)) {
328 uint32_t pipeline_code_hash = _mesa_hash_data_with_seed(
329 program->shader.binary.code_buffer,
330 program->shader.binary.code_size,
331 0);
332
333 if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
334 /* Short lived fake pipeline: we don't need to reupload the compute shaders,
335 * as we do for the gfx ones so just create a temp pipeline to be able to
336 * call si_sqtt_register_pipeline, and then drop it.
337 */
338 struct si_sqtt_fake_pipeline pipeline = { 0 };
339 pipeline.code_hash = pipeline_code_hash;
340 pipeline.bo = program->shader.bo;
341
342 si_sqtt_register_pipeline(sctx, &pipeline, NULL);
343 }
344
345 si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 1);
346 }
347 }
348
si_set_global_binding(struct pipe_context * ctx,unsigned first,unsigned n,struct pipe_resource ** resources,uint32_t ** handles)349 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
350 struct pipe_resource **resources, uint32_t **handles)
351 {
352 unsigned i;
353 struct si_context *sctx = (struct si_context *)ctx;
354 struct si_compute *program = sctx->cs_shader_state.program;
355
356 if (first + n > program->max_global_buffers) {
357 unsigned old_max = program->max_global_buffers;
358 program->max_global_buffers = first + n;
359 program->global_buffers = realloc(
360 program->global_buffers, program->max_global_buffers * sizeof(program->global_buffers[0]));
361 if (!program->global_buffers) {
362 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
363 return;
364 }
365
366 memset(&program->global_buffers[old_max], 0,
367 (program->max_global_buffers - old_max) * sizeof(program->global_buffers[0]));
368 }
369
370 if (!resources) {
371 for (i = 0; i < n; i++) {
372 pipe_resource_reference(&program->global_buffers[first + i], NULL);
373 }
374 return;
375 }
376
377 for (i = 0; i < n; i++) {
378 uint64_t va;
379 uint32_t offset;
380 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
381 va = si_resource(resources[i])->gpu_address;
382 offset = util_le32_to_cpu(*handles[i]);
383 va += offset;
384 va = util_cpu_to_le64(va);
385 memcpy(handles[i], &va, sizeof(va));
386 }
387 }
388
si_setup_compute_scratch_buffer(struct si_context * sctx,struct si_shader * shader)389 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
390 {
391 uint64_t scratch_bo_size =
392 sctx->compute_scratch_buffer ? sctx->compute_scratch_buffer->b.b.width0 : 0;
393 uint64_t scratch_needed = sctx->max_seen_compute_scratch_bytes_per_wave *
394 sctx->screen->info.max_scratch_waves;
395 assert(scratch_needed);
396
397 if (scratch_bo_size < scratch_needed) {
398 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
399
400 sctx->compute_scratch_buffer =
401 si_aligned_buffer_create(&sctx->screen->b,
402 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
403 SI_RESOURCE_FLAG_DISCARDABLE,
404 PIPE_USAGE_DEFAULT,
405 scratch_needed, sctx->screen->info.pte_fragment_size);
406
407 if (!sctx->compute_scratch_buffer)
408 return false;
409 }
410
411 /* Set the scratch address in the shader binary. */
412 if (!sctx->screen->info.has_scratch_base_registers) {
413 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
414
415 if (shader->scratch_va != scratch_va) {
416 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
417 return false;
418
419 shader->scratch_va = scratch_va;
420 }
421 }
422
423 return true;
424 }
425
si_switch_compute_shader(struct si_context * sctx,struct si_compute * program,struct si_shader * shader,const amd_kernel_code_t * code_object,unsigned offset,bool * prefetch,unsigned variable_shared_size)426 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
427 struct si_shader *shader, const amd_kernel_code_t *code_object,
428 unsigned offset, bool *prefetch, unsigned variable_shared_size)
429 {
430 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
431 struct ac_shader_config inline_config = {0};
432 const struct ac_shader_config *config;
433 unsigned rsrc2;
434 uint64_t shader_va;
435 unsigned stage = shader->selector->info.base.stage;
436
437 *prefetch = false;
438
439 assert(variable_shared_size == 0 || stage == MESA_SHADER_KERNEL || program->ir_type == PIPE_SHADER_IR_NATIVE);
440 if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset &&
441 sctx->cs_shader_state.variable_shared_size == variable_shared_size)
442 return true;
443
444 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
445 config = &shader->config;
446 } else {
447 code_object_to_config(code_object, &inline_config);
448 config = &inline_config;
449 }
450 /* copy rsrc2 so we don't have to change it inside the si_shader object */
451 rsrc2 = config->rsrc2;
452
453 /* only do this for OpenCL */
454 if (program->ir_type == PIPE_SHADER_IR_NATIVE || stage == MESA_SHADER_KERNEL) {
455 unsigned shared_size = program->sel.info.base.shared_size + variable_shared_size;
456 unsigned lds_blocks;
457
458 /* Clover uses the compute API differently than other frontends and expects drivers to parse
459 * the shared_size out of the shader headers.
460 */
461 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
462 lds_blocks = config->lds_size;
463 } else {
464 lds_blocks = 0;
465 }
466
467 /* XXX: We are over allocating LDS. For GFX6, the shader reports
468 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
469 * allocated in the shader and 4 bytes allocated by the state
470 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
471 */
472 if (sctx->gfx_level <= GFX6) {
473 lds_blocks += align(shared_size, 256) >> 8;
474 } else {
475 lds_blocks += align(shared_size, 512) >> 9;
476 }
477
478 /* TODO: use si_multiwave_lds_size_workaround */
479 assert(lds_blocks <= 0xFF);
480
481 rsrc2 &= C_00B84C_LDS_SIZE;
482 rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
483 }
484
485 if (config->scratch_bytes_per_wave) {
486 /* Prevent race conditions for accesses to shader->scratch_va and shader->bo, which
487 * can change when scratch_va is updated. Any accesses to shader->bo must also be inside
488 * the lock.
489 *
490 * TODO: This lock could be removed if the scratch address was passed via user SGPRs instead
491 * of the shader binary.
492 */
493 if (!sctx->screen->info.has_scratch_base_registers)
494 simple_mtx_lock(&shader->selector->mutex);
495
496 /* Update max_seen_compute_scratch_bytes_per_wave and compute_tmpring_size. */
497 ac_get_scratch_tmpring_size(&sctx->screen->info,
498 config->scratch_bytes_per_wave,
499 &sctx->max_seen_compute_scratch_bytes_per_wave,
500 &sctx->compute_tmpring_size);
501
502 if (!si_setup_compute_scratch_buffer(sctx, shader))
503 return false;
504
505 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->compute_scratch_buffer,
506 RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
507 }
508
509 shader_va = shader->bo->gpu_address + offset;
510 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
511 /* Shader code is placed after the amd_kernel_code_t
512 * struct. */
513 shader_va += sizeof(amd_kernel_code_t);
514 }
515
516 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo,
517 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
518
519 /* shader->bo can't be used after this if the scratch address is inserted into the shader
520 * binary.
521 */
522 if (config->scratch_bytes_per_wave && !sctx->screen->info.has_scratch_base_registers)
523 simple_mtx_unlock(&shader->selector->mutex);
524
525 if (sctx->gfx_level >= GFX12) {
526 unsigned rsrc3 = S_00B8A0_INST_PREF_SIZE_GFX12(si_get_shader_prefetch_size(shader));
527
528 gfx12_push_compute_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
529 gfx12_opt_push_compute_sh_reg(R_00B848_COMPUTE_PGM_RSRC1,
530 SI_TRACKED_COMPUTE_PGM_RSRC1, config->rsrc1);
531 gfx12_opt_push_compute_sh_reg(R_00B84C_COMPUTE_PGM_RSRC2,
532 SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2);
533 gfx12_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
534 SI_TRACKED_COMPUTE_PGM_RSRC3, rsrc3);
535 gfx12_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
536 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
537 if (config->scratch_bytes_per_wave) {
538 gfx12_opt_push_compute_sh_reg(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
539 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
540 sctx->compute_scratch_buffer->gpu_address >> 8);
541 gfx12_opt_push_compute_sh_reg(R_00B844_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
542 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
543 sctx->compute_scratch_buffer->gpu_address >> 40);
544 }
545 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
546 unsigned rsrc3 = S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader));
547
548 gfx11_push_compute_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
549 gfx11_opt_push_compute_sh_reg(R_00B848_COMPUTE_PGM_RSRC1,
550 SI_TRACKED_COMPUTE_PGM_RSRC1, config->rsrc1);
551 gfx11_opt_push_compute_sh_reg(R_00B84C_COMPUTE_PGM_RSRC2,
552 SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2);
553 gfx11_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
554 SI_TRACKED_COMPUTE_PGM_RSRC3, rsrc3);
555 gfx11_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
556 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
557 if (config->scratch_bytes_per_wave) {
558 gfx11_opt_push_compute_sh_reg(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
559 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
560 sctx->compute_scratch_buffer->gpu_address >> 8);
561 gfx11_opt_push_compute_sh_reg(R_00B844_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
562 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
563 sctx->compute_scratch_buffer->gpu_address >> 40);
564 }
565 } else {
566 radeon_begin(cs);
567 radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
568 radeon_opt_set_sh_reg2(R_00B848_COMPUTE_PGM_RSRC1,
569 SI_TRACKED_COMPUTE_PGM_RSRC1,
570 config->rsrc1, rsrc2);
571 radeon_opt_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
572 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
573
574 if (config->scratch_bytes_per_wave && sctx->screen->info.has_scratch_base_registers) {
575 radeon_opt_set_sh_reg2(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
576 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
577 sctx->compute_scratch_buffer->gpu_address >> 8,
578 sctx->compute_scratch_buffer->gpu_address >> 40);
579 }
580
581 if (sctx->gfx_level >= GFX11) {
582 radeon_opt_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
583 SI_TRACKED_COMPUTE_PGM_RSRC3,
584 S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader)));
585 }
586 radeon_end();
587 }
588
589 COMPUTE_DBG(sctx->screen,
590 "COMPUTE_PGM_RSRC1: 0x%08x "
591 "COMPUTE_PGM_RSRC2: 0x%08x\n",
592 config->rsrc1, config->rsrc2);
593
594 sctx->cs_shader_state.emitted_program = program;
595 sctx->cs_shader_state.offset = offset;
596 sctx->cs_shader_state.variable_shared_size = variable_shared_size;
597
598 *prefetch = true;
599 return true;
600 }
601
setup_scratch_rsrc_user_sgprs(struct si_context * sctx,const amd_kernel_code_t * code_object,unsigned user_sgpr)602 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
603 const amd_kernel_code_t *code_object, unsigned user_sgpr)
604 {
605 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
606 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
607
608 unsigned max_private_element_size =
609 AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
610
611 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
612 uint32_t scratch_dword1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
613
614 if (sctx->gfx_level >= GFX11)
615 scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1);
616 else
617 scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1);
618
619 /* Disable address clamping */
620 uint32_t scratch_dword2 = 0xffffffff;
621 uint32_t index_stride = sctx->cs_shader_state.program->shader.wave_size == 32 ? 2 : 3;
622 uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(1);
623
624 if (sctx->gfx_level >= GFX9) {
625 assert(max_private_element_size == 1); /* only 4 bytes on GFX9 */
626 } else {
627 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
628
629 if (sctx->gfx_level < GFX8) {
630 /* BUF_DATA_FORMAT is ignored, but it cannot be
631 * BUF_DATA_FORMAT_INVALID. */
632 scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
633 }
634 }
635
636 radeon_begin(cs);
637 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
638 radeon_emit(scratch_dword0);
639 radeon_emit(scratch_dword1);
640 radeon_emit(scratch_dword2);
641 radeon_emit(scratch_dword3);
642 radeon_end();
643 }
644
si_setup_user_sgprs_co_v2(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info,uint64_t kernel_args_va)645 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
646 const struct pipe_grid_info *info, uint64_t kernel_args_va)
647 {
648 struct si_compute *program = sctx->cs_shader_state.program;
649 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
650
651 static const enum amd_code_property_mask_t workgroup_count_masks[] = {
652 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
653 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
654 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
655
656 unsigned i, user_sgpr = 0;
657 if (AMD_HSA_BITS_GET(code_object->code_properties,
658 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
659 if (code_object->workitem_private_segment_byte_size > 0) {
660 setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
661 }
662 user_sgpr += 4;
663 }
664
665 radeon_begin(cs);
666
667 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
668 struct dispatch_packet dispatch;
669 unsigned dispatch_offset;
670 struct si_resource *dispatch_buf = NULL;
671 uint64_t dispatch_va;
672
673 /* Upload dispatch ptr */
674 memset(&dispatch, 0, sizeof(dispatch));
675
676 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
677 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
678 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
679
680 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
681 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
682 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
683
684 dispatch.group_segment_size =
685 util_cpu_to_le32(program->sel.info.base.shared_size + info->variable_shared_mem);
686
687 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
688
689 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
690 (struct pipe_resource **)&dispatch_buf);
691
692 if (!dispatch_buf) {
693 fprintf(stderr, "Error: Failed to allocate dispatch "
694 "packet.");
695 }
696 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf,
697 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
698
699 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
700
701 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
702 radeon_emit(dispatch_va);
703 radeon_emit(S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
704
705 si_resource_reference(&dispatch_buf, NULL);
706 user_sgpr += 2;
707 }
708
709 if (AMD_HSA_BITS_GET(code_object->code_properties,
710 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
711 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
712 radeon_emit(kernel_args_va);
713 radeon_emit(S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
714 user_sgpr += 2;
715 }
716
717 for (i = 0; i < 3 && user_sgpr < 16; i++) {
718 if (code_object->code_properties & workgroup_count_masks[i]) {
719 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
720 radeon_emit(info->grid[i]);
721 user_sgpr += 1;
722 }
723 }
724 radeon_end();
725 }
726
si_upload_compute_input(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info)727 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
728 const struct pipe_grid_info *info)
729 {
730 struct si_compute *program = sctx->cs_shader_state.program;
731 struct si_resource *input_buffer = NULL;
732 uint32_t kernel_args_offset = 0;
733 uint32_t *kernel_args;
734 void *kernel_args_ptr;
735 uint64_t kernel_args_va;
736
737 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
738 sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
739 (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
740
741 if (unlikely(!kernel_args_ptr))
742 return false;
743
744 kernel_args = (uint32_t *)kernel_args_ptr;
745 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
746
747 memcpy(kernel_args, info->input, program->input_size);
748
749 for (unsigned i = 0; i < program->input_size / 4; i++) {
750 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
751 }
752
753 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer,
754 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
755
756 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
757 si_resource_reference(&input_buffer, NULL);
758 return true;
759 }
760
si_setup_nir_user_data(struct si_context * sctx,const struct pipe_grid_info * info)761 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
762 {
763 struct si_compute *program = sctx->cs_shader_state.program;
764 struct si_shader_selector *sel = &program->sel;
765 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
766 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
767 unsigned block_size_reg = grid_size_reg +
768 /* 12 bytes = 3 dwords. */
769 12 * sel->info.uses_grid_size;
770 unsigned cs_user_data_reg = block_size_reg + 4 * program->sel.info.uses_variable_block_size;
771
772 if (sel->info.uses_grid_size && info->indirect) {
773 for (unsigned i = 0; i < 3; ++i) {
774 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
775 COPY_DATA_SRC_MEM, si_resource(info->indirect),
776 info->indirect_offset + 4 * i);
777 }
778 }
779
780 if (sctx->gfx_level >= GFX12) {
781 if (sel->info.uses_grid_size && !info->indirect) {
782 gfx12_push_compute_sh_reg(grid_size_reg, info->grid[0]);
783 gfx12_push_compute_sh_reg(grid_size_reg + 4, info->grid[1]);
784 gfx12_push_compute_sh_reg(grid_size_reg + 8, info->grid[2]);
785 }
786
787 if (sel->info.uses_variable_block_size) {
788 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
789 gfx12_push_compute_sh_reg(block_size_reg, value);
790 }
791
792 if (sel->info.base.cs.user_data_components_amd) {
793 unsigned num = sel->info.base.cs.user_data_components_amd;
794 for (unsigned i = 0; i < num; i++)
795 gfx12_push_compute_sh_reg(cs_user_data_reg + i * 4, sctx->cs_user_data[i]);
796 }
797 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
798 if (sel->info.uses_grid_size && !info->indirect) {
799 gfx11_push_compute_sh_reg(grid_size_reg, info->grid[0]);
800 gfx11_push_compute_sh_reg(grid_size_reg + 4, info->grid[1]);
801 gfx11_push_compute_sh_reg(grid_size_reg + 8, info->grid[2]);
802 }
803
804 if (sel->info.uses_variable_block_size) {
805 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
806 gfx11_push_compute_sh_reg(block_size_reg, value);
807 }
808
809 if (sel->info.base.cs.user_data_components_amd) {
810 unsigned num = sel->info.base.cs.user_data_components_amd;
811 for (unsigned i = 0; i < num; i++)
812 gfx11_push_compute_sh_reg(cs_user_data_reg + i * 4, sctx->cs_user_data[i]);
813 }
814 } else {
815 radeon_begin(cs);
816
817 if (sel->info.uses_grid_size && !info->indirect) {
818 radeon_set_sh_reg_seq(grid_size_reg, 3);
819 radeon_emit(info->grid[0]);
820 radeon_emit(info->grid[1]);
821 radeon_emit(info->grid[2]);
822 }
823
824 if (sel->info.uses_variable_block_size) {
825 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
826 radeon_set_sh_reg(block_size_reg, value);
827 }
828
829 if (sel->info.base.cs.user_data_components_amd) {
830 unsigned num = sel->info.base.cs.user_data_components_amd;
831 radeon_set_sh_reg_seq(cs_user_data_reg, num);
832 radeon_emit_array(sctx->cs_user_data, num);
833 }
834 radeon_end();
835 }
836 }
837
si_get_2d_interleave_size(const struct pipe_grid_info * info,unsigned * log_x,unsigned * log_y)838 static bool si_get_2d_interleave_size(const struct pipe_grid_info *info,
839 unsigned *log_x, unsigned *log_y)
840 {
841 /* The following code produces this behavior:
842 *
843 * WG size | WG block/SE | Thread block/SE
844 * ( 1, 32) = 32 | (16, 1) = 16 | ( 16, 32) = 512
845 * ( 2, 16) = 32 | ( 8, 2) = 16 | ( 16, 32) = 512
846 * ( 2, 32) = 64 | (16, 1) = 16 | ( 32, 32) = 1024
847 * ( 4, 8) = 32 | ( 4, 4) = 16 | ( 16, 32) = 512
848 * ( 4, 16) = 64 | ( 8, 2) = 16 | ( 32, 32) = 1024
849 * ( 4, 32) = 128 | ( 8, 1) = 8 | ( 32, 32) = 1024
850 * ( 8, 4) = 32 | ( 2, 8) = 16 | ( 16, 32) = 512
851 * ( 8, 8) = 64 | ( 4, 4) = 16 | ( 32, 32) = 1024
852 * ( 8, 16) = 128 | ( 4, 2) = 8 | ( 32, 32) = 1024
853 * ( 8, 32) = 256 | ( 4, 1) = 4 | ( 32, 32) = 1024
854 * (16, 2) = 32 | ( 1, 16) = 16 | ( 16, 32) = 512
855 * (16, 4) = 64 | ( 2, 8) = 16 | ( 32, 32) = 1024
856 * (16, 8) = 128 | ( 2, 4) = 8 | ( 32, 32) = 1024
857 * (16, 16) = 256 | ( 2, 2) = 4 | ( 32, 32) = 1024
858 * (16, 32) = 512 | ( 2, 1) = 2 | ( 32, 32) = 1024
859 * (32, 1) = 32 | ( 1, 16) = 16 | ( 32, 16) = 512
860 * (32, 2) = 64 | ( 1, 16) = 16 | ( 32, 32) = 1024
861 * (32, 4) = 128 | ( 1, 8) = 8 | ( 32, 32) = 1024
862 * (32, 8) = 256 | ( 1, 4) = 4 | ( 32, 32) = 1024
863 * (32, 16) = 512 | ( 1, 2) = 2 | ( 32, 32) = 1024
864 *
865 * For 3D workgroups, the total 2D thread count is divided by Z.
866 * Example with Z=8, showing only a 2D slice of the grid:
867 *
868 * WG size | WG block/SE | Thread block/SE
869 * ( 1, 32) = 32 | ( 4, 1) = 4 | ( 4, 32) = 128
870 * ( 2, 16) = 32 | ( 4, 1) = 4 | ( 8, 16) = 128
871 * ( 2, 32) = 64 | ( 2, 1) = 2 | ( 4, 32) = 128
872 * ( 4, 8) = 32 | ( 2, 2) = 4 | ( 8, 16) = 128
873 * ( 4, 16) = 64 | ( 2, 1) = 2 | ( 8, 16) = 128
874 * ( 8, 4) = 32 | ( 1, 4) = 4 | ( 8, 16) = 128
875 * ( 8, 8) = 64 | ( 1, 2) = 2 | ( 8, 16) = 128
876 * (16, 2) = 32 | ( 1, 4) = 4 | ( 16, 8) = 128
877 * (16, 4) = 64 | ( 1, 2) = 2 | ( 16, 8) = 128
878 * (32, 1) = 32 | ( 1, 4) = 4 | ( 32, 4) = 128
879 * (32, 2) = 64 | ( 1, 2) = 2 | ( 32, 4) = 128
880 *
881 * It tries to find a WG block size that corresponds to (N, N) or (N, 2*N) threads,
882 * but it's limited by the maximum WGs/SE, which is 16, and the number of threads/SE,
883 * which we set to 1024.
884 */
885 unsigned max_threads_per_se = 1024;
886 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
887 unsigned workgroups_per_se = MIN2(max_threads_per_se / threads_per_threadgroup, 16);
888 unsigned log_workgroups_per_se = util_logbase2(workgroups_per_se);
889
890 if (!log_workgroups_per_se)
891 return false;
892
893 assert(log_workgroups_per_se <= 4);
894
895 *log_x = MIN2(log_workgroups_per_se, 4);
896 *log_y = log_workgroups_per_se - *log_x;
897
898 while (*log_x > 0 && *log_y < 4 &&
899 info->block[0] * (1 << *log_x) > info->block[1] * (1 << *log_y)) {
900 (*log_x)--;
901 (*log_y)++;
902 }
903
904 assert(*log_x + *log_y <= 4);
905 return true;
906 }
907
si_emit_dispatch_packets(struct si_context * sctx,const struct pipe_grid_info * info)908 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
909 {
910 struct si_screen *sscreen = sctx->screen;
911 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
912 bool render_cond_bit = sctx->render_cond_enabled;
913 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
914 unsigned waves_per_threadgroup =
915 DIV_ROUND_UP(threads_per_threadgroup, sctx->cs_shader_state.program->shader.wave_size);
916 unsigned threadgroups_per_cu = 1;
917
918 if (sctx->gfx_level >= GFX10 && waves_per_threadgroup == 1)
919 threadgroups_per_cu = 2;
920
921 if (unlikely(sctx->sqtt_enabled)) {
922 if (info->indirect) {
923 si_sqtt_write_event_marker(sctx, &sctx->gfx_cs,
924 EventCmdDispatchIndirect,
925 UINT_MAX, UINT_MAX, UINT_MAX);
926 } else {
927 si_write_event_with_dims_marker(sctx, &sctx->gfx_cs,
928 EventCmdDispatch,
929 info->grid[0], info->grid[1], info->grid[2]);
930 }
931 }
932
933 radeon_begin(cs);
934 unsigned compute_resource_limits =
935 ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
936 sctx->cs_max_waves_per_sh,
937 threadgroups_per_cu);
938
939 if (sctx->gfx_level >= GFX12) {
940 gfx12_opt_push_compute_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
941 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
942 compute_resource_limits);
943 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
944 gfx11_opt_push_compute_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
945 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
946 compute_resource_limits);
947 } else {
948 radeon_opt_set_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
949 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
950 compute_resource_limits);
951 }
952
953 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
954 /* If the KMD allows it (there is a KMD hw register for it),
955 * allow launching waves out-of-order. (same as Vulkan)
956 * Not available in gfx940.
957 */
958 S_00B800_ORDER_MODE(!sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add &&
959 sctx->gfx_level >= GFX7 &&
960 (sctx->family < CHIP_GFX940 || sctx->screen->info.has_graphics)) |
961 S_00B800_CS_W32_EN(sctx->cs_shader_state.program->shader.wave_size == 32);
962
963 const uint *last_block = info->last_block;
964 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
965 uint32_t num_threads[3];
966
967 if (sctx->gfx_level >= GFX12) {
968 num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX12(info->block[0]);
969 num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX12(info->block[1]);
970 } else {
971 num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX6(info->block[0]);
972 num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX6(info->block[1]);
973 }
974 num_threads[2] = S_00B824_NUM_THREAD_FULL(info->block[2]);
975
976 if (partial_block_en) {
977 unsigned partial[3];
978
979 /* If no partial_block, these should be an entire block size, not 0. */
980 partial[0] = last_block[0] ? last_block[0] : info->block[0];
981 partial[1] = last_block[1] ? last_block[1] : info->block[1];
982 partial[2] = last_block[2] ? last_block[2] : info->block[2];
983
984 num_threads[0] |= S_00B81C_NUM_THREAD_PARTIAL(partial[0]);
985 num_threads[1] |= S_00B820_NUM_THREAD_PARTIAL(partial[1]);
986 num_threads[2] |= S_00B824_NUM_THREAD_PARTIAL(partial[2]);
987
988 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
989 }
990
991 if (sctx->gfx_level >= GFX12) {
992 /* Set PING_PONG_EN for every other dispatch.
993 * Only allowed on a gfx queue, and PARTIAL_TG_EN and USE_THREAD_DIMENSIONS must be 0.
994 */
995 if (sctx->has_graphics && !partial_block_en &&
996 !sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add) {
997 dispatch_initiator |= S_00B800_PING_PONG_EN(sctx->compute_ping_pong_launch);
998 sctx->compute_ping_pong_launch ^= 1;
999 }
1000
1001 /* Thread tiling within a workgroup. */
1002 switch (sctx->cs_shader_state.program->shader.selector->info.base.derivative_group) {
1003 case DERIVATIVE_GROUP_LINEAR:
1004 break;
1005 case DERIVATIVE_GROUP_QUADS:
1006 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(1); /* 2x2 */
1007 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(1);
1008 break;
1009 case DERIVATIVE_GROUP_NONE:
1010 /* These are the only legal combinations. */
1011 if (info->block[0] % 8 == 0 && info->block[1] % 8 == 0) {
1012 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(3); /* 8x8 */
1013 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(3);
1014 } else if (info->block[0] % 4 == 0 && info->block[1] % 8 == 0) {
1015 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(2); /* 4x8 */
1016 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(3);
1017 } else if (info->block[0] % 4 == 0 && info->block[1] % 4 == 0) {
1018 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(2); /* 4x4 */
1019 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(2);
1020 } else if (info->block[0] % 2 == 0 && info->block[1] % 2 == 0) {
1021 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(1); /* 2x2 */
1022 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(1);
1023 }
1024 break;
1025 }
1026
1027 /* How many threads should go to 1 SE before moving onto the next if INTERLEAVE_2D_EN == 0.
1028 * Only these values are valid: 0 (disabled), 64, 128, 256, 512
1029 * 64 = RT, 256 = non-RT (run benchmarks to be sure)
1030 */
1031 unsigned dispatch_interleave = S_00B8BC_INTERLEAVE_1D(256);
1032 unsigned log_x, log_y;
1033
1034 /* Launch a 2D subgrid on each SE instead of a 1D subgrid. If enabled, INTERLEAVE_1D is
1035 * ignored and each SE gets 1 subgrid up to a certain number of threads.
1036 *
1037 * Constraints:
1038 * - Only supported by the gfx queue.
1039 * - Max 16 workgroups per SE can be launched, max 4 in each dimension.
1040 * - PARTIAL_TG_EN, USE_THREAD_DIMENSIONS, and ORDERED_APPEND_ENBL must be 0.
1041 * - COMPUTE_START_X/Y are in units of 2D subgrids, not workgroups
1042 * (program COMPUTE_START_X to start_x >> log_x, COMPUTE_START_Y to start_y >> log_y).
1043 */
1044 if (sctx->has_graphics && !partial_block_en &&
1045 (info->indirect || info->grid[1] >= 4) && MIN2(info->block[0], info->block[1]) >= 4 &&
1046 si_get_2d_interleave_size(info, &log_x, &log_y)) {
1047 dispatch_interleave = S_00B8BC_INTERLEAVE_1D(1) || /* 1D is disabled */
1048 S_00B8BC_INTERLEAVE_2D_X_SIZE(log_x) |
1049 S_00B8BC_INTERLEAVE_2D_Y_SIZE(log_y);
1050 dispatch_initiator |= S_00B800_INTERLEAVE_2D_EN(1);
1051 }
1052
1053 if (sctx->has_graphics) {
1054 radeon_opt_set_sh_reg_idx(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
1055 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, 2, dispatch_interleave);
1056 } else {
1057 gfx12_opt_push_compute_sh_reg(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
1058 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, dispatch_interleave);
1059 }
1060 }
1061
1062 if (sctx->gfx_level >= GFX12) {
1063 gfx12_opt_push_compute_sh_reg(R_00B81C_COMPUTE_NUM_THREAD_X,
1064 SI_TRACKED_COMPUTE_NUM_THREAD_X, num_threads[0]);
1065 gfx12_opt_push_compute_sh_reg(R_00B820_COMPUTE_NUM_THREAD_Y,
1066 SI_TRACKED_COMPUTE_NUM_THREAD_Y, num_threads[1]);
1067 gfx12_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
1068 SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
1069 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
1070 gfx11_opt_push_compute_sh_reg(R_00B81C_COMPUTE_NUM_THREAD_X,
1071 SI_TRACKED_COMPUTE_NUM_THREAD_X, num_threads[0]);
1072 gfx11_opt_push_compute_sh_reg(R_00B820_COMPUTE_NUM_THREAD_Y,
1073 SI_TRACKED_COMPUTE_NUM_THREAD_Y, num_threads[1]);
1074 gfx11_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
1075 SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
1076 } else {
1077 radeon_opt_set_sh_reg3(R_00B81C_COMPUTE_NUM_THREAD_X,
1078 SI_TRACKED_COMPUTE_NUM_THREAD_X,
1079 num_threads[0], num_threads[1], num_threads[2]);
1080 }
1081
1082 if (sctx->gfx_level >= GFX12 || sctx->screen->info.has_set_sh_pairs_packed) {
1083 radeon_end();
1084 si_emit_buffered_compute_sh_regs(sctx);
1085 radeon_begin_again(cs);
1086 }
1087
1088 if (info->indirect) {
1089 uint64_t base_va = si_resource(info->indirect)->gpu_address;
1090
1091 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect),
1092 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1093
1094 radeon_emit(PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
1095 radeon_emit(1);
1096 radeon_emit(base_va);
1097 radeon_emit(base_va >> 32);
1098
1099 unsigned pkt = PKT3_DISPATCH_INDIRECT;
1100
1101 if (sctx->gfx_level >= GFX12 && G_00B800_INTERLEAVE_2D_EN(dispatch_initiator))
1102 pkt = PKT3_DISPATCH_INDIRECT_INTERLEAVED;
1103
1104 radeon_emit(PKT3(pkt, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
1105 radeon_emit(info->indirect_offset);
1106 radeon_emit(dispatch_initiator);
1107 } else {
1108 unsigned pkt = PKT3_DISPATCH_DIRECT;
1109
1110 if (sctx->gfx_level >= GFX12 && G_00B800_INTERLEAVE_2D_EN(dispatch_initiator))
1111 pkt = PKT3_DISPATCH_DIRECT_INTERLEAVED;
1112
1113 radeon_emit(PKT3(pkt, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
1114 radeon_emit(info->grid[0]);
1115 radeon_emit(info->grid[1]);
1116 radeon_emit(info->grid[2]);
1117 radeon_emit(dispatch_initiator);
1118 }
1119
1120 if (unlikely(sctx->sqtt_enabled && sctx->gfx_level >= GFX9))
1121 radeon_event_write(V_028A90_THREAD_TRACE_MARKER);
1122
1123 radeon_end();
1124 }
1125
si_check_needs_implicit_sync(struct si_context * sctx,uint32_t usage)1126 static bool si_check_needs_implicit_sync(struct si_context *sctx, uint32_t usage)
1127 {
1128 /* If the compute shader is going to read from a texture/image written by a
1129 * previous draw, we must wait for its completion before continuing.
1130 * Buffers and image stores (from the draw) are not taken into consideration
1131 * because that's the app responsibility.
1132 *
1133 * The OpenGL 4.6 spec says:
1134 *
1135 * buffer object and texture stores performed by shaders are not
1136 * automatically synchronized
1137 *
1138 * TODO: Bindless textures are not handled, and thus are not synchronized.
1139 */
1140 struct si_shader_info *info = &sctx->cs_shader_state.program->sel.info;
1141 struct si_samplers *samplers = &sctx->samplers[PIPE_SHADER_COMPUTE];
1142 unsigned mask = samplers->enabled_mask & info->base.textures_used[0];
1143
1144 while (mask) {
1145 int i = u_bit_scan(&mask);
1146 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
1147
1148 struct si_resource *res = si_resource(sview->base.texture);
1149 if (sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, res->buf, usage))
1150 return true;
1151 }
1152
1153 struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
1154 mask = u_bit_consecutive(0, info->base.num_images) & images->enabled_mask;
1155
1156 while (mask) {
1157 int i = u_bit_scan(&mask);
1158 struct pipe_image_view *sview = &images->views[i];
1159
1160 struct si_resource *res = si_resource(sview->resource);
1161 if (sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, res->buf, usage))
1162 return true;
1163 }
1164 return false;
1165 }
1166
si_launch_grid(struct pipe_context * ctx,const struct pipe_grid_info * info)1167 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
1168 {
1169 struct si_context *sctx = (struct si_context *)ctx;
1170 struct si_screen *sscreen = sctx->screen;
1171 struct si_compute *program = sctx->cs_shader_state.program;
1172 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
1173 int i;
1174 bool cs_regalloc_hang = sscreen->info.has_cs_regalloc_hang_bug &&
1175 info->block[0] * info->block[1] * info->block[2] > 256;
1176
1177 if (cs_regalloc_hang) {
1178 sctx->barrier_flags |= SI_BARRIER_SYNC_PS | SI_BARRIER_SYNC_CS;
1179 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1180 }
1181
1182 if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
1183 return;
1184
1185 si_check_dirty_buffers_textures(sctx);
1186
1187 if (sctx->has_graphics) {
1188 if (sctx->num_draw_calls_sh_coherent.with_cb != sctx->num_draw_calls ||
1189 sctx->num_draw_calls_sh_coherent.with_db != sctx->num_draw_calls) {
1190 bool sync_cb = sctx->force_shader_coherency.with_cb ||
1191 si_check_needs_implicit_sync(sctx, RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC);
1192 bool sync_db = sctx->gfx_level == GFX12 &&
1193 (sctx->force_shader_coherency.with_db ||
1194 si_check_needs_implicit_sync(sctx, RADEON_USAGE_DB_NEEDS_IMPLICIT_SYNC));
1195
1196 si_fb_barrier_after_rendering(sctx,
1197 (sync_cb ? SI_FB_BARRIER_SYNC_CB : 0) |
1198 (sync_db ? SI_FB_BARRIER_SYNC_DB : 0));
1199
1200 if (sync_cb)
1201 sctx->num_draw_calls_sh_coherent.with_cb = sctx->num_draw_calls;
1202
1203 if (sync_db)
1204 sctx->num_draw_calls_sh_coherent.with_db = sctx->num_draw_calls;
1205 }
1206
1207 if (sctx->gfx_level < GFX11)
1208 gfx6_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
1209 else if (sctx->gfx_level < GFX12)
1210 gfx11_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
1211 }
1212
1213 if (info->indirect) {
1214 /* Indirect buffers are read through L2 on GFX9-GFX11, but not other hw. */
1215 if ((sctx->gfx_level <= GFX8 || sctx->gfx_level == GFX12) &&
1216 si_resource(info->indirect)->L2_cache_dirty) {
1217 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
1218 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1219 si_resource(info->indirect)->L2_cache_dirty = false;
1220 }
1221 }
1222
1223 si_need_gfx_cs_space(sctx, 0);
1224
1225 /* If we're using a secure context, determine if cs must be secure or not */
1226 if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
1227 bool secure = si_compute_resources_check_encrypted(sctx);
1228 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) {
1229 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW |
1230 RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION,
1231 NULL);
1232 }
1233 }
1234
1235 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1236 trace_si_begin_compute(&sctx->trace);
1237
1238 if (sctx->bo_list_add_all_compute_resources)
1239 si_compute_resources_add_all_to_bo_list(sctx);
1240
1241 /* Skipping setting redundant registers on compute queues breaks compute. */
1242 if (!sctx->has_graphics) {
1243 BITSET_CLEAR_RANGE(sctx->tracked_regs.reg_saved_mask,
1244 SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1);
1245 }
1246
1247 /* First emit registers. */
1248 bool prefetch;
1249 if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc, &prefetch,
1250 info->variable_shared_mem))
1251 return;
1252
1253 si_emit_compute_shader_pointers(sctx);
1254
1255 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
1256 unlikely(!si_upload_compute_input(sctx, code_object, info)))
1257 return;
1258
1259 /* Global buffers */
1260 for (i = 0; i < program->max_global_buffers; i++) {
1261 struct si_resource *buffer = si_resource(program->global_buffers[i]);
1262 if (!buffer) {
1263 continue;
1264 }
1265 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer,
1266 RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RW_BUFFER);
1267 }
1268
1269 /* Registers that are not read from memory should be set before this: */
1270 si_emit_barrier_direct(sctx);
1271
1272 if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
1273 sctx->atoms.s.render_cond.emit(sctx, -1);
1274 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
1275 }
1276
1277 /* Prefetch the compute shader to L2. */
1278 if (sctx->gfx_level >= GFX7 && sctx->screen->info.has_cp_dma && prefetch)
1279 si_cp_dma_prefetch(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
1280
1281 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
1282 si_setup_nir_user_data(sctx, info);
1283
1284 si_emit_dispatch_packets(sctx, info);
1285
1286 if (unlikely(sctx->current_saved_cs)) {
1287 si_trace_emit(sctx);
1288 si_log_compute_state(sctx, sctx->log);
1289 }
1290
1291 if (sctx->gfx_level < GFX12) {
1292 /* Mark displayable DCC as dirty for bound images. */
1293 unsigned display_dcc_store_mask = sctx->images[PIPE_SHADER_COMPUTE].display_dcc_store_mask &
1294 BITFIELD_MASK(program->sel.info.base.num_images);
1295 while (display_dcc_store_mask) {
1296 struct si_texture *tex = (struct si_texture *)
1297 sctx->images[PIPE_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
1298
1299 si_mark_display_dcc_dirty(sctx, tex);
1300 }
1301
1302 /* TODO: Bindless images don't set displayable_dcc_dirty after image stores. */
1303 }
1304
1305 sctx->compute_is_busy = true;
1306 sctx->num_compute_calls++;
1307
1308 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1309 trace_si_end_compute(&sctx->trace, info->grid[0], info->grid[1], info->grid[2]);
1310
1311 if (cs_regalloc_hang) {
1312 sctx->barrier_flags |= SI_BARRIER_SYNC_CS;
1313 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1314 }
1315 }
1316
si_destroy_compute(struct si_compute * program)1317 void si_destroy_compute(struct si_compute *program)
1318 {
1319 struct si_shader_selector *sel = &program->sel;
1320
1321 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
1322 util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
1323 util_queue_fence_destroy(&sel->ready);
1324 }
1325
1326 for (unsigned i = 0; i < program->max_global_buffers; i++)
1327 pipe_resource_reference(&program->global_buffers[i], NULL);
1328 FREE(program->global_buffers);
1329
1330 si_shader_destroy(&program->shader);
1331 ralloc_free(program->sel.nir);
1332 simple_mtx_destroy(&sel->mutex);
1333 FREE(program);
1334 }
1335
si_delete_compute_state(struct pipe_context * ctx,void * state)1336 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
1337 {
1338 struct si_compute *program = (struct si_compute *)state;
1339 struct si_context *sctx = (struct si_context *)ctx;
1340
1341 if (!state)
1342 return;
1343
1344 if (program == sctx->cs_shader_state.program)
1345 sctx->cs_shader_state.program = NULL;
1346
1347 if (program == sctx->cs_shader_state.emitted_program)
1348 sctx->cs_shader_state.emitted_program = NULL;
1349
1350 si_compute_reference(&program, NULL);
1351 }
1352
si_set_compute_resources(struct pipe_context * ctx_,unsigned start,unsigned count,struct pipe_surface ** surfaces)1353 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
1354 struct pipe_surface **surfaces)
1355 {
1356 }
1357
si_init_compute_functions(struct si_context * sctx)1358 void si_init_compute_functions(struct si_context *sctx)
1359 {
1360 sctx->b.create_compute_state = si_create_compute_state;
1361 sctx->b.delete_compute_state = si_delete_compute_state;
1362 sctx->b.bind_compute_state = si_bind_compute_state;
1363 sctx->b.get_compute_state_info = si_get_compute_state_info;
1364 sctx->b.set_compute_resources = si_set_compute_resources;
1365 sctx->b.set_global_binding = si_set_global_binding;
1366 sctx->b.launch_grid = si_launch_grid;
1367
1368 #if 0 /* test for si_get_2d_interleave_size */
1369 static bool visited = false;
1370 if (visited)
1371 return;
1372
1373 visited = true;
1374 struct pipe_grid_info info = {};
1375 info.grid[0] = info.grid[1] = info.grid[2] = 1024;
1376 info.block[2] = 1;
1377
1378 for (unsigned block_3d = 0; block_3d < 2; block_3d++) {
1379 printf(" WG size | WG block/SE | Thread block/SE\n");
1380
1381 for (unsigned x = 1; x <= 32; x *= 2) {
1382 for (unsigned y = 1; y <= 32; y *= 2) {
1383 info.block[0] = x;
1384 info.block[1] = y;
1385 info.block[2] = block_3d ? 8 : 1;
1386
1387 if ((x * y) % 32)
1388 continue;
1389
1390 unsigned log_x, log_y;
1391 if (!si_get_2d_interleave_size(&info, &log_x, &log_y))
1392 continue;
1393
1394 printf(" (%2u, %2u) = %3u | (%2u, %2u) = %2u | (%3u,%3u) = %u\n",
1395 info.block[0], info.block[1], info.block[0] * info.block[1],
1396 1 << log_x, 1 << log_y, (1 << log_x) * (1 << log_y),
1397 info.block[0] * (1 << log_x), info.block[1] * (1 << log_y),
1398 info.block[0] * (1 << log_x) * info.block[1] * (1 << log_y));
1399 }
1400 }
1401 }
1402 #endif
1403 }
1404