1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "compiler/nir/nir.h"
8 #include "ac_nir.h"
9 #include "ac_shader_util.h"
10 #include "radeon_uvd_enc.h"
11 #include "radeon_vce.h"
12 #include "radeon_video.h"
13 #include "si_pipe.h"
14 #include "util/u_cpu_detect.h"
15 #include "util/u_screen.h"
16 #include "util/u_video.h"
17 #include "vl/vl_decoder.h"
18 #include "vl/vl_video_buffer.h"
19 #include <sys/utsname.h>
20
21 /* The capabilities reported by the kernel has priority
22 over the existing logic in si_get_video_param */
23 #define QUERYABLE_KERNEL (sscreen->info.is_amdgpu && \
24 !!(sscreen->info.drm_minor >= 41))
25 #define KERNEL_DEC_CAP(codec, attrib) \
26 (codec > PIPE_VIDEO_FORMAT_UNKNOWN && codec <= PIPE_VIDEO_FORMAT_AV1) ? \
27 (sscreen->info.dec_caps.codec_info[codec - 1].valid ? \
28 sscreen->info.dec_caps.codec_info[codec - 1].attrib : 0) : 0
29 #define KERNEL_ENC_CAP(codec, attrib) \
30 (codec > PIPE_VIDEO_FORMAT_UNKNOWN && codec <= PIPE_VIDEO_FORMAT_AV1) ? \
31 (sscreen->info.enc_caps.codec_info[codec - 1].valid ? \
32 sscreen->info.enc_caps.codec_info[codec - 1].attrib : 0) : 0
33
si_get_vendor(struct pipe_screen * pscreen)34 static const char *si_get_vendor(struct pipe_screen *pscreen)
35 {
36 return "AMD";
37 }
38
si_get_device_vendor(struct pipe_screen * pscreen)39 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
40 {
41 return "AMD";
42 }
43
44 static bool
si_is_compute_copy_faster(struct pipe_screen * pscreen,enum pipe_format src_format,enum pipe_format dst_format,unsigned width,unsigned height,unsigned depth,bool cpu)45 si_is_compute_copy_faster(struct pipe_screen *pscreen,
46 enum pipe_format src_format,
47 enum pipe_format dst_format,
48 unsigned width,
49 unsigned height,
50 unsigned depth,
51 bool cpu)
52 {
53 if (cpu)
54 /* very basic for now */
55 return width * height * depth > 64 * 64;
56 return false;
57 }
58
si_get_param(struct pipe_screen * pscreen,enum pipe_cap param)59 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
60 {
61 struct si_screen *sscreen = (struct si_screen *)pscreen;
62
63 /* Gfx8 (Polaris11) hangs, so don't enable this on Gfx8 and older chips. */
64 bool enable_sparse = sscreen->info.gfx_level >= GFX9 && sscreen->info.gfx_level < GFX12 &&
65 sscreen->info.has_sparse_vm_mappings;
66
67 switch (param) {
68 /* Supported features (boolean caps). */
69 case PIPE_CAP_ACCELERATED:
70 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
71 case PIPE_CAP_ANISOTROPIC_FILTER:
72 case PIPE_CAP_OCCLUSION_QUERY:
73 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
74 case PIPE_CAP_TEXTURE_SHADOW_LOD:
75 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
76 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
77 case PIPE_CAP_TEXTURE_SWIZZLE:
78 case PIPE_CAP_DEPTH_CLIP_DISABLE:
79 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
80 case PIPE_CAP_SHADER_STENCIL_EXPORT:
81 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
82 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
83 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
84 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
85 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
86 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
87 case PIPE_CAP_PRIMITIVE_RESTART:
88 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
89 case PIPE_CAP_CONDITIONAL_RENDER:
90 case PIPE_CAP_TEXTURE_BARRIER:
91 case PIPE_CAP_INDEP_BLEND_ENABLE:
92 case PIPE_CAP_INDEP_BLEND_FUNC:
93 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
94 case PIPE_CAP_START_INSTANCE:
95 case PIPE_CAP_NPOT_TEXTURES:
96 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
97 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
98 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
99 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
100 case PIPE_CAP_VS_INSTANCEID:
101 case PIPE_CAP_COMPUTE:
102 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
103 case PIPE_CAP_VS_LAYER_VIEWPORT:
104 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
105 case PIPE_CAP_SAMPLE_SHADING:
106 case PIPE_CAP_DRAW_INDIRECT:
107 case PIPE_CAP_CLIP_HALFZ:
108 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
109 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
110 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
111 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
112 case PIPE_CAP_TGSI_TEXCOORD:
113 case PIPE_CAP_FS_FINE_DERIVATIVE:
114 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
115 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
116 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
117 case PIPE_CAP_DEPTH_BOUNDS_TEST:
118 case PIPE_CAP_SAMPLER_VIEW_TARGET:
119 case PIPE_CAP_TEXTURE_QUERY_LOD:
120 case PIPE_CAP_TEXTURE_GATHER_SM5:
121 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
122 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
123 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
124 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
125 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
126 case PIPE_CAP_INVALIDATE_BUFFER:
127 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
128 case PIPE_CAP_QUERY_BUFFER_OBJECT:
129 case PIPE_CAP_QUERY_MEMORY_INFO:
130 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
131 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
132 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
133 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
134 case PIPE_CAP_STRING_MARKER:
135 case PIPE_CAP_CULL_DISTANCE:
136 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
137 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
138 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
139 case PIPE_CAP_DOUBLES:
140 case PIPE_CAP_TGSI_TEX_TXF_LZ:
141 case PIPE_CAP_TES_LAYER_VIEWPORT:
142 case PIPE_CAP_BINDLESS_TEXTURE:
143 case PIPE_CAP_QUERY_TIMESTAMP:
144 case PIPE_CAP_QUERY_TIME_ELAPSED:
145 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
146 case PIPE_CAP_MEMOBJ:
147 case PIPE_CAP_LOAD_CONSTBUF:
148 case PIPE_CAP_INT64:
149 case PIPE_CAP_SHADER_CLOCK:
150 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
151 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
152 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
153 case PIPE_CAP_SHADER_BALLOT:
154 case PIPE_CAP_SHADER_GROUP_VOTE:
155 case PIPE_CAP_FBFETCH:
156 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
157 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
158 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
159 case PIPE_CAP_TGSI_DIV:
160 case PIPE_CAP_PACKED_UNIFORMS:
161 case PIPE_CAP_GL_SPIRV:
162 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
163 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
164 case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
165 case PIPE_CAP_SHADER_ATOMIC_INT64:
166 case PIPE_CAP_FRONTEND_NOOP:
167 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
168 case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
169 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
170 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
171 case PIPE_CAP_IMAGE_STORE_FORMATTED:
172 case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER:
173 case PIPE_CAP_QUERY_SO_OVERFLOW:
174 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
175 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
176 case PIPE_CAP_TEXTURE_MULTISAMPLE:
177 case PIPE_CAP_ALLOW_GLTHREAD_BUFFER_SUBDATA_OPT: /* TODO: remove if it's slow */
178 case PIPE_CAP_NULL_TEXTURES:
179 case PIPE_CAP_HAS_CONST_BW:
180 case PIPE_CAP_CL_GL_SHARING:
181 return 1;
182
183 /* Tahiti and Verde only: reduction mode is unsupported due to a bug
184 * (it might work sometimes, but that's not enough)
185 */
186 case PIPE_CAP_SAMPLER_REDUCTION_MINMAX:
187 case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB:
188 return !(sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_VERDE);
189
190 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
191 return PIPE_TEXTURE_TRANSFER_BLIT | PIPE_TEXTURE_TRANSFER_COMPUTE;
192
193 case PIPE_CAP_DRAW_VERTEX_STATE:
194 return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST));
195
196 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
197 return sscreen->info.gfx_level < GFX11 && !(sscreen->debug_flags & DBG(NO_FMASK));
198
199 case PIPE_CAP_GLSL_ZERO_INIT:
200 return 2;
201
202 case PIPE_CAP_GENERATE_MIPMAP:
203 case PIPE_CAP_SEAMLESS_CUBE_MAP:
204 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
205 case PIPE_CAP_CUBE_MAP_ARRAY:
206 return sscreen->info.has_3d_cube_border_color_mipmap;
207
208 case PIPE_CAP_POST_DEPTH_COVERAGE:
209 return sscreen->info.gfx_level >= GFX10;
210
211 case PIPE_CAP_GRAPHICS:
212 return sscreen->info.has_graphics;
213
214 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
215 return !UTIL_ARCH_BIG_ENDIAN && sscreen->info.has_userptr;
216
217 case PIPE_CAP_DEVICE_PROTECTED_SURFACE:
218 return sscreen->info.has_tmz_support;
219
220 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
221 return SI_MAP_BUFFER_ALIGNMENT;
222
223 case PIPE_CAP_MAX_VERTEX_BUFFERS:
224 return SI_MAX_ATTRIBS;
225
226 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
227 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
228 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
229 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
230 case PIPE_CAP_MAX_VERTEX_STREAMS:
231 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
232 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
233 return 4;
234
235 case PIPE_CAP_GLSL_FEATURE_LEVEL:
236 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
237 return 460;
238
239 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
240 /* Optimal number for good TexSubImage performance on Polaris10. */
241 return 64 * 1024 * 1024;
242
243 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
244 return 4096 * 1024;
245
246 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT: {
247 unsigned max_texels =
248 pscreen->get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT);
249
250 /* FYI, BUF_RSRC_WORD2.NUM_RECORDS field limit is UINT32_MAX. */
251
252 /* Gfx8 and older use the size in bytes for bounds checking, and the max element size
253 * is 16B. Gfx9 and newer use the VGPR index for bounds checking.
254 */
255 if (sscreen->info.gfx_level <= GFX8)
256 max_texels = MIN2(max_texels, UINT32_MAX / 16);
257 else
258 /* Gallium has a limitation that it can only bind UINT32_MAX bytes, not texels.
259 * TODO: Remove this after the gallium interface is changed. */
260 max_texels = MIN2(max_texels, UINT32_MAX / 16);
261
262 return max_texels;
263 }
264
265 case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
266 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: {
267 /* Return 1/4th of the heap size as the maximum because the max size is not practically
268 * allocatable. Also, this can only return UINT32_MAX at most.
269 */
270 unsigned max_size = MIN2((sscreen->info.max_heap_size_kb * 1024ull) / 4, UINT32_MAX);
271
272 /* Allow max 512 MB to pass CTS with a 32-bit build. */
273 if (sizeof(void*) == 4)
274 max_size = MIN2(max_size, 512 * 1024 * 1024);
275
276 return max_size;
277 }
278
279 case PIPE_CAP_MAX_TEXTURE_MB:
280 /* Allow 1/4th of the heap size. */
281 return sscreen->info.max_heap_size_kb / 1024 / 4;
282
283 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
284 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
285 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
286 case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
287 case PIPE_CAP_UMA:
288 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
289 return 0;
290
291 case PIPE_CAP_PERFORMANCE_MONITOR:
292 return sscreen->info.gfx_level >= GFX7 && sscreen->info.gfx_level <= GFX10_3;
293
294 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
295 return enable_sparse ? RADEON_SPARSE_PAGE_SIZE : 0;
296
297 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
298 if (!sscreen->info.is_amdgpu)
299 return 0;
300 return PIPE_CONTEXT_PRIORITY_LOW |
301 PIPE_CONTEXT_PRIORITY_MEDIUM |
302 PIPE_CONTEXT_PRIORITY_HIGH;
303
304 case PIPE_CAP_FENCE_SIGNAL:
305 return sscreen->info.has_syncobj;
306
307 case PIPE_CAP_CONSTBUF0_FLAGS:
308 return SI_RESOURCE_FLAG_32BIT;
309
310 case PIPE_CAP_NATIVE_FENCE_FD:
311 return sscreen->info.has_fence_to_handle;
312
313 case PIPE_CAP_DRAW_PARAMETERS:
314 case PIPE_CAP_MULTI_DRAW_INDIRECT:
315 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
316 return sscreen->has_draw_indirect_multi;
317
318 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
319 return 30;
320
321 case PIPE_CAP_MAX_VARYINGS:
322 case PIPE_CAP_MAX_GS_INVOCATIONS:
323 return 32;
324
325 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
326 return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
327
328 /* Stream output. */
329 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
330 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
331 return 32 * 4;
332
333 /* Geometry shader output. */
334 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
335 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
336 * gfx8 and earlier can do 1024.
337 */
338 return 256;
339 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
340 return 4095;
341
342 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
343 return 2048;
344
345 /* Texturing. */
346 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
347 /* TODO: Gfx12 supports 64K textures, but Gallium can't represent them at the moment. */
348 return sscreen->info.gfx_level >= GFX12 ? 32768 : 16384;
349 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
350 if (!sscreen->info.has_3d_cube_border_color_mipmap)
351 return 0;
352 return sscreen->info.gfx_level >= GFX12 ? 16 : 15; /* 32K : 16K */
353 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
354 if (!sscreen->info.has_3d_cube_border_color_mipmap)
355 return 0;
356 /* This is limited by maximums that both the texture unit and layered rendering support. */
357 return sscreen->info.gfx_level >= GFX12 ? 15 : /* 16K */
358 sscreen->info.gfx_level >= GFX10 ? 14 : 12; /* 8K : 2K */
359 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
360 /* This is limited by maximums that both the texture unit and layered rendering support. */
361 return sscreen->info.gfx_level >= GFX10 ? 8192 : 2048;
362
363 /* Sparse texture */
364 case PIPE_CAP_MAX_SPARSE_TEXTURE_SIZE:
365 return enable_sparse ?
366 si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_2D_SIZE) : 0;
367 case PIPE_CAP_MAX_SPARSE_3D_TEXTURE_SIZE:
368 return enable_sparse ?
369 (1 << (si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_3D_LEVELS) - 1)) : 0;
370 case PIPE_CAP_MAX_SPARSE_ARRAY_TEXTURE_LAYERS:
371 return enable_sparse ?
372 si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS) : 0;
373 case PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS:
374 case PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY:
375 case PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD:
376 return enable_sparse;
377
378 /* Viewports and render targets. */
379 case PIPE_CAP_MAX_VIEWPORTS:
380 return SI_MAX_VIEWPORTS;
381 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
382 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
383 case PIPE_CAP_MAX_RENDER_TARGETS:
384 return 8;
385 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
386 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
387
388 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
389 case PIPE_CAP_MIN_TEXEL_OFFSET:
390 return -32;
391
392 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
393 case PIPE_CAP_MAX_TEXEL_OFFSET:
394 return 31;
395
396 case PIPE_CAP_ENDIANNESS:
397 return PIPE_ENDIAN_LITTLE;
398
399 case PIPE_CAP_VENDOR_ID:
400 return ATI_VENDOR_ID;
401 case PIPE_CAP_DEVICE_ID:
402 return sscreen->info.pci_id;
403 case PIPE_CAP_VIDEO_MEMORY:
404 return sscreen->info.vram_size_kb >> 10;
405 case PIPE_CAP_PCI_GROUP:
406 return sscreen->info.pci.domain;
407 case PIPE_CAP_PCI_BUS:
408 return sscreen->info.pci.bus;
409 case PIPE_CAP_PCI_DEVICE:
410 return sscreen->info.pci.dev;
411 case PIPE_CAP_PCI_FUNCTION:
412 return sscreen->info.pci.func;
413
414 case PIPE_CAP_TIMER_RESOLUTION:
415 /* Conversion to nanos from cycles per millisecond */
416 return DIV_ROUND_UP(1000000, sscreen->info.clock_crystal_freq);
417
418 case PIPE_CAP_SHADER_SUBGROUP_SIZE:
419 return 64;
420 case PIPE_CAP_SHADER_SUBGROUP_SUPPORTED_STAGES:
421 return BITFIELD_MASK(PIPE_SHADER_TYPES);
422 case PIPE_CAP_SHADER_SUBGROUP_SUPPORTED_FEATURES:
423 return BITFIELD_MASK(PIPE_SHADER_SUBGROUP_NUM_FEATURES);
424 case PIPE_CAP_SHADER_SUBGROUP_QUAD_ALL_STAGES:
425 return true;
426
427 default:
428 return u_pipe_screen_get_param_defaults(pscreen, param);
429 }
430 }
431
si_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)432 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
433 {
434 switch (param) {
435 case PIPE_CAPF_MIN_LINE_WIDTH:
436 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
437 return 1; /* due to axis-aligned end caps at line width 1 */
438 case PIPE_CAPF_MIN_POINT_SIZE:
439 case PIPE_CAPF_MIN_POINT_SIZE_AA:
440 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
441 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
442 return 1.0 / 8.0; /* due to the register field precision */
443 case PIPE_CAPF_MAX_LINE_WIDTH:
444 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
445 /* This depends on the quant mode, though the precise interactions
446 * are unknown. */
447 return 2048;
448 case PIPE_CAPF_MAX_POINT_SIZE:
449 case PIPE_CAPF_MAX_POINT_SIZE_AA:
450 return SI_MAX_POINT_SIZE;
451 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
452 return 16.0f;
453 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
454 /* The hw can do 31, but this test fails if we use that:
455 * KHR-GL46.texture_lod_bias.texture_lod_bias_all
456 */
457 return 16;
458 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
459 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
460 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
461 return 0.0f;
462 }
463 return 0.0f;
464 }
465
si_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)466 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
467 enum pipe_shader_cap param)
468 {
469 struct si_screen *sscreen = (struct si_screen *)pscreen;
470
471 if (shader == PIPE_SHADER_MESH ||
472 shader == PIPE_SHADER_TASK)
473 return 0;
474
475 switch (param) {
476 /* Shader limits. */
477 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
478 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
479 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
480 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
481 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
482 return 16384;
483 case PIPE_SHADER_CAP_MAX_INPUTS:
484 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
485 case PIPE_SHADER_CAP_MAX_OUTPUTS:
486 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
487 case PIPE_SHADER_CAP_MAX_TEMPS:
488 return 256; /* Max native temporaries. */
489 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
490 return 1 << 26; /* 64 MB */
491 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
492 return SI_NUM_CONST_BUFFERS;
493 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
494 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
495 return SI_NUM_SAMPLERS;
496 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
497 return SI_NUM_SHADER_BUFFERS;
498 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
499 return SI_NUM_IMAGES;
500
501 case PIPE_SHADER_CAP_SUPPORTED_IRS:
502 if (shader == PIPE_SHADER_COMPUTE) {
503 return (1 << PIPE_SHADER_IR_NATIVE) |
504 (1 << PIPE_SHADER_IR_NIR) |
505 (1 << PIPE_SHADER_IR_TGSI);
506 }
507 return (1 << PIPE_SHADER_IR_TGSI) |
508 (1 << PIPE_SHADER_IR_NIR);
509
510 /* Supported boolean features. */
511 case PIPE_SHADER_CAP_CONT_SUPPORTED:
512 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
513 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
514 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
515 case PIPE_SHADER_CAP_INTEGERS:
516 case PIPE_SHADER_CAP_INT64_ATOMICS:
517 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
518 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
519 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
520 return 1;
521
522 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
523 /* We need f16c for fast FP16 conversions in glUniform. */
524 if (!util_get_cpu_caps()->has_f16c)
525 return 0;
526 FALLTHROUGH;
527 case PIPE_SHADER_CAP_FP16:
528 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
529 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
530 case PIPE_SHADER_CAP_INT16:
531 return sscreen->nir_options->lower_mediump_io != NULL;
532
533 /* Unsupported boolean features. */
534 case PIPE_SHADER_CAP_SUBROUTINES:
535 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
536 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
537 return 0;
538 }
539 return 0;
540 }
541
si_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)542 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
543 enum pipe_shader_type shader)
544 {
545 struct si_screen *sscreen = (struct si_screen *)screen;
546
547 assert(ir == PIPE_SHADER_IR_NIR);
548 return sscreen->nir_options;
549 }
550
si_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)551 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
552 {
553 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
554 }
555
si_get_device_uuid(struct pipe_screen * pscreen,char * uuid)556 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
557 {
558 struct si_screen *sscreen = (struct si_screen *)pscreen;
559
560 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
561 }
562
si_get_name(struct pipe_screen * pscreen)563 static const char *si_get_name(struct pipe_screen *pscreen)
564 {
565 struct si_screen *sscreen = (struct si_screen *)pscreen;
566
567 return sscreen->renderer_string;
568 }
569
si_get_video_param_no_video_hw(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)570 static int si_get_video_param_no_video_hw(struct pipe_screen *screen, enum pipe_video_profile profile,
571 enum pipe_video_entrypoint entrypoint,
572 enum pipe_video_cap param)
573 {
574 switch (param) {
575 case PIPE_VIDEO_CAP_SUPPORTED:
576 return vl_profile_supported(screen, profile, entrypoint);
577 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
578 return 1;
579 case PIPE_VIDEO_CAP_MAX_WIDTH:
580 case PIPE_VIDEO_CAP_MAX_HEIGHT:
581 return vl_video_buffer_max_size(screen);
582 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
583 return PIPE_FORMAT_NV12;
584 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
585 return false;
586 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
587 return false;
588 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
589 return true;
590 case PIPE_VIDEO_CAP_MAX_LEVEL:
591 return vl_level_supported(screen, profile);
592 default:
593 return 0;
594 }
595 }
596
si_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)597 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
598 enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
599 {
600 struct si_screen *sscreen = (struct si_screen *)screen;
601 enum pipe_video_format codec = u_reduce_video_profile(profile);
602 bool fully_supported_profile = ((profile >= PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE) &&
603 (profile <= PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH)) ||
604 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN) ||
605 (profile == PIPE_VIDEO_PROFILE_AV1_MAIN);
606
607 /* Return the capability of Video Post Processor.
608 * Have to determine the HW version of VPE.
609 * Have to check the HW limitation and
610 * Check if the VPE exists and is valid
611 */
612 if (sscreen->info.ip[AMD_IP_VPE].num_queues && entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
613
614 switch(param) {
615 case PIPE_VIDEO_CAP_SUPPORTED:
616 return true;
617 case PIPE_VIDEO_CAP_MAX_WIDTH:
618 return 10240;
619 case PIPE_VIDEO_CAP_MAX_HEIGHT:
620 return 10240;
621 case PIPE_VIDEO_CAP_VPP_MAX_INPUT_WIDTH:
622 return 10240;
623 case PIPE_VIDEO_CAP_VPP_MAX_INPUT_HEIGHT:
624 return 10240;
625 case PIPE_VIDEO_CAP_VPP_MIN_INPUT_WIDTH:
626 return 16;
627 case PIPE_VIDEO_CAP_VPP_MIN_INPUT_HEIGHT:
628 return 16;
629 case PIPE_VIDEO_CAP_VPP_MAX_OUTPUT_WIDTH:
630 return 10240;
631 case PIPE_VIDEO_CAP_VPP_MAX_OUTPUT_HEIGHT:
632 return 10240;
633 case PIPE_VIDEO_CAP_VPP_MIN_OUTPUT_WIDTH:
634 return 16;
635 case PIPE_VIDEO_CAP_VPP_MIN_OUTPUT_HEIGHT:
636 return 16;
637 case PIPE_VIDEO_CAP_VPP_ORIENTATION_MODES:
638 /* VPE 1st generation does not support orientation
639 * Have to determine the version and features of VPE in future.
640 */
641 return PIPE_VIDEO_VPP_ORIENTATION_DEFAULT;
642 case PIPE_VIDEO_CAP_VPP_BLEND_MODES:
643 /* VPE 1st generation does not support blending.
644 * Have to determine the version and features of VPE in future.
645 */
646 return PIPE_VIDEO_VPP_BLEND_MODE_NONE;
647 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
648 return PIPE_FORMAT_NV12;
649 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
650 return false;
651 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
652 return true;
653 case PIPE_VIDEO_CAP_REQUIRES_FLUSH_ON_END_FRAME:
654 /* true: VPP flush function will be called within vaEndPicture() */
655 /* false: VPP flush function will be skipped */
656 return false;
657 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
658 /* for VPE we prefer non-interlaced buffer */
659 return false;
660 default:
661 return 0;
662 }
663 }
664
665 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
666 if (!(sscreen->info.ip[AMD_IP_VCE].num_queues ||
667 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues ||
668 sscreen->info.ip[AMD_IP_VCN_ENC].num_queues))
669 return 0;
670
671 if (sscreen->info.vcn_ip_version == VCN_4_0_3)
672 return 0;
673
674 switch (param) {
675 case PIPE_VIDEO_CAP_SUPPORTED:
676 return (
677 /* in case it is explicitly marked as not supported by the kernel */
678 ((QUERYABLE_KERNEL && fully_supported_profile) ? KERNEL_ENC_CAP(codec, valid) : 1) &&
679 ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && profile != PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10 &&
680 (sscreen->info.vcn_ip_version >= VCN_1_0_0 || si_vce_is_fw_version_supported(sscreen))) ||
681 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
682 (sscreen->info.vcn_ip_version >= VCN_1_0_0 || si_radeon_uvd_enc_supported(sscreen))) ||
683 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.vcn_ip_version >= VCN_2_0_0) ||
684 (profile == PIPE_VIDEO_PROFILE_AV1_MAIN &&
685 (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3))));
686 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
687 return 1;
688 case PIPE_VIDEO_CAP_MIN_WIDTH:
689 return (codec == PIPE_VIDEO_FORMAT_HEVC) ? 130 : 128;
690 case PIPE_VIDEO_CAP_MIN_HEIGHT:
691 return 128;
692 case PIPE_VIDEO_CAP_MAX_WIDTH:
693 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
694 return KERNEL_ENC_CAP(codec, max_width);
695 else
696 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
697 case PIPE_VIDEO_CAP_MAX_HEIGHT:
698 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
699 return KERNEL_ENC_CAP(codec, max_height);
700 else
701 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
702 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
703 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
704 return PIPE_FORMAT_P010;
705 else
706 return PIPE_FORMAT_NV12;
707 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
708 return false;
709 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
710 return false;
711 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
712 return true;
713 case PIPE_VIDEO_CAP_STACKED_FRAMES:
714 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
715 case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS:
716 return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
717 sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 4 : 0;
718 case PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL:
719 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 32 : 0;
720 case PIPE_VIDEO_CAP_ENC_SUPPORTS_MAX_FRAME_SIZE:
721 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
722
723 case PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS:
724 if ((sscreen->info.vcn_ip_version >= VCN_1_0_0) &&
725 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
726 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
727 union pipe_h265_enc_cap_features pipe_features;
728 pipe_features.value = 0;
729
730 pipe_features.bits.amp = PIPE_ENC_FEATURE_SUPPORTED;
731 pipe_features.bits.strong_intra_smoothing = PIPE_ENC_FEATURE_SUPPORTED;
732 pipe_features.bits.constrained_intra_pred = PIPE_ENC_FEATURE_SUPPORTED;
733 pipe_features.bits.deblocking_filter_disable
734 = PIPE_ENC_FEATURE_SUPPORTED;
735 if (sscreen->info.vcn_ip_version >= VCN_2_0_0) {
736 pipe_features.bits.sao = PIPE_ENC_FEATURE_SUPPORTED;
737 pipe_features.bits.cu_qp_delta = PIPE_ENC_FEATURE_SUPPORTED;
738 }
739 if (sscreen->info.vcn_ip_version >= VCN_3_0_0)
740 pipe_features.bits.transform_skip = PIPE_ENC_FEATURE_SUPPORTED;
741
742 return pipe_features.value;
743 } else
744 return 0;
745
746 case PIPE_VIDEO_CAP_ENC_HEVC_BLOCK_SIZES:
747 if (sscreen->info.vcn_ip_version >= VCN_1_0_0 &&
748 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
749 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
750 union pipe_h265_enc_cap_block_sizes pipe_block_sizes;
751 pipe_block_sizes.value = 0;
752
753 pipe_block_sizes.bits.log2_max_coding_tree_block_size_minus3 = 3;
754 pipe_block_sizes.bits.log2_min_coding_tree_block_size_minus3 = 3;
755 pipe_block_sizes.bits.log2_min_luma_coding_block_size_minus3 = 0;
756 pipe_block_sizes.bits.log2_max_luma_transform_block_size_minus2 = 3;
757 pipe_block_sizes.bits.log2_min_luma_transform_block_size_minus2 = 0;
758
759 return pipe_block_sizes.value;
760 } else
761 return 0;
762
763 case PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION:
764 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
765
766 case PIPE_VIDEO_CAP_ENC_MAX_SLICES_PER_FRAME:
767 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 128 : 1;
768
769 case PIPE_VIDEO_CAP_ENC_SLICES_STRUCTURE:
770 if (sscreen->info.vcn_ip_version >= VCN_2_0_0) {
771 int value = (PIPE_VIDEO_CAP_SLICE_STRUCTURE_ARBITRARY_MACROBLOCKS |
772 PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_ROWS |
773 PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_MULTI_ROWS);
774 return value;
775 } else
776 return 0;
777
778 case PIPE_VIDEO_CAP_ENC_AV1_FEATURE:
779 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
780 union pipe_av1_enc_cap_features attrib;
781 attrib.value = 0;
782
783 attrib.bits.support_128x128_superblock = PIPE_ENC_FEATURE_NOT_SUPPORTED;
784 attrib.bits.support_filter_intra = PIPE_ENC_FEATURE_NOT_SUPPORTED;
785 attrib.bits.support_intra_edge_filter = PIPE_ENC_FEATURE_NOT_SUPPORTED;
786 attrib.bits.support_interintra_compound = PIPE_ENC_FEATURE_NOT_SUPPORTED;
787 attrib.bits.support_masked_compound = PIPE_ENC_FEATURE_NOT_SUPPORTED;
788 attrib.bits.support_warped_motion = PIPE_ENC_FEATURE_NOT_SUPPORTED;
789 attrib.bits.support_palette_mode = PIPE_ENC_FEATURE_SUPPORTED;
790 attrib.bits.support_dual_filter = PIPE_ENC_FEATURE_NOT_SUPPORTED;
791 attrib.bits.support_jnt_comp = PIPE_ENC_FEATURE_NOT_SUPPORTED;
792 attrib.bits.support_ref_frame_mvs = PIPE_ENC_FEATURE_NOT_SUPPORTED;
793 attrib.bits.support_superres = PIPE_ENC_FEATURE_NOT_SUPPORTED;
794 attrib.bits.support_restoration = PIPE_ENC_FEATURE_NOT_SUPPORTED;
795 attrib.bits.support_allow_intrabc = PIPE_ENC_FEATURE_NOT_SUPPORTED;
796 attrib.bits.support_cdef_channel_strength = PIPE_ENC_FEATURE_SUPPORTED;
797
798 return attrib.value;
799 } else
800 return 0;
801
802 case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT1:
803 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
804 union pipe_av1_enc_cap_features_ext1 attrib_ext1;
805 attrib_ext1.value = 0;
806 attrib_ext1.bits.interpolation_filter = PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP |
807 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP_SMOOTH |
808 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP_SHARP |
809 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_BILINEAR |
810 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_SWITCHABLE;
811 attrib_ext1.bits.min_segid_block_size_accepted = 0;
812 attrib_ext1.bits.segment_feature_support = 0;
813
814 return attrib_ext1.value;
815 } else
816 return 0;
817
818 case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT2:
819 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
820 union pipe_av1_enc_cap_features_ext2 attrib_ext2;
821 attrib_ext2.value = 0;
822
823 attrib_ext2.bits.tile_size_bytes_minus1 = 3;
824 attrib_ext2.bits.obu_size_bytes_minus1 = 1;
825 /**
826 * tx_mode supported.
827 * (tx_mode_support & 0x01) == 1: ONLY_4X4 is supported, 0: not.
828 * (tx_mode_support & 0x02) == 1: TX_MODE_LARGEST is supported, 0: not.
829 * (tx_mode_support & 0x04) == 1: TX_MODE_SELECT is supported, 0: not.
830 */
831 attrib_ext2.bits.tx_mode_support = PIPE_VIDEO_CAP_ENC_AV1_TX_MODE_SELECT;
832 attrib_ext2.bits.max_tile_num_minus1 = 31;
833
834 return attrib_ext2.value;
835 } else
836 return 0;
837 case PIPE_VIDEO_CAP_ENC_SUPPORTS_TILE:
838 if ((sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) &&
839 profile == PIPE_VIDEO_PROFILE_AV1_MAIN)
840 return 1;
841 else
842 return 0;
843
844 case PIPE_VIDEO_CAP_ENC_MAX_REFERENCES_PER_FRAME:
845 if (sscreen->info.vcn_ip_version >= VCN_3_0_0) {
846 int refPicList0 = 1;
847 int refPicList1 = codec == PIPE_VIDEO_FORMAT_MPEG4_AVC ? 1 : 0;
848 return refPicList0 | (refPicList1 << 16);
849 } else
850 return 1;
851
852 case PIPE_VIDEO_CAP_ENC_INTRA_REFRESH:
853 if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
854 int value = PIPE_VIDEO_ENC_INTRA_REFRESH_ROW |
855 PIPE_VIDEO_ENC_INTRA_REFRESH_COLUMN |
856 PIPE_VIDEO_ENC_INTRA_REFRESH_P_FRAME;
857 return value;
858 }
859 else
860 return 0;
861
862 case PIPE_VIDEO_CAP_ENC_ROI:
863 if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
864 union pipe_enc_cap_roi attrib;
865 attrib.value = 0;
866
867 attrib.bits.num_roi_regions = PIPE_ENC_ROI_REGION_NUM_MAX;
868 attrib.bits.roi_rc_priority_support = PIPE_ENC_FEATURE_NOT_SUPPORTED;
869 attrib.bits.roi_rc_qp_delta_support = PIPE_ENC_FEATURE_SUPPORTED;
870 return attrib.value;
871 }
872 else
873 return 0;
874 case PIPE_VIDEO_CAP_ENC_SURFACE_ALIGNMENT:
875 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
876 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
877 union pipe_enc_cap_surface_alignment attrib;
878 attrib.value = 0;
879
880 attrib.bits.log2_width_alignment = RADEON_ENC_HEVC_SURFACE_LOG2_WIDTH_ALIGNMENT;
881 attrib.bits.log2_height_alignment = RADEON_ENC_HEVC_SURFACE_LOG2_HEIGHT_ALIGNMENT;
882 return attrib.value;
883 }
884 else
885 return 0;
886
887 case PIPE_VIDEO_CAP_ENC_RATE_CONTROL_QVBR:
888 if (sscreen->info.vcn_ip_version >= VCN_3_0_0 &&
889 sscreen->info.vcn_ip_version < VCN_4_0_0)
890 return sscreen->info.vcn_enc_minor_version >= 30;
891
892 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 &&
893 sscreen->info.vcn_ip_version < VCN_5_0_0)
894 return sscreen->info.vcn_enc_minor_version >= 15;
895
896 if (sscreen->info.vcn_ip_version >= VCN_5_0_0)
897 return sscreen->info.vcn_enc_minor_version >= 3;
898
899 return 0;
900
901 default:
902 return 0;
903 }
904 }
905
906 switch (param) {
907 case PIPE_VIDEO_CAP_SUPPORTED:
908 if (codec != PIPE_VIDEO_FORMAT_JPEG &&
909 !(sscreen->info.ip[AMD_IP_UVD].num_queues ||
910 ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
911 sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues :
912 sscreen->info.ip[AMD_IP_VCN_DEC].num_queues)))
913 return false;
914 if (QUERYABLE_KERNEL && fully_supported_profile &&
915 sscreen->info.vcn_ip_version >= VCN_1_0_0)
916 return KERNEL_DEC_CAP(codec, valid);
917 if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
918 sscreen->info.vcn_ip_version >= VCN_3_0_33)
919 return false;
920
921 switch (codec) {
922 case PIPE_VIDEO_FORMAT_MPEG12:
923 return !(sscreen->info.vcn_ip_version >= VCN_3_0_33 || profile == PIPE_VIDEO_PROFILE_MPEG1);
924 case PIPE_VIDEO_FORMAT_MPEG4:
925 return !(sscreen->info.vcn_ip_version >= VCN_3_0_33);
926 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
927 if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
928 sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
929 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
930 return false;
931 }
932 return (profile != PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10);
933 case PIPE_VIDEO_FORMAT_VC1:
934 return !(sscreen->info.vcn_ip_version >= VCN_3_0_33);
935 case PIPE_VIDEO_FORMAT_HEVC:
936 /* Carrizo only supports HEVC Main */
937 if (sscreen->info.family >= CHIP_STONEY)
938 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
939 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
940 else if (sscreen->info.family >= CHIP_CARRIZO)
941 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
942 return false;
943 case PIPE_VIDEO_FORMAT_JPEG:
944 if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
945 if (!sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues)
946 return false;
947 else
948 return true;
949 }
950 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
951 return false;
952 if (!sscreen->info.is_amdgpu) {
953 RVID_ERR("No MJPEG support for the kernel version\n");
954 return false;
955 }
956 return true;
957 case PIPE_VIDEO_FORMAT_VP9:
958 return sscreen->info.vcn_ip_version >= VCN_1_0_0;
959 case PIPE_VIDEO_FORMAT_AV1:
960 return sscreen->info.vcn_ip_version >= VCN_3_0_0 && sscreen->info.vcn_ip_version != VCN_3_0_33;
961 default:
962 return false;
963 }
964 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
965 return 1;
966 case PIPE_VIDEO_CAP_MIN_WIDTH:
967 case PIPE_VIDEO_CAP_MIN_HEIGHT:
968 return (codec == PIPE_VIDEO_FORMAT_AV1) ? 16 : 64;
969 case PIPE_VIDEO_CAP_MAX_WIDTH:
970 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
971 return KERNEL_DEC_CAP(codec, max_width);
972 else {
973 switch (codec) {
974 case PIPE_VIDEO_FORMAT_HEVC:
975 case PIPE_VIDEO_FORMAT_VP9:
976 case PIPE_VIDEO_FORMAT_AV1:
977 return (sscreen->info.vcn_ip_version < VCN_2_0_0) ?
978 ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192;
979 default:
980 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
981 }
982 }
983 case PIPE_VIDEO_CAP_MAX_HEIGHT:
984 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
985 return KERNEL_DEC_CAP(codec, max_height);
986 else {
987 switch (codec) {
988 case PIPE_VIDEO_FORMAT_HEVC:
989 case PIPE_VIDEO_FORMAT_VP9:
990 case PIPE_VIDEO_FORMAT_AV1:
991 return (sscreen->info.vcn_ip_version < VCN_2_0_0) ?
992 ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352;
993 default:
994 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
995 }
996 }
997 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
998 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
999 return PIPE_FORMAT_P010;
1000 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1001 return PIPE_FORMAT_P010;
1002 else
1003 return PIPE_FORMAT_NV12;
1004
1005 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1006 return false;
1007 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
1008 enum pipe_video_format format = u_reduce_video_profile(profile);
1009
1010 if (format >= PIPE_VIDEO_FORMAT_HEVC)
1011 return false;
1012
1013 return true;
1014 }
1015 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1016 return true;
1017 case PIPE_VIDEO_CAP_MAX_LEVEL:
1018 if ((profile == PIPE_VIDEO_PROFILE_MPEG2_SIMPLE ||
1019 profile == PIPE_VIDEO_PROFILE_MPEG2_MAIN ||
1020 profile == PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE ||
1021 profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) &&
1022 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
1023 return sscreen->info.dec_caps.codec_info[codec - 1].max_level;
1024 } else {
1025 switch (profile) {
1026 case PIPE_VIDEO_PROFILE_MPEG1:
1027 return 0;
1028 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
1029 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
1030 return 3;
1031 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
1032 return 3;
1033 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
1034 return 5;
1035 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
1036 return 1;
1037 case PIPE_VIDEO_PROFILE_VC1_MAIN:
1038 return 2;
1039 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
1040 return 4;
1041 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
1042 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
1043 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
1044 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
1045 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
1046 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
1047 return 186;
1048 default:
1049 return 0;
1050 }
1051 }
1052 case PIPE_VIDEO_CAP_SUPPORTS_CONTIGUOUS_PLANES_MAP:
1053 return true;
1054 case PIPE_VIDEO_CAP_ROI_CROP_DEC:
1055 if (codec == PIPE_VIDEO_FORMAT_JPEG &&
1056 sscreen->info.vcn_ip_version == VCN_4_0_3)
1057 return true;
1058 return false;
1059 default:
1060 return 0;
1061 }
1062 }
1063
si_vid_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)1064 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
1065 enum pipe_video_profile profile,
1066 enum pipe_video_entrypoint entrypoint)
1067 {
1068 struct si_screen *sscreen = (struct si_screen *)screen;
1069
1070 if (sscreen->info.ip[AMD_IP_VPE].num_queues && entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
1071 /* Todo:
1072 * Unable to confirm whether it is asking for an input or output type
1073 * Have to modify va frontend for solving this problem
1074 */
1075 /* VPE Supported input type */
1076 if ((format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_NV21) || (format == PIPE_FORMAT_P010))
1077 return true;
1078
1079 /* VPE Supported output type */
1080 if ((format == PIPE_FORMAT_A8R8G8B8_UNORM) || (format == PIPE_FORMAT_A8B8G8R8_UNORM) || (format == PIPE_FORMAT_R8G8B8A8_UNORM) ||
1081 (format == PIPE_FORMAT_B8G8R8A8_UNORM) || (format == PIPE_FORMAT_X8R8G8B8_UNORM) || (format == PIPE_FORMAT_X8B8G8R8_UNORM) ||
1082 (format == PIPE_FORMAT_R8G8B8X8_UNORM) || (format == PIPE_FORMAT_B8G8R8X8_UNORM) || (format == PIPE_FORMAT_A2R10G10B10_UNORM) ||
1083 (format == PIPE_FORMAT_A2B10G10R10_UNORM) || (format == PIPE_FORMAT_B10G10R10A2_UNORM) || (format == PIPE_FORMAT_R10G10B10A2_UNORM))
1084 return true;
1085 }
1086
1087 /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
1088 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1089 return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
1090 (format == PIPE_FORMAT_P016);
1091
1092 /* Vp9 profile 2 supports 10 bit decoding using P016 */
1093 if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1094 return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
1095
1096 if (profile == PIPE_VIDEO_PROFILE_AV1_MAIN && entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1097 return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016) ||
1098 (format == PIPE_FORMAT_NV12);
1099
1100 /* JPEG supports YUV400 and YUV444 */
1101 if (profile == PIPE_VIDEO_PROFILE_JPEG_BASELINE) {
1102 switch (format) {
1103 case PIPE_FORMAT_NV12:
1104 case PIPE_FORMAT_YUYV:
1105 case PIPE_FORMAT_L8_UNORM:
1106 case PIPE_FORMAT_Y8_400_UNORM:
1107 return true;
1108 case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
1109 case PIPE_FORMAT_Y8_U8_V8_440_UNORM:
1110 if (sscreen->info.vcn_ip_version >= VCN_2_0_0)
1111 return true;
1112 else
1113 return false;
1114 case PIPE_FORMAT_R8G8B8A8_UNORM:
1115 case PIPE_FORMAT_A8R8G8B8_UNORM:
1116 case PIPE_FORMAT_R8_G8_B8_UNORM:
1117 if (sscreen->info.vcn_ip_version == VCN_4_0_3)
1118 return true;
1119 else
1120 return false;
1121 default:
1122 return false;
1123 }
1124 }
1125
1126 if ((entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) &&
1127 (((profile == PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH) &&
1128 (sscreen->info.vcn_ip_version >= VCN_2_0_0)) ||
1129 ((profile == PIPE_VIDEO_PROFILE_AV1_MAIN) &&
1130 (sscreen->info.vcn_ip_version >= VCN_4_0_0 &&
1131 sscreen->info.vcn_ip_version != VCN_4_0_3))))
1132 return (format == PIPE_FORMAT_P010 || format == PIPE_FORMAT_NV12);
1133
1134
1135 /* we can only handle this one with UVD */
1136 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
1137 return format == PIPE_FORMAT_NV12;
1138
1139 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
1140 }
1141
si_vid_is_target_buffer_supported(struct pipe_screen * screen,enum pipe_format format,struct pipe_video_buffer * target,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)1142 static bool si_vid_is_target_buffer_supported(struct pipe_screen *screen,
1143 enum pipe_format format,
1144 struct pipe_video_buffer *target,
1145 enum pipe_video_profile profile,
1146 enum pipe_video_entrypoint entrypoint)
1147 {
1148 struct si_screen *sscreen = (struct si_screen *)screen;
1149 struct si_texture *tex = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
1150 const bool is_dcc = tex->surface.meta_offset;
1151 const bool is_format_conversion = format != target->buffer_format;
1152
1153 switch (entrypoint) {
1154 case PIPE_VIDEO_ENTRYPOINT_BITSTREAM:
1155 return !is_dcc && !is_format_conversion;
1156
1157 case PIPE_VIDEO_ENTRYPOINT_ENCODE:
1158 if (is_dcc)
1159 return false;
1160
1161 /* EFC */
1162 if (is_format_conversion) {
1163 const bool input_8bit =
1164 target->buffer_format == PIPE_FORMAT_B8G8R8A8_UNORM ||
1165 target->buffer_format == PIPE_FORMAT_B8G8R8X8_UNORM ||
1166 target->buffer_format == PIPE_FORMAT_R8G8B8A8_UNORM ||
1167 target->buffer_format == PIPE_FORMAT_R8G8B8X8_UNORM;
1168 const bool input_10bit =
1169 target->buffer_format == PIPE_FORMAT_B10G10R10A2_UNORM ||
1170 target->buffer_format == PIPE_FORMAT_B10G10R10X2_UNORM ||
1171 target->buffer_format == PIPE_FORMAT_R10G10B10A2_UNORM ||
1172 target->buffer_format == PIPE_FORMAT_R10G10B10X2_UNORM;
1173
1174 if (sscreen->info.vcn_ip_version < VCN_2_0_0 ||
1175 sscreen->info.vcn_ip_version == VCN_2_2_0 ||
1176 sscreen->info.vcn_ip_version >= VCN_5_0_0 ||
1177 sscreen->debug_flags & DBG(NO_EFC))
1178 return false;
1179
1180 if (input_8bit)
1181 return format == PIPE_FORMAT_NV12;
1182 else if (input_10bit)
1183 return format == PIPE_FORMAT_NV12 || format == PIPE_FORMAT_P010;
1184 else
1185 return false;
1186 }
1187
1188 return true;
1189
1190 default:
1191 return !is_format_conversion;
1192 }
1193 }
1194
get_max_threads_per_block(struct si_screen * screen,enum pipe_shader_ir ir_type)1195 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
1196 {
1197 if (ir_type == PIPE_SHADER_IR_NATIVE)
1198 return 256;
1199
1200 /* LLVM only supports 1024 threads per block. */
1201 return 1024;
1202 }
1203
si_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)1204 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
1205 enum pipe_compute_cap param, void *ret)
1206 {
1207 struct si_screen *sscreen = (struct si_screen *)screen;
1208
1209 // TODO: select these params by asic
1210 switch (param) {
1211 case PIPE_COMPUTE_CAP_IR_TARGET: {
1212 const char *gpu, *triple;
1213
1214 triple = "amdgcn-mesa-mesa3d";
1215 gpu = ac_get_llvm_processor_name(sscreen->info.family);
1216 if (ret) {
1217 sprintf(ret, "%s-%s", gpu, triple);
1218 }
1219 /* +2 for dash and terminating NIL byte */
1220 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1221 }
1222 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1223 if (ret) {
1224 uint64_t *grid_dimension = ret;
1225 grid_dimension[0] = 3;
1226 }
1227 return 1 * sizeof(uint64_t);
1228
1229 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1230 if (ret) {
1231 uint64_t *grid_size = ret;
1232 /* Use this size, so that internal counters don't overflow 64 bits. */
1233 grid_size[0] = UINT32_MAX;
1234 grid_size[1] = UINT16_MAX;
1235 grid_size[2] = UINT16_MAX;
1236 }
1237 return 3 * sizeof(uint64_t);
1238
1239 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1240 if (ret) {
1241 uint64_t *block_size = ret;
1242 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
1243 block_size[0] = threads_per_block;
1244 block_size[1] = threads_per_block;
1245 block_size[2] = threads_per_block;
1246 }
1247 return 3 * sizeof(uint64_t);
1248
1249 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1250 if (ret) {
1251 uint64_t *max_threads_per_block = ret;
1252 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
1253 }
1254 return sizeof(uint64_t);
1255 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1256 if (ret) {
1257 uint32_t *address_bits = ret;
1258 address_bits[0] = 64;
1259 }
1260 return 1 * sizeof(uint32_t);
1261
1262 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1263 if (ret) {
1264 uint64_t *max_global_size = ret;
1265 uint64_t max_mem_alloc_size;
1266
1267 si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1268 &max_mem_alloc_size);
1269
1270 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1271 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1272 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1273 * make sure we never report more than
1274 * 4 * MAX_MEM_ALLOC_SIZE.
1275 */
1276 *max_global_size =
1277 MIN2(4 * max_mem_alloc_size, sscreen->info.max_heap_size_kb * 1024ull);
1278 }
1279 return sizeof(uint64_t);
1280
1281 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1282 if (ret) {
1283 uint64_t *max_local_size = ret;
1284 /* Value reported by the closed source driver. */
1285 if (sscreen->info.gfx_level == GFX6)
1286 *max_local_size = 32 * 1024;
1287 else
1288 *max_local_size = 64 * 1024;
1289 }
1290 return sizeof(uint64_t);
1291
1292 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1293 if (ret) {
1294 uint64_t *max_input_size = ret;
1295 /* Value reported by the closed source driver. */
1296 *max_input_size = 1024;
1297 }
1298 return sizeof(uint64_t);
1299
1300 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1301 if (ret) {
1302 uint64_t *max_mem_alloc_size = ret;
1303
1304 /* Return 1/4 of the heap size as the maximum because the max size is not practically
1305 * allocatable.
1306 */
1307 *max_mem_alloc_size = (sscreen->info.max_heap_size_kb / 4) * 1024ull;
1308 }
1309 return sizeof(uint64_t);
1310
1311 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1312 if (ret) {
1313 uint32_t *max_clock_frequency = ret;
1314 *max_clock_frequency = sscreen->info.max_gpu_freq_mhz;
1315 }
1316 return sizeof(uint32_t);
1317
1318 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1319 if (ret) {
1320 uint32_t *max_compute_units = ret;
1321 *max_compute_units = sscreen->info.num_cu;
1322 }
1323 return sizeof(uint32_t);
1324
1325 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1326 if (ret) {
1327 uint32_t *images_supported = ret;
1328 *images_supported = 0;
1329 }
1330 return sizeof(uint32_t);
1331 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1332 break; /* unused */
1333 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS: {
1334 if (ret) {
1335 uint32_t *max_subgroups = ret;
1336 unsigned threads = get_max_threads_per_block(sscreen, ir_type);
1337 unsigned subgroup_size;
1338
1339 if (sscreen->debug_flags & DBG(W64_CS) || sscreen->info.gfx_level < GFX10)
1340 subgroup_size = 64;
1341 else
1342 subgroup_size = 32;
1343
1344 *max_subgroups = threads / subgroup_size;
1345 }
1346 return sizeof(uint32_t);
1347 }
1348 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
1349 if (ret) {
1350 uint32_t *subgroup_size = ret;
1351 if (sscreen->debug_flags & DBG(W32_CS))
1352 *subgroup_size = 32;
1353 else if (sscreen->debug_flags & DBG(W64_CS))
1354 *subgroup_size = 64;
1355 else
1356 *subgroup_size = sscreen->info.gfx_level < GFX10 ? 64 : 64 | 32;
1357 }
1358 return sizeof(uint32_t);
1359 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1360 if (ret) {
1361 uint64_t *max_variable_threads_per_block = ret;
1362 if (ir_type == PIPE_SHADER_IR_NATIVE)
1363 *max_variable_threads_per_block = 0;
1364 else
1365 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1366 }
1367 return sizeof(uint64_t);
1368 }
1369
1370 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1371 return 0;
1372 }
1373
si_get_timestamp(struct pipe_screen * screen)1374 static uint64_t si_get_timestamp(struct pipe_screen *screen)
1375 {
1376 struct si_screen *sscreen = (struct si_screen *)screen;
1377
1378 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
1379 sscreen->info.clock_crystal_freq;
1380 }
1381
si_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)1382 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
1383 {
1384 struct si_screen *sscreen = (struct si_screen *)screen;
1385 struct radeon_winsys *ws = sscreen->ws;
1386 unsigned vram_usage, gtt_usage;
1387
1388 info->total_device_memory = sscreen->info.vram_size_kb;
1389 info->total_staging_memory = sscreen->info.gart_size_kb;
1390
1391 /* The real TTM memory usage is somewhat random, because:
1392 *
1393 * 1) TTM delays freeing memory, because it can only free it after
1394 * fences expire.
1395 *
1396 * 2) The memory usage can be really low if big VRAM evictions are
1397 * taking place, but the real usage is well above the size of VRAM.
1398 *
1399 * Instead, return statistics of this process.
1400 */
1401 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
1402 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
1403
1404 info->avail_device_memory =
1405 vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
1406 info->avail_staging_memory =
1407 gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
1408
1409 info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1410
1411 if (sscreen->info.is_amdgpu)
1412 info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
1413 else
1414 /* Just return the number of evicted 64KB pages. */
1415 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1416 }
1417
si_get_disk_shader_cache(struct pipe_screen * pscreen)1418 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
1419 {
1420 struct si_screen *sscreen = (struct si_screen *)pscreen;
1421
1422 return sscreen->disk_shader_cache;
1423 }
1424
si_init_renderer_string(struct si_screen * sscreen)1425 static void si_init_renderer_string(struct si_screen *sscreen)
1426 {
1427 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
1428 struct utsname uname_data;
1429
1430 snprintf(first_name, sizeof(first_name), "%s",
1431 sscreen->info.marketing_name ? sscreen->info.marketing_name : sscreen->info.name);
1432 snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.lowercase_name);
1433
1434 if (uname(&uname_data) == 0)
1435 snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
1436
1437 const char *compiler_name =
1438 #if AMD_LLVM_AVAILABLE
1439 !sscreen->use_aco ? "LLVM " MESA_LLVM_VERSION_STRING :
1440 #endif
1441 "ACO";
1442
1443 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
1444 "%s (radeonsi, %s%s, DRM %i.%i%s)", first_name, second_name, compiler_name,
1445 sscreen->info.drm_major, sscreen->info.drm_minor, kernel_version);
1446 }
1447
si_get_screen_fd(struct pipe_screen * screen)1448 static int si_get_screen_fd(struct pipe_screen *screen)
1449 {
1450 struct si_screen *sscreen = (struct si_screen *)screen;
1451 struct radeon_winsys *ws = sscreen->ws;
1452
1453 return ws->get_fd(ws);
1454 }
1455
si_varying_expression_max_cost(nir_shader * producer,nir_shader * consumer)1456 static unsigned si_varying_expression_max_cost(nir_shader *producer, nir_shader *consumer)
1457 {
1458 unsigned num_profiles = si_get_num_shader_profiles();
1459
1460 for (unsigned i = 0; i < num_profiles; i++) {
1461 if (_mesa_printed_blake3_equal(consumer->info.source_blake3, si_shader_profiles[i].blake3)) {
1462 if (si_shader_profiles[i].options & SI_PROFILE_NO_OPT_UNIFORM_VARYINGS)
1463 return 0; /* only propagate constants */
1464 break;
1465 }
1466 }
1467
1468 return ac_nir_varying_expression_max_cost(producer, consumer);
1469 }
1470
1471
1472 static void
si_driver_thread_add_job(struct pipe_screen * screen,void * data,struct util_queue_fence * fence,pipe_driver_thread_func execute,pipe_driver_thread_func cleanup,const size_t job_size)1473 si_driver_thread_add_job(struct pipe_screen *screen, void *data,
1474 struct util_queue_fence *fence,
1475 pipe_driver_thread_func execute,
1476 pipe_driver_thread_func cleanup,
1477 const size_t job_size)
1478 {
1479 struct si_screen *sscreen = (struct si_screen *)screen;
1480 util_queue_add_job(&sscreen->shader_compiler_queue, data, fence, execute, cleanup, job_size);
1481 }
1482
1483
si_init_screen_get_functions(struct si_screen * sscreen)1484 void si_init_screen_get_functions(struct si_screen *sscreen)
1485 {
1486 sscreen->b.get_name = si_get_name;
1487 sscreen->b.get_vendor = si_get_vendor;
1488 sscreen->b.get_device_vendor = si_get_device_vendor;
1489 sscreen->b.get_screen_fd = si_get_screen_fd;
1490 sscreen->b.get_param = si_get_param;
1491 sscreen->b.is_compute_copy_faster = si_is_compute_copy_faster;
1492 sscreen->b.driver_thread_add_job = si_driver_thread_add_job;
1493 sscreen->b.get_paramf = si_get_paramf;
1494 sscreen->b.get_compute_param = si_get_compute_param;
1495 sscreen->b.get_timestamp = si_get_timestamp;
1496 sscreen->b.get_shader_param = si_get_shader_param;
1497 sscreen->b.get_compiler_options = si_get_compiler_options;
1498 sscreen->b.get_device_uuid = si_get_device_uuid;
1499 sscreen->b.get_driver_uuid = si_get_driver_uuid;
1500 sscreen->b.query_memory_info = si_query_memory_info;
1501 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1502
1503 if (sscreen->info.ip[AMD_IP_UVD].num_queues ||
1504 ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
1505 sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_DEC].num_queues) ||
1506 sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
1507 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues ||
1508 sscreen->info.ip[AMD_IP_VPE].num_queues) {
1509 sscreen->b.get_video_param = si_get_video_param;
1510 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1511 sscreen->b.is_video_target_buffer_supported = si_vid_is_target_buffer_supported;
1512 } else {
1513 sscreen->b.get_video_param = si_get_video_param_no_video_hw;
1514 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1515 }
1516
1517 si_init_renderer_string(sscreen);
1518
1519 /* |---------------------------------- Performance & Availability --------------------------------|
1520 * |MAD/MAC/MADAK/MADMK|MAD_LEGACY|MAC_LEGACY| FMA |FMAC/FMAAK/FMAMK|FMA_LEGACY|PK_FMA_F16,|Best choice
1521 * Arch | F32,F16,F64 | F32,F16 | F32,F16 |F32,F16,F64 | F32,F16 | F32 |PK_FMAC_F16|F16,F32,F64
1522 * ------------------------------------------------------------------------------------------------------------------
1523 * gfx6,7 | 1 , - , - | 1 , - | 1 , - |1/4, - ,1/16| - , - | - | - , - | - ,MAD,FMA
1524 * gfx8 | 1 , 1 , - | 1 , - | - , - |1/4, 1 ,1/16| - , - | - | - , - |MAD,MAD,FMA
1525 * gfx9 | 1 ,1|0, - | 1 , - | - , - | 1 , 1 ,1/16| 0|1, - | - | 2 , - |FMA,MAD,FMA
1526 * gfx10 | 1 , - , - | 1 , - | 1 , - | 1 , 1 ,1/16| 1 , 1 | - | 2 , 2 |FMA,MAD,FMA
1527 * gfx10.3| - , - , - | - , - | - , - | 1 , 1 ,1/16| 1 , 1 | 1 | 2 , 2 | all FMA
1528 * gfx11 | - , - , - | - , - | - , - | 2 , 2 ,1/16| 2 , 2 | 2 | 2 , 2 | all FMA
1529 *
1530 * Tahiti, Hawaii, Carrizo, Vega20: FMA_F32 is full rate, FMA_F64 is 1/4
1531 * gfx9 supports MAD_F16 only on Vega10, Raven, Raven2, Renoir.
1532 * gfx9 supports FMAC_F32 only on Vega20, but doesn't support FMAAK and FMAMK.
1533 *
1534 * gfx8 prefers MAD for F16 because of MAC/MADAK/MADMK.
1535 * gfx9 and newer prefer FMA for F16 because of the packed instruction.
1536 * gfx10 and older prefer MAD for F32 because of the legacy instruction.
1537 */
1538 bool use_fma32 =
1539 sscreen->info.gfx_level >= GFX10_3 ||
1540 (sscreen->info.family >= CHIP_GFX940 && !sscreen->info.has_graphics) ||
1541 /* fma32 is too slow for gpu < gfx9, so apply the option only for gpu >= gfx9 */
1542 (sscreen->info.gfx_level >= GFX9 && sscreen->options.force_use_fma32);
1543 bool has_mediump = sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16;
1544
1545 nir_shader_compiler_options *options = sscreen->nir_options;
1546 ac_set_nir_options(&sscreen->info, !sscreen->use_aco, options);
1547
1548 options->lower_ffma16 = sscreen->info.gfx_level < GFX9;
1549 options->lower_ffma32 = !use_fma32;
1550 options->lower_ffma64 = false;
1551 options->fuse_ffma16 = sscreen->info.gfx_level >= GFX9;
1552 options->fuse_ffma32 = use_fma32;
1553 options->fuse_ffma64 = true;
1554 options->lower_uniforms_to_ubo = true;
1555 options->lower_layer_fs_input_to_sysval = true;
1556 options->optimize_sample_mask_in = true;
1557 options->lower_to_scalar = true;
1558 options->lower_to_scalar_filter =
1559 sscreen->info.has_packed_math_16bit ? si_alu_to_scalar_packed_math_filter : NULL;
1560 options->max_unroll_iterations = 128;
1561 options->max_unroll_iterations_aggressive = 128;
1562 /* For OpenGL, rounding mode is undefined. We want fast packing with v_cvt_pkrtz_f16,
1563 * but if we use it, all f32->f16 conversions have to round towards zero,
1564 * because both scalar and vec2 down-conversions have to round equally.
1565 *
1566 * For OpenCL, rounding mode is explicit. This will only lower f2f16 to f2f16_rtz
1567 * when execution mode is rtz instead of rtne.
1568 */
1569 options->force_f2f16_rtz = true;
1570 options->io_options |= (!has_mediump ? nir_io_mediump_is_32bit : 0) |
1571 nir_io_glsl_lower_derefs |
1572 (sscreen->options.optimize_io ? nir_io_glsl_opt_varyings : 0);
1573 options->lower_mediump_io = has_mediump ? si_lower_mediump_io : NULL;
1574 /* HW supports indirect indexing for: | Enabled in driver
1575 * -------------------------------------------------------
1576 * TCS inputs | Yes
1577 * TES inputs | Yes
1578 * GS inputs | No
1579 * -------------------------------------------------------
1580 * VS outputs before TCS | No
1581 * TCS outputs | Yes
1582 * VS/TES outputs before GS | No
1583 */
1584 options->support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
1585 BITFIELD_BIT(MESA_SHADER_TESS_EVAL);
1586 options->support_indirect_outputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL);
1587 options->varying_expression_max_cost = si_varying_expression_max_cost;
1588 options->varying_estimate_instr_cost = ac_nir_varying_estimate_instr_cost;
1589 }
1590