xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * SPDX-License-Identifier: MIT
5  */
6 
7 #include "si_pipe.h"
8 #include "si_shader_internal.h"
9 #include "si_shader_llvm.h"
10 #include "sid.h"
11 
si_nir_load_tcs_varyings(struct ac_shader_abi * abi,LLVMTypeRef type,unsigned driver_location,unsigned component,unsigned num_components)12 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi, LLVMTypeRef type,
13                                              unsigned driver_location, unsigned component,
14                                              unsigned num_components)
15 {
16    struct si_shader_context *ctx = si_shader_context_from_abi(abi);
17    struct si_shader_info *info = &ctx->shader->selector->info;
18 
19    assert(ctx->shader->key.ge.opt.same_patch_vertices);
20 
21    uint8_t semantic = info->input[driver_location].semantic;
22    /* Load the TCS input from a VGPR. */
23    unsigned func_param = ctx->args->ac.tcs_rel_ids.arg_index + 1 +
24       si_shader_io_get_unique_index(semantic) * 4;
25 
26    LLVMValueRef value[4];
27    for (unsigned i = component; i < component + num_components; i++) {
28       value[i] = LLVMGetParam(ctx->main_fn.value, func_param + i);
29       value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
30    }
31 
32    return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
33 }
34 
si_llvm_tcs_build_end(struct si_shader_context * ctx)35 void si_llvm_tcs_build_end(struct si_shader_context *ctx)
36 {
37    if (ctx->screen->info.gfx_level >= GFX9) {
38       ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
39    }
40 }
41 
si_llvm_ls_build_end(struct si_shader_context * ctx)42 void si_llvm_ls_build_end(struct si_shader_context *ctx)
43 {
44    struct si_shader *shader = ctx->shader;
45    bool same_thread_count = shader->key.ge.opt.same_patch_vertices;
46 
47    /* Only need return value when merged shader on part mode or mono mode with same thread count. */
48    if (ctx->screen->info.gfx_level < GFX9 || (shader->is_monolithic && !same_thread_count))
49       return;
50 
51    if (!ctx->shader->is_monolithic)
52       ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
53 
54    LLVMValueRef ret = ctx->return_value;
55 
56    ret = si_insert_input_ptr(ctx, ret, ctx->args->other_const_and_shader_buffers, 0);
57    ret = si_insert_input_ptr(ctx, ret, ctx->args->other_samplers_and_images, 1);
58    ret = si_insert_input_ret(ctx, ret, ctx->args->ac.tess_offchip_offset, 2);
59    ret = si_insert_input_ret(ctx, ret, ctx->args->ac.merged_wave_info, 3);
60    ret = si_insert_input_ret(ctx, ret, ctx->args->ac.tcs_factor_offset, 4);
61    if (ctx->screen->info.gfx_level <= GFX10_3)
62       ret = si_insert_input_ret(ctx, ret, ctx->args->ac.scratch_offset, 5);
63 
64    ret = si_insert_input_ptr(ctx, ret, ctx->args->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS);
65    ret = si_insert_input_ptr(ctx, ret, ctx->args->bindless_samplers_and_images,
66                              8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
67 
68    ret = si_insert_input_ret(ctx, ret, ctx->args->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS);
69 
70    ret = si_insert_input_ret(ctx, ret, ctx->args->tcs_offchip_layout, 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
71    ret = si_insert_input_ret(ctx, ret, ctx->args->tes_offchip_addr, 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR);
72 
73    unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
74    ret = si_insert_input_ret_float(ctx, ret, ctx->args->ac.tcs_patch_id, vgpr++);
75    ret = si_insert_input_ret_float(ctx, ret, ctx->args->ac.tcs_rel_ids, vgpr++);
76 
77    if (same_thread_count) {
78       /* Same thread count is set only when mono mode. */
79       assert(shader->is_monolithic);
80 
81       struct si_shader_info *info = &shader->selector->info;
82       LLVMValueRef *addrs = ctx->abi.outputs;
83 
84       for (unsigned i = 0; i < info->num_outputs; i++) {
85          unsigned semantic = info->output_semantic[i];
86          int param = si_shader_io_get_unique_index(semantic);
87 
88          if (!(info->outputs_written_before_tes_gs & BITFIELD64_BIT(param)))
89             continue;
90 
91          for (unsigned chan = 0; chan < 4; chan++) {
92             if (!(info->output_usagemask[i] & (1 << chan)))
93                continue;
94 
95             LLVMValueRef value = LLVMBuildLoad2(ctx->ac.builder, ctx->ac.f32, addrs[4 * i + chan], "");
96 
97             ret = LLVMBuildInsertValue(ctx->ac.builder, ret, value, vgpr + param * 4 + chan, "");
98          }
99       }
100    }
101 
102    ctx->return_value = ret;
103 }
104 
si_llvm_init_tcs_callbacks(struct si_shader_context * ctx)105 void si_llvm_init_tcs_callbacks(struct si_shader_context *ctx)
106 {
107    ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
108 }
109