1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "drm-uapi/drm_fourcc.h"
10 #include "radeon_uvd.h"
11 #include "radeon_uvd_enc.h"
12 #include "radeon_vce.h"
13 #include "radeon_vcn_dec.h"
14 #include "radeon_vcn_enc.h"
15 #include "radeon_video.h"
16 #include "si_pipe.h"
17 #include "si_vpe.h"
18 #include "util/u_video.h"
19
20 /**
21 * creates an video buffer with an UVD compatible memory layout
22 */
si_video_buffer_create(struct pipe_context * pipe,const struct pipe_video_buffer * tmpl)23 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
24 const struct pipe_video_buffer *tmpl)
25 {
26 struct pipe_video_buffer vidbuf = *tmpl;
27 uint64_t *modifiers = NULL;
28 int modifiers_count = 0;
29 uint64_t mod = DRM_FORMAT_MOD_LINEAR;
30
31 /* To get tiled buffers, users need to explicitly provide a list of
32 * modifiers. */
33 vidbuf.bind |= PIPE_BIND_LINEAR;
34
35 if (pipe->screen->resource_create_with_modifiers) {
36 modifiers = &mod;
37 modifiers_count = 1;
38 }
39
40 return vl_video_buffer_create_as_resource(pipe, &vidbuf, modifiers,
41 modifiers_count);
42 }
43
si_video_buffer_create_with_modifiers(struct pipe_context * pipe,const struct pipe_video_buffer * tmpl,const uint64_t * modifiers,unsigned int modifiers_count)44 struct pipe_video_buffer *si_video_buffer_create_with_modifiers(struct pipe_context *pipe,
45 const struct pipe_video_buffer *tmpl,
46 const uint64_t *modifiers,
47 unsigned int modifiers_count)
48 {
49 uint64_t *allowed_modifiers;
50 unsigned int allowed_modifiers_count, i;
51
52 /* Filter out DCC modifiers, because we don't support them for video
53 * for now. */
54 allowed_modifiers = calloc(modifiers_count, sizeof(uint64_t));
55 if (!allowed_modifiers)
56 return NULL;
57
58 allowed_modifiers_count = 0;
59 for (i = 0; i < modifiers_count; i++) {
60 if (ac_modifier_has_dcc(modifiers[i]))
61 continue;
62 allowed_modifiers[allowed_modifiers_count++] = modifiers[i];
63 }
64
65 struct pipe_video_buffer *buf =
66 vl_video_buffer_create_as_resource(pipe, tmpl, allowed_modifiers, allowed_modifiers_count);
67 free(allowed_modifiers);
68 return buf;
69 }
70
71 /* set the decoding target buffer offsets */
si_uvd_set_dtb(struct ruvd_msg * msg,struct vl_video_buffer * buf)72 static struct pb_buffer_lean *si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
73 {
74 struct si_screen *sscreen = (struct si_screen *)buf->base.context->screen;
75 struct si_texture *luma = (struct si_texture *)buf->resources[0];
76 struct si_texture *chroma = (struct si_texture *)buf->resources[1];
77 enum ruvd_surface_type type =
78 (sscreen->info.gfx_level >= GFX9) ? RUVD_SURFACE_TYPE_GFX9 : RUVD_SURFACE_TYPE_LEGACY;
79
80 msg->body.decode.dt_field_mode = buf->base.interlaced;
81
82 si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
83
84 return luma->buffer.buf;
85 }
86
87 /* get the radeon resources for VCE */
si_vce_get_buffer(struct pipe_resource * resource,struct pb_buffer_lean ** handle,struct radeon_surf ** surface)88 static void si_vce_get_buffer(struct pipe_resource *resource, struct pb_buffer_lean **handle,
89 struct radeon_surf **surface)
90 {
91 struct si_texture *res = (struct si_texture *)resource;
92
93 if (handle)
94 *handle = res->buffer.buf;
95
96 if (surface)
97 *surface = &res->surface;
98 }
99
100 /**
101 * creates an UVD compatible decoder
102 */
si_uvd_create_decoder(struct pipe_context * context,const struct pipe_video_codec * templ)103 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
104 const struct pipe_video_codec *templ)
105 {
106 struct si_context *ctx = (struct si_context *)context;
107 bool vcn = ctx->vcn_ip_ver >= VCN_1_0_0;
108
109 if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
110 if (vcn) {
111 return radeon_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
112 } else {
113 if (u_reduce_video_profile(templ->profile) == PIPE_VIDEO_FORMAT_HEVC)
114 return radeon_uvd_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
115 else
116 return si_vce_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
117 }
118 } else if (((struct si_screen *)(context->screen))->info.ip[AMD_IP_VPE].num_queues &&
119 templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING)
120 return si_vpe_create_processor(context, templ);
121
122 if (ctx->vcn_ip_ver == VCN_4_0_0)
123 ctx->vcn_has_ctx = true;
124
125 return (vcn) ? radeon_create_decoder(context, templ)
126 : si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
127 }
128