xref: /aosp_15_r20/external/coreboot/src/soc/ti/am335x/pinmux.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include "pinmux.h"
4 
5 #include <device/mmio.h>
6 
7 static struct am335x_pinmux_regs *regs =
8 	(struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR;
9 
am335x_pinmux_uart0(void)10 void am335x_pinmux_uart0(void)
11 {
12 	write32(&regs->uart0_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
13 	write32(&regs->uart0_txd, MODE(0) | PULLUDEN);
14 }
15 
am335x_pinmux_uart1(void)16 void am335x_pinmux_uart1(void)
17 {
18 	write32(&regs->uart1_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
19 	write32(&regs->uart1_txd, MODE(0) | PULLUDEN);
20 }
21 
am335x_pinmux_uart2(void)22 void am335x_pinmux_uart2(void)
23 {
24 	// UART2_RXD
25 	write32(&regs->spi0_sclk, MODE(1) | PULLUP_EN | RXACTIVE);
26 	// UART2_TXD
27 	write32(&regs->spi0_d0, MODE(1) | PULLUDEN);
28 }
29 
am335x_pinmux_uart3(void)30 void am335x_pinmux_uart3(void)
31 {
32 	// UART3_RXD
33 	write32(&regs->spi0_cs1, MODE(1) | PULLUP_EN | RXACTIVE);
34 	// UART3_TXD
35 	write32(&regs->ecap0_in_pwm0_out, MODE(1) | PULLUDEN);
36 }
37 
am335x_pinmux_uart4(void)38 void am335x_pinmux_uart4(void)
39 {
40 	// UART4_RXD
41 	write32(&regs->gpmc_wait0, MODE(6) | PULLUP_EN | RXACTIVE);
42 	// UART4_TXD
43 	write32(&regs->gpmc_wpn, MODE(6) | PULLUDEN);
44 }
45 
am335x_pinmux_uart5(void)46 void am335x_pinmux_uart5(void)
47 {
48 	// UART5_RXD
49 	write32(&regs->lcd_data9, MODE(4) | PULLUP_EN | RXACTIVE);
50 	// UART5_TXD
51 	write32(&regs->lcd_data8, MODE(4) | PULLUDEN);
52 }
53 
am335x_pinmux_mmc0(int cd,int sk_evm)54 void am335x_pinmux_mmc0(int cd, int sk_evm)
55 {
56 	write32(&regs->mmc0_dat0, MODE(0) | RXACTIVE | PULLUP_EN);
57 	write32(&regs->mmc0_dat1, MODE(0) | RXACTIVE | PULLUP_EN);
58 	write32(&regs->mmc0_dat2, MODE(0) | RXACTIVE | PULLUP_EN);
59 	write32(&regs->mmc0_dat3, MODE(0) | RXACTIVE | PULLUP_EN);
60 	write32(&regs->mmc0_clk, MODE(0) | RXACTIVE | PULLUP_EN);
61 	write32(&regs->mmc0_cmd, MODE(0) | RXACTIVE | PULLUP_EN);
62 	if (!sk_evm) {
63 		// MMC0_WP
64 		write32(&regs->mcasp0_aclkr, MODE(4) | RXACTIVE);
65 	}
66 	if (cd) {
67 		// MMC0_CD
68 		write32(&regs->spi0_cs1, MODE(5) | RXACTIVE | PULLUP_EN);
69 	}
70 }
71 
am335x_pinmux_mmc1(void)72 void am335x_pinmux_mmc1(void)
73 {
74 	// MMC1_DAT0
75 	write32(&regs->gpmc_ad0, MODE(1) | RXACTIVE | PULLUP_EN);
76 	// MMC1_DAT1
77 	write32(&regs->gpmc_ad1, MODE(1) | RXACTIVE | PULLUP_EN);
78 	// MMC1_DAT2
79 	write32(&regs->gpmc_ad2, MODE(1) | RXACTIVE | PULLUP_EN);
80 	// MMC1_DAT3
81 	write32(&regs->gpmc_ad3, MODE(1) | RXACTIVE | PULLUP_EN);
82 	// MMC1_CLK
83 	write32(&regs->gpmc_csn1, MODE(2) | RXACTIVE | PULLUP_EN);
84 	// MMC1_CMD
85 	write32(&regs->gpmc_csn2, MODE(2) | RXACTIVE | PULLUP_EN);
86 	// MMC1_WP
87 	write32(&regs->gpmc_csn0, MODE(7) | RXACTIVE | PULLUP_EN);
88 	// MMC1_CD
89 	write32(&regs->gpmc_advn_ale, MODE(7) | RXACTIVE | PULLUP_EN);
90 }
91 
am335x_pinmux_i2c0(void)92 void am335x_pinmux_i2c0(void)
93 {
94 	write32(&regs->i2c0_sda, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
95 	write32(&regs->i2c0_scl, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
96 }
97 
am335x_pinmux_i2c1(void)98 void am335x_pinmux_i2c1(void)
99 {
100 	// I2C_DATA
101 	write32(&regs->spi0_d1, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
102 	// I2C_SCLK
103 	write32(&regs->spi0_cs0, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
104 }
105 
am335x_pinmux_spi0(void)106 void am335x_pinmux_spi0(void)
107 {
108 	write32(&regs->spi0_sclk, MODE(0) | RXACTIVE | PULLUDEN);
109 	write32(&regs->spi0_d0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
110 	write32(&regs->spi0_d1, MODE(0) | RXACTIVE | PULLUDEN);
111 	write32(&regs->spi0_cs0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
112 }
113 
am335x_pinmux_gpio0_7(void)114 void am335x_pinmux_gpio0_7(void)
115 {
116 	write32(&regs->ecap0_in_pwm0_out, MODE(7) | PULLUDEN);
117 }
118 
am335x_pinmux_rgmii1(void)119 void am335x_pinmux_rgmii1(void)
120 {
121 	write32(&regs->mii1_txen, MODE(2));
122 	write32(&regs->mii1_rxdv, MODE(2) | RXACTIVE);
123 	write32(&regs->mii1_txd0, MODE(2));
124 	write32(&regs->mii1_txd1, MODE(2));
125 	write32(&regs->mii1_txd2, MODE(2));
126 	write32(&regs->mii1_txd3, MODE(2));
127 	write32(&regs->mii1_txclk, MODE(2));
128 	write32(&regs->mii1_rxclk, MODE(2) | RXACTIVE);
129 	write32(&regs->mii1_rxd0, MODE(2) | RXACTIVE);
130 	write32(&regs->mii1_rxd1, MODE(2) | RXACTIVE);
131 	write32(&regs->mii1_rxd2, MODE(2) | RXACTIVE);
132 	write32(&regs->mii1_rxd3, MODE(2) | RXACTIVE);
133 }
134 
am335x_pinmux_mii1(void)135 void am335x_pinmux_mii1(void)
136 {
137 	write32(&regs->mii1_rxerr, MODE(0) | RXACTIVE);
138 	write32(&regs->mii1_txen, MODE(0));
139 	write32(&regs->mii1_rxdv, MODE(0) | RXACTIVE);
140 	write32(&regs->mii1_txd0, MODE(0));
141 	write32(&regs->mii1_txd1, MODE(0));
142 	write32(&regs->mii1_txd2, MODE(0));
143 	write32(&regs->mii1_txd3, MODE(0));
144 	write32(&regs->mii1_txclk, MODE(0) | RXACTIVE);
145 	write32(&regs->mii1_rxclk, MODE(0) | RXACTIVE);
146 	write32(&regs->mii1_rxd0, MODE(0) | RXACTIVE);
147 	write32(&regs->mii1_rxd1, MODE(0) | RXACTIVE);
148 	write32(&regs->mii1_rxd2, MODE(0) | RXACTIVE);
149 	write32(&regs->mii1_rxd3, MODE(0) | RXACTIVE);
150 	write32(&regs->mdio_data, MODE(0) | RXACTIVE | PULLUP_EN);
151 	write32(&regs->mdio_clk, MODE(0) | PULLUP_EN);
152 }
153 
am335x_pinmux_nand(void)154 void am335x_pinmux_nand(void)
155 {
156 	write32(&regs->gpmc_ad0, MODE(0) | PULLUP_EN | RXACTIVE);
157 	write32(&regs->gpmc_ad1, MODE(0) | PULLUP_EN | RXACTIVE);
158 	write32(&regs->gpmc_ad2, MODE(0) | PULLUP_EN | RXACTIVE);
159 	write32(&regs->gpmc_ad3, MODE(0) | PULLUP_EN | RXACTIVE);
160 	write32(&regs->gpmc_ad4, MODE(0) | PULLUP_EN | RXACTIVE);
161 	write32(&regs->gpmc_ad5, MODE(0) | PULLUP_EN | RXACTIVE);
162 	write32(&regs->gpmc_ad6, MODE(0) | PULLUP_EN | RXACTIVE);
163 	write32(&regs->gpmc_ad7, MODE(0) | PULLUP_EN | RXACTIVE);
164 	write32(&regs->gpmc_wait0, MODE(0) | RXACTIVE | PULLUP_EN);
165 	write32(&regs->gpmc_wpn, MODE(7) | PULLUP_EN | RXACTIVE);
166 	write32(&regs->gpmc_csn0, MODE(0) | PULLUDEN);
167 	write32(&regs->gpmc_advn_ale, MODE(0) | PULLUDEN);
168 	write32(&regs->gpmc_oen_ren, MODE(0) | PULLUDEN);
169 	write32(&regs->gpmc_wen, MODE(0) | PULLUDEN);
170 	write32(&regs->gpmc_be0n_cle, MODE(0) | PULLUDEN);
171 }
172