1 // SPDX-License-Identifier: GPL-2.0
2
3 /***************************************************************************
4 * copyright : (C) 2002, 2004 by Frank Mori Hess *
5 ***************************************************************************/
6
7 #include "agilent_82350b.h"
8 #include <linux/delay.h>
9 #include <linux/ioport.h>
10 #include <linux/sched.h>
11 #include <linux/module.h>
12 #include <linux/slab.h>
13 #include <asm/dma.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/wait.h>
19
20 MODULE_LICENSE("GPL");
21 MODULE_DESCRIPTION("GPIB driver for Agilent 82350b");
22
agilent_82350b_accel_read(gpib_board_t * board,uint8_t * buffer,size_t length,int * end,size_t * bytes_read)23 int agilent_82350b_accel_read(gpib_board_t *board, uint8_t *buffer, size_t length, int *end,
24 size_t *bytes_read)
25
26 {
27 struct agilent_82350b_priv *a_priv = board->private_data;
28 struct tms9914_priv *tms_priv = &a_priv->tms9914_priv;
29 int retval = 0;
30 unsigned short event_status;
31 int i, num_fifo_bytes;
32 //hardware doesn't support checking for end-of-string character when using fifo
33 if (tms_priv->eos_flags & REOS)
34 return tms9914_read(board, tms_priv, buffer, length, end, bytes_read);
35
36 clear_bit(DEV_CLEAR_BN, &tms_priv->state);
37
38 read_and_clear_event_status(board);
39 *end = 0;
40 *bytes_read = 0;
41 if (length == 0)
42 return 0;
43 //disable fifo for the moment
44 writeb(DIRECTION_GPIB_TO_HOST, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
45 // handle corner case of board not in holdoff and one byte might slip in early
46 if (tms_priv->holdoff_active == 0 && length > 1) {
47 size_t num_bytes;
48
49 retval = tms9914_read(board, tms_priv, buffer, 1, end, &num_bytes);
50 *bytes_read += num_bytes;
51 if (retval < 0)
52 dev_err(board->gpib_dev, "%s: tms9914_read failed retval=%i\n",
53 driver_name, retval);
54 if (retval < 0 || *end)
55 return retval;
56 ++buffer;
57 --length;
58 }
59 tms9914_set_holdoff_mode(tms_priv, TMS9914_HOLDOFF_EOI);
60 tms9914_release_holdoff(tms_priv);
61 i = 0;
62 num_fifo_bytes = length - 1;
63 write_byte(tms_priv, tms_priv->imr0_bits & ~HR_BIIE, IMR0); // disable BI interrupts
64 while (i < num_fifo_bytes && *end == 0) {
65 int block_size;
66 int j;
67 int count;
68
69 if (num_fifo_bytes - i < agilent_82350b_fifo_size)
70 block_size = num_fifo_bytes - i;
71 else
72 block_size = agilent_82350b_fifo_size;
73 set_transfer_counter(a_priv, block_size);
74 writeb(ENABLE_TI_TO_SRAM | DIRECTION_GPIB_TO_HOST,
75 a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
76 if (agilent_82350b_fifo_is_halted(a_priv))
77 writeb(RESTART_STREAM_BIT, a_priv->gpib_base + STREAM_STATUS_REG);
78
79 clear_bit(READ_READY_BN, &tms_priv->state);
80
81 retval = wait_event_interruptible(board->wait,
82 ((event_status =
83 read_and_clear_event_status(board)) &
84 (TERM_COUNT_STATUS_BIT |
85 BUFFER_END_STATUS_BIT)) ||
86 test_bit(DEV_CLEAR_BN, &tms_priv->state) ||
87 test_bit(TIMO_NUM, &board->status));
88 if (retval) {
89 dev_dbg(board->gpib_dev, "%s: read wait interrupted\n", driver_name);
90 retval = -ERESTARTSYS;
91 break;
92 }
93 count = block_size - read_transfer_counter(a_priv);
94 for (j = 0; j < count && i < num_fifo_bytes; ++j)
95 buffer[i++] = readb(a_priv->sram_base + j);
96 if (event_status & BUFFER_END_STATUS_BIT) {
97 clear_bit(RECEIVED_END_BN, &tms_priv->state);
98
99 tms_priv->holdoff_active = 1;
100 *end = 1;
101 }
102 if (test_bit(TIMO_NUM, &board->status)) {
103 dev_err(board->gpib_dev, "%s: read timed out\n", driver_name);
104 retval = -ETIMEDOUT;
105 break;
106 }
107 if (test_bit(DEV_CLEAR_BN, &tms_priv->state)) {
108 dev_err(board->gpib_dev, "%s: device clear interrupted read\n",
109 driver_name);
110 retval = -EINTR;
111 break;
112 }
113 }
114 write_byte(tms_priv, tms_priv->imr0_bits, IMR0); // re-enable BI interrupts
115 *bytes_read += i;
116 buffer += i;
117 length -= i;
118 writeb(DIRECTION_GPIB_TO_HOST, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
119 if (retval < 0)
120 return retval;
121 // read last bytes if we havn't received an END yet
122 if (*end == 0) {
123 size_t num_bytes;
124 // try to make sure we holdoff after last byte read
125 retval = tms9914_read(board, tms_priv, buffer, length, end, &num_bytes);
126 *bytes_read += num_bytes;
127 if (retval < 0)
128 return retval;
129 }
130 return 0;
131 }
132
translate_wait_return_value(gpib_board_t * board,int retval)133 static int translate_wait_return_value(gpib_board_t *board, int retval)
134
135 {
136 struct agilent_82350b_priv *a_priv = board->private_data;
137 struct tms9914_priv *tms_priv = &a_priv->tms9914_priv;
138
139 if (retval) {
140 dev_err(board->gpib_dev, "%s: write wait interrupted\n", driver_name);
141 return -ERESTARTSYS;
142 }
143 if (test_bit(TIMO_NUM, &board->status)) {
144 dev_err(board->gpib_dev, "%s: write timed out\n", driver_name);
145 return -ETIMEDOUT;
146 }
147 if (test_bit(DEV_CLEAR_BN, &tms_priv->state)) {
148 dev_err(board->gpib_dev, "%s: device clear interrupted write\n", driver_name);
149 return -EINTR;
150 }
151 return 0;
152 }
153
agilent_82350b_accel_write(gpib_board_t * board,uint8_t * buffer,size_t length,int send_eoi,size_t * bytes_written)154 int agilent_82350b_accel_write(gpib_board_t *board, uint8_t *buffer, size_t length, int send_eoi,
155 size_t *bytes_written)
156
157 {
158 struct agilent_82350b_priv *a_priv = board->private_data;
159 struct tms9914_priv *tms_priv = &a_priv->tms9914_priv;
160 int i, j;
161 unsigned short event_status;
162 int retval = 0;
163 int fifotransferlength = length;
164 int block_size = 0;
165 size_t num_bytes;
166
167 *bytes_written = 0;
168 if (send_eoi)
169 --fifotransferlength;
170
171 clear_bit(DEV_CLEAR_BN, &tms_priv->state);
172
173 writeb(0, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
174
175 event_status = read_and_clear_event_status(board);
176
177 //pr_info("ag_ac_wr: event status 0x%x tms state 0x%lx\n", event_status, tms_priv->state);
178
179 #ifdef EXPERIMENTAL
180 pr_info("ag_ac_wr: wait for previous BO to complete if any\n");
181 retval = wait_event_interruptible(board->wait,
182 test_bit(DEV_CLEAR_BN, &tms_priv->state) ||
183 test_bit(WRITE_READY_BN, &tms_priv->state) ||
184 test_bit(TIMO_NUM, &board->status));
185 retval = translate_wait_return_value(board, retval);
186
187 if (retval)
188 return retval;
189 #endif
190
191 //pr_info("ag_ac_wr: sending first byte\n");
192 retval = agilent_82350b_write(board, buffer, 1, 0, &num_bytes);
193 *bytes_written += num_bytes;
194 if (retval < 0)
195 return retval;
196
197 //pr_info("ag_ac_wr: %ld bytes eoi %d tms state 0x%lx\n",length, send_eoi, tms_priv->state);
198
199 write_byte(tms_priv, tms_priv->imr0_bits & ~HR_BOIE, IMR0);
200 for (i = 1; i < fifotransferlength;) {
201 clear_bit(WRITE_READY_BN, &tms_priv->state);
202
203 if (fifotransferlength - i < agilent_82350b_fifo_size)
204 block_size = fifotransferlength - i;
205 else
206 block_size = agilent_82350b_fifo_size;
207 set_transfer_counter(a_priv, block_size);
208 for (j = 0; j < block_size; ++j, ++i) {
209 // load data into board's sram
210 writeb(buffer[i], a_priv->sram_base + j);
211 }
212 writeb(ENABLE_TI_TO_SRAM, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
213
214 //pr_info("ag_ac_wr: send block: %d bytes tms 0x%lx\n", block_size,
215 // tms_priv->state);
216
217 if (agilent_82350b_fifo_is_halted(a_priv)) {
218 writeb(RESTART_STREAM_BIT, a_priv->gpib_base + STREAM_STATUS_REG);
219 // pr_info("ag_ac_wr: needed restart\n");
220 }
221
222 retval = wait_event_interruptible(board->wait,
223 ((event_status =
224 read_and_clear_event_status(board)) &
225 TERM_COUNT_STATUS_BIT) ||
226 test_bit(DEV_CLEAR_BN, &tms_priv->state) ||
227 test_bit(TIMO_NUM, &board->status));
228 writeb(0, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
229 num_bytes = block_size - read_transfer_counter(a_priv);
230 //pr_info("ag_ac_wr: sent %ld bytes tms 0x%lx\n", num_bytes, tms_priv->state);
231
232 *bytes_written += num_bytes;
233 retval = translate_wait_return_value(board, retval);
234 if (retval)
235 break;
236 }
237 write_byte(tms_priv, tms_priv->imr0_bits, IMR0);
238 if (retval)
239 return retval;
240
241 if (send_eoi) {
242 //pr_info("ag_ac_wr: sending last byte with eoi byte no: %d\n",
243 // fifotransferlength+1);
244
245 retval = agilent_82350b_write(board, buffer + fifotransferlength, 1, send_eoi,
246 &num_bytes);
247 *bytes_written += num_bytes;
248 if (retval < 0)
249 return retval;
250 }
251 return 0;
252 }
253
read_and_clear_event_status(gpib_board_t * board)254 unsigned short read_and_clear_event_status(gpib_board_t *board)
255
256 {
257 struct agilent_82350b_priv *a_priv = board->private_data;
258 unsigned long flags;
259 unsigned short status;
260
261 spin_lock_irqsave(&board->spinlock, flags);
262 status = a_priv->event_status_bits;
263 a_priv->event_status_bits = 0;
264 spin_unlock_irqrestore(&board->spinlock, flags);
265 return status;
266 }
267
agilent_82350b_interrupt(int irq,void * arg)268 irqreturn_t agilent_82350b_interrupt(int irq, void *arg)
269
270 {
271 int tms9914_status1 = 0, tms9914_status2 = 0;
272 int event_status;
273 gpib_board_t *board = arg;
274 struct agilent_82350b_priv *a_priv = board->private_data;
275 unsigned long flags;
276 irqreturn_t retval = IRQ_NONE;
277
278 spin_lock_irqsave(&board->spinlock, flags);
279 event_status = readb(a_priv->gpib_base + EVENT_STATUS_REG);
280 if (event_status & IRQ_STATUS_BIT)
281 retval = IRQ_HANDLED;
282
283 if (event_status & TMS9914_IRQ_STATUS_BIT) {
284 tms9914_status1 = read_byte(&a_priv->tms9914_priv, ISR0);
285 tms9914_status2 = read_byte(&a_priv->tms9914_priv, ISR1);
286 tms9914_interrupt_have_status(board, &a_priv->tms9914_priv, tms9914_status1,
287 tms9914_status2);
288 }
289 //pr_info("event_status=0x%x s1 %x s2 %x\n", event_status,tms9914_status1,tms9914_status2);
290 //write-clear status bits
291 if (event_status & (BUFFER_END_STATUS_BIT | TERM_COUNT_STATUS_BIT)) {
292 writeb(event_status & (BUFFER_END_STATUS_BIT | TERM_COUNT_STATUS_BIT),
293 a_priv->gpib_base + EVENT_STATUS_REG);
294 a_priv->event_status_bits |= event_status;
295 wake_up_interruptible(&board->wait);
296 }
297 spin_unlock_irqrestore(&board->spinlock, flags);
298 return retval;
299 }
300
301 void agilent_82350b_detach(gpib_board_t *board);
302
303 const char *driver_name = "agilent_82350b";
304
read_transfer_counter(struct agilent_82350b_priv * a_priv)305 int read_transfer_counter(struct agilent_82350b_priv *a_priv)
306
307 {
308 int lo, mid, value;
309
310 lo = readb(a_priv->gpib_base + XFER_COUNT_LO_REG);
311 mid = readb(a_priv->gpib_base + XFER_COUNT_MID_REG);
312 value = (lo & 0xff) | ((mid << 8) & 0x7f00);
313 value = ~(value - 1) & 0x7fff;
314 return value;
315 }
316
set_transfer_counter(struct agilent_82350b_priv * a_priv,int count)317 void set_transfer_counter(struct agilent_82350b_priv *a_priv, int count)
318
319 {
320 int complement = -count;
321
322 writeb(complement & 0xff, a_priv->gpib_base + XFER_COUNT_LO_REG);
323 writeb((complement >> 8) & 0xff, a_priv->gpib_base + XFER_COUNT_MID_REG);
324 //I don't think the hi count reg is even used, but oh well
325 writeb((complement >> 16) & 0xf, a_priv->gpib_base + XFER_COUNT_HI_REG);
326 }
327
328 // wrappers for interface functions
agilent_82350b_read(gpib_board_t * board,uint8_t * buffer,size_t length,int * end,size_t * bytes_read)329 int agilent_82350b_read(gpib_board_t *board, uint8_t *buffer, size_t length, int *end,
330 size_t *bytes_read)
331
332 {
333 struct agilent_82350b_priv *priv = board->private_data;
334
335 return tms9914_read(board, &priv->tms9914_priv, buffer, length, end, bytes_read);
336 }
337
agilent_82350b_write(gpib_board_t * board,uint8_t * buffer,size_t length,int send_eoi,size_t * bytes_written)338 int agilent_82350b_write(gpib_board_t *board, uint8_t *buffer, size_t length, int send_eoi,
339 size_t *bytes_written)
340
341 {
342 struct agilent_82350b_priv *priv = board->private_data;
343
344 return tms9914_write(board, &priv->tms9914_priv, buffer, length, send_eoi, bytes_written);
345 }
346
agilent_82350b_command(gpib_board_t * board,uint8_t * buffer,size_t length,size_t * bytes_written)347 int agilent_82350b_command(gpib_board_t *board, uint8_t *buffer, size_t length,
348 size_t *bytes_written)
349
350 {
351 struct agilent_82350b_priv *priv = board->private_data;
352
353 return tms9914_command(board, &priv->tms9914_priv, buffer, length, bytes_written);
354 }
355
agilent_82350b_take_control(gpib_board_t * board,int synchronous)356 int agilent_82350b_take_control(gpib_board_t *board, int synchronous)
357
358 {
359 struct agilent_82350b_priv *priv = board->private_data;
360
361 return tms9914_take_control_workaround(board, &priv->tms9914_priv, synchronous);
362 }
363
agilent_82350b_go_to_standby(gpib_board_t * board)364 int agilent_82350b_go_to_standby(gpib_board_t *board)
365
366 {
367 struct agilent_82350b_priv *priv = board->private_data;
368
369 return tms9914_go_to_standby(board, &priv->tms9914_priv);
370 }
371
agilent_82350b_request_system_control(gpib_board_t * board,int request_control)372 void agilent_82350b_request_system_control(gpib_board_t *board, int request_control)
373
374 {
375 struct agilent_82350b_priv *a_priv = board->private_data;
376
377 if (request_control) {
378 a_priv->card_mode_bits |= CM_SYSTEM_CONTROLLER_BIT;
379 if (a_priv->model != MODEL_82350A)
380 writeb(IC_SYSTEM_CONTROLLER_BIT, a_priv->gpib_base + INTERNAL_CONFIG_REG);
381 } else {
382 a_priv->card_mode_bits &= ~CM_SYSTEM_CONTROLLER_BIT;
383 if (a_priv->model != MODEL_82350A)
384 writeb(0, a_priv->gpib_base + INTERNAL_CONFIG_REG);
385 }
386 writeb(a_priv->card_mode_bits, a_priv->gpib_base + CARD_MODE_REG);
387 tms9914_request_system_control(board, &a_priv->tms9914_priv, request_control);
388 }
389
agilent_82350b_interface_clear(gpib_board_t * board,int assert)390 void agilent_82350b_interface_clear(gpib_board_t *board, int assert)
391
392 {
393 struct agilent_82350b_priv *priv = board->private_data;
394
395 tms9914_interface_clear(board, &priv->tms9914_priv, assert);
396 }
397
agilent_82350b_remote_enable(gpib_board_t * board,int enable)398 void agilent_82350b_remote_enable(gpib_board_t *board, int enable)
399
400 {
401 struct agilent_82350b_priv *priv = board->private_data;
402
403 tms9914_remote_enable(board, &priv->tms9914_priv, enable);
404 }
405
agilent_82350b_enable_eos(gpib_board_t * board,uint8_t eos_byte,int compare_8_bits)406 int agilent_82350b_enable_eos(gpib_board_t *board, uint8_t eos_byte, int compare_8_bits)
407
408 {
409 struct agilent_82350b_priv *priv = board->private_data;
410
411 return tms9914_enable_eos(board, &priv->tms9914_priv, eos_byte, compare_8_bits);
412 }
413
agilent_82350b_disable_eos(gpib_board_t * board)414 void agilent_82350b_disable_eos(gpib_board_t *board)
415
416 {
417 struct agilent_82350b_priv *priv = board->private_data;
418
419 tms9914_disable_eos(board, &priv->tms9914_priv);
420 }
421
agilent_82350b_update_status(gpib_board_t * board,unsigned int clear_mask)422 unsigned int agilent_82350b_update_status(gpib_board_t *board, unsigned int clear_mask)
423
424 {
425 struct agilent_82350b_priv *priv = board->private_data;
426
427 return tms9914_update_status(board, &priv->tms9914_priv, clear_mask);
428 }
429
agilent_82350b_primary_address(gpib_board_t * board,unsigned int address)430 int agilent_82350b_primary_address(gpib_board_t *board, unsigned int address)
431
432 {
433 struct agilent_82350b_priv *priv = board->private_data;
434
435 return tms9914_primary_address(board, &priv->tms9914_priv, address);
436 }
437
agilent_82350b_secondary_address(gpib_board_t * board,unsigned int address,int enable)438 int agilent_82350b_secondary_address(gpib_board_t *board, unsigned int address, int enable)
439
440 {
441 struct agilent_82350b_priv *priv = board->private_data;
442
443 return tms9914_secondary_address(board, &priv->tms9914_priv, address, enable);
444 }
445
agilent_82350b_parallel_poll(gpib_board_t * board,uint8_t * result)446 int agilent_82350b_parallel_poll(gpib_board_t *board, uint8_t *result)
447
448 {
449 struct agilent_82350b_priv *priv = board->private_data;
450
451 return tms9914_parallel_poll(board, &priv->tms9914_priv, result);
452 }
453
agilent_82350b_parallel_poll_configure(gpib_board_t * board,uint8_t config)454 void agilent_82350b_parallel_poll_configure(gpib_board_t *board, uint8_t config)
455
456 {
457 struct agilent_82350b_priv *priv = board->private_data;
458
459 tms9914_parallel_poll_configure(board, &priv->tms9914_priv, config);
460 }
461
agilent_82350b_parallel_poll_response(gpib_board_t * board,int ist)462 void agilent_82350b_parallel_poll_response(gpib_board_t *board, int ist)
463
464 {
465 struct agilent_82350b_priv *priv = board->private_data;
466
467 tms9914_parallel_poll_response(board, &priv->tms9914_priv, ist);
468 }
469
agilent_82350b_serial_poll_response(gpib_board_t * board,uint8_t status)470 void agilent_82350b_serial_poll_response(gpib_board_t *board, uint8_t status)
471
472 {
473 struct agilent_82350b_priv *priv = board->private_data;
474
475 tms9914_serial_poll_response(board, &priv->tms9914_priv, status);
476 }
477
agilent_82350b_serial_poll_status(gpib_board_t * board)478 uint8_t agilent_82350b_serial_poll_status(gpib_board_t *board)
479
480 {
481 struct agilent_82350b_priv *priv = board->private_data;
482
483 return tms9914_serial_poll_status(board, &priv->tms9914_priv);
484 }
485
agilent_82350b_line_status(const gpib_board_t * board)486 int agilent_82350b_line_status(const gpib_board_t *board)
487
488 {
489 struct agilent_82350b_priv *priv = board->private_data;
490
491 return tms9914_line_status(board, &priv->tms9914_priv);
492 }
493
agilent_82350b_t1_delay(gpib_board_t * board,unsigned int nanosec)494 unsigned int agilent_82350b_t1_delay(gpib_board_t *board, unsigned int nanosec)
495
496 {
497 struct agilent_82350b_priv *a_priv = board->private_data;
498 static const int nanosec_per_clock = 30;
499 unsigned int value;
500
501 tms9914_t1_delay(board, &a_priv->tms9914_priv, nanosec);
502
503 value = (nanosec + nanosec_per_clock - 1) / nanosec_per_clock;
504 if (value > 0xff)
505 value = 0xff;
506 writeb(value, a_priv->gpib_base + T1_DELAY_REG);
507 return value * nanosec_per_clock;
508 }
509
agilent_82350b_return_to_local(gpib_board_t * board)510 void agilent_82350b_return_to_local(gpib_board_t *board)
511
512 {
513 struct agilent_82350b_priv *priv = board->private_data;
514
515 tms9914_return_to_local(board, &priv->tms9914_priv);
516 }
517
agilent_82350b_allocate_private(gpib_board_t * board)518 int agilent_82350b_allocate_private(gpib_board_t *board)
519
520 {
521 board->private_data = kzalloc(sizeof(struct agilent_82350b_priv), GFP_KERNEL);
522 if (!board->private_data)
523 return -ENOMEM;
524 return 0;
525 }
526
agilent_82350b_free_private(gpib_board_t * board)527 void agilent_82350b_free_private(gpib_board_t *board)
528
529 {
530 kfree(board->private_data);
531 board->private_data = NULL;
532 }
533
init_82350a_hardware(gpib_board_t * board,const gpib_board_config_t * config)534 static int init_82350a_hardware(gpib_board_t *board, const gpib_board_config_t *config)
535
536 {
537 struct agilent_82350b_priv *a_priv = board->private_data;
538 static const unsigned int firmware_length = 5302;
539 unsigned int borg_status;
540 static const unsigned int timeout = 1000;
541 int i, j;
542 const char *firmware_data = config->init_data;
543 const unsigned int plx_cntrl_static_bits = PLX9050_WAITO_NOT_USER0_SELECT_BIT |
544 PLX9050_USER0_OUTPUT_BIT |
545 PLX9050_LLOCK_NOT_USER1_SELECT_BIT |
546 PLX9050_USER1_OUTPUT_BIT |
547 PLX9050_USER2_OUTPUT_BIT |
548 PLX9050_USER3_OUTPUT_BIT |
549 PLX9050_PCI_READ_MODE_BIT |
550 PLX9050_PCI_WRITE_MODE_BIT |
551 PLX9050_PCI_RETRY_DELAY_BITS(64) |
552 PLX9050_DIRECT_SLAVE_LOCK_ENABLE_BIT;
553
554 // load borg data
555 borg_status = readb(a_priv->borg_base);
556 if ((borg_status & BORG_DONE_BIT))
557 return 0;
558 // need to programme borg
559 if (!config->init_data || config->init_data_length != firmware_length) {
560 dev_err(board->gpib_dev, "%s: the 82350A board requires firmware after powering on.\n",
561 driver_name);
562 return -EIO;
563 }
564 dev_info(board->gpib_dev, "%s: Loading firmware...\n", driver_name);
565
566 // tickle the borg
567 writel(plx_cntrl_static_bits | PLX9050_USER3_DATA_BIT,
568 a_priv->plx_base + PLX9050_CNTRL_REG);
569 usleep_range(1000, 2000);
570 writel(plx_cntrl_static_bits, a_priv->plx_base + PLX9050_CNTRL_REG);
571 usleep_range(1000, 2000);
572 writel(plx_cntrl_static_bits | PLX9050_USER3_DATA_BIT,
573 a_priv->plx_base + PLX9050_CNTRL_REG);
574 usleep_range(1000, 2000);
575
576 for (i = 0; i < config->init_data_length; ++i) {
577 for (j = 0; j < timeout && (readb(a_priv->borg_base) & BORG_READY_BIT) == 0; ++j) {
578 if (need_resched())
579 schedule();
580 usleep_range(10, 20);
581 }
582 if (j == timeout) {
583 dev_err(board->gpib_dev, "%s: timed out loading firmware.\n", driver_name);
584 return -ETIMEDOUT;
585 }
586 writeb(firmware_data[i], a_priv->gpib_base + CONFIG_DATA_REG);
587 }
588 for (j = 0; j < timeout && (readb(a_priv->borg_base) & BORG_DONE_BIT) == 0; ++j) {
589 if (need_resched())
590 schedule();
591 usleep_range(10, 20);
592 }
593 if (j == timeout) {
594 dev_err(board->gpib_dev, "%s: timed out waiting for firmware load to complete.\n",
595 driver_name);
596 return -ETIMEDOUT;
597 }
598 dev_info(board->gpib_dev, "%s: ...done.\n", driver_name);
599 return 0;
600 }
601
test_sram(gpib_board_t * board)602 static int test_sram(gpib_board_t *board)
603
604 {
605 struct agilent_82350b_priv *a_priv = board->private_data;
606 unsigned int i;
607 const unsigned int sram_length = pci_resource_len(a_priv->pci_device, SRAM_82350A_REGION);
608 // test SRAM
609 const unsigned int byte_mask = 0xff;
610
611 for (i = 0; i < sram_length; ++i) {
612 writeb(i & byte_mask, a_priv->sram_base + i);
613 if (need_resched())
614 schedule();
615 }
616 for (i = 0; i < sram_length; ++i) {
617 unsigned int read_value = readb(a_priv->sram_base + i);
618
619 if ((i & byte_mask) != read_value) {
620 dev_err(board->gpib_dev, "%s: SRAM test failed at %d wanted %d got %d\n",
621 driver_name, i, (i & byte_mask), read_value);
622 return -EIO;
623 }
624 if (need_resched())
625 schedule();
626 }
627 dev_info(board->gpib_dev, "%s: SRAM test passed 0x%x bytes checked\n",
628 driver_name, sram_length);
629 return 0;
630 }
631
agilent_82350b_generic_attach(gpib_board_t * board,const gpib_board_config_t * config,int use_fifos)632 static int agilent_82350b_generic_attach(gpib_board_t *board, const gpib_board_config_t *config,
633 int use_fifos)
634
635 {
636 struct agilent_82350b_priv *a_priv;
637 struct tms9914_priv *tms_priv;
638 int retval;
639
640 board->status = 0;
641
642 if (agilent_82350b_allocate_private(board))
643 return -ENOMEM;
644 a_priv = board->private_data;
645 a_priv->using_fifos = use_fifos;
646 tms_priv = &a_priv->tms9914_priv;
647 tms_priv->read_byte = tms9914_iomem_read_byte;
648 tms_priv->write_byte = tms9914_iomem_write_byte;
649 tms_priv->offset = 1;
650
651 // find board
652 a_priv->pci_device = gpib_pci_get_device(config, PCI_VENDOR_ID_AGILENT,
653 PCI_DEVICE_ID_82350B, NULL);
654 if (a_priv->pci_device) {
655 a_priv->model = MODEL_82350B;
656 dev_info(board->gpib_dev, "%s: Agilent 82350B board found\n", driver_name);
657
658 } else {
659 a_priv->pci_device = gpib_pci_get_device(config, PCI_VENDOR_ID_AGILENT,
660 PCI_DEVICE_ID_82351A, NULL);
661 if (a_priv->pci_device) {
662 a_priv->model = MODEL_82351A;
663 dev_info(board->gpib_dev, "%s: Agilent 82351B board found\n", driver_name);
664
665 } else {
666 a_priv->pci_device = gpib_pci_get_subsys(config, PCI_VENDOR_ID_PLX,
667 PCI_DEVICE_ID_PLX_9050,
668 PCI_VENDOR_ID_HP,
669 PCI_SUBDEVICE_ID_82350A,
670 a_priv->pci_device);
671 if (a_priv->pci_device) {
672 a_priv->model = MODEL_82350A;
673 dev_info(board->gpib_dev, "%s: HP/Agilent 82350A board found\n",
674 driver_name);
675 } else {
676 dev_err(board->gpib_dev, "%s: no 82350/82351 board found\n",
677 driver_name);
678 return -ENODEV;
679 }
680 }
681 }
682 if (pci_enable_device(a_priv->pci_device)) {
683 dev_err(board->gpib_dev, "%s: error enabling pci device\n", driver_name);
684 return -EIO;
685 }
686 if (pci_request_regions(a_priv->pci_device, driver_name))
687 return -EIO;
688 switch (a_priv->model) {
689 case MODEL_82350A:
690 a_priv->plx_base = ioremap(pci_resource_start(a_priv->pci_device, PLX_MEM_REGION),
691 pci_resource_len(a_priv->pci_device, PLX_MEM_REGION));
692 dev_dbg(board->gpib_dev, "%s: plx base address remapped to 0x%p\n",
693 driver_name, a_priv->plx_base);
694 a_priv->gpib_base = ioremap(pci_resource_start(a_priv->pci_device,
695 GPIB_82350A_REGION),
696 pci_resource_len(a_priv->pci_device,
697 GPIB_82350A_REGION));
698 dev_dbg(board->gpib_dev, "%s: gpib base address remapped to 0x%p\n",
699 driver_name, a_priv->gpib_base);
700 tms_priv->mmiobase = a_priv->gpib_base + TMS9914_BASE_REG;
701 a_priv->sram_base = ioremap(pci_resource_start(a_priv->pci_device,
702 SRAM_82350A_REGION),
703 pci_resource_len(a_priv->pci_device,
704 SRAM_82350A_REGION));
705 dev_dbg(board->gpib_dev, "%s: sram base address remapped to 0x%p\n",
706 driver_name, a_priv->sram_base);
707 a_priv->borg_base = ioremap(pci_resource_start(a_priv->pci_device,
708 BORG_82350A_REGION),
709 pci_resource_len(a_priv->pci_device,
710 BORG_82350A_REGION));
711 dev_dbg(board->gpib_dev, "%s: borg base address remapped to 0x%p\n",
712 driver_name, a_priv->borg_base);
713
714 retval = init_82350a_hardware(board, config);
715 if (retval < 0)
716 return retval;
717 break;
718 case MODEL_82350B:
719 case MODEL_82351A:
720 a_priv->gpib_base = ioremap(pci_resource_start(a_priv->pci_device, GPIB_REGION),
721 pci_resource_len(a_priv->pci_device, GPIB_REGION));
722 dev_dbg(board->gpib_dev, "%s: gpib base address remapped to 0x%p\n",
723 driver_name, a_priv->gpib_base);
724 tms_priv->mmiobase = a_priv->gpib_base + TMS9914_BASE_REG;
725 a_priv->sram_base = ioremap(pci_resource_start(a_priv->pci_device, SRAM_REGION),
726 pci_resource_len(a_priv->pci_device, SRAM_REGION));
727 dev_dbg(board->gpib_dev, "%s: sram base address remapped to 0x%p\n",
728 driver_name, a_priv->sram_base);
729 a_priv->misc_base = ioremap(pci_resource_start(a_priv->pci_device, MISC_REGION),
730 pci_resource_len(a_priv->pci_device, MISC_REGION));
731 dev_dbg(board->gpib_dev, "%s: misc base address remapped to 0x%p\n",
732 driver_name, a_priv->misc_base);
733 break;
734 default:
735 pr_err("%s: invalid board\n", driver_name);
736 return -1;
737 }
738
739 retval = test_sram(board);
740 if (retval < 0)
741 return retval;
742
743 if (request_irq(a_priv->pci_device->irq, agilent_82350b_interrupt,
744 IRQF_SHARED, driver_name, board)) {
745 pr_err("%s: can't request IRQ %d\n", driver_name, a_priv->pci_device->irq);
746 return -EIO;
747 }
748 a_priv->irq = a_priv->pci_device->irq;
749 dev_dbg(board->gpib_dev, "%s: IRQ %d\n", driver_name, a_priv->irq);
750
751 writeb(0, a_priv->gpib_base + SRAM_ACCESS_CONTROL_REG);
752 a_priv->card_mode_bits = ENABLE_PCI_IRQ_BIT;
753 writeb(a_priv->card_mode_bits, a_priv->gpib_base + CARD_MODE_REG);
754
755 if (a_priv->model == MODEL_82350A) {
756 // enable PCI interrupts for 82350a
757 writel(PLX9050_LINTR1_EN_BIT | PLX9050_LINTR2_POLARITY_BIT |
758 PLX9050_PCI_INTR_EN_BIT,
759 a_priv->plx_base + PLX9050_INTCSR_REG);
760 }
761
762 if (use_fifos) {
763 writeb(ENABLE_BUFFER_END_EVENTS_BIT | ENABLE_TERM_COUNT_EVENTS_BIT,
764 a_priv->gpib_base + EVENT_ENABLE_REG);
765 writeb(ENABLE_TERM_COUNT_INTERRUPT_BIT | ENABLE_BUFFER_END_INTERRUPT_BIT |
766 ENABLE_TMS9914_INTERRUPTS_BIT, a_priv->gpib_base + INTERRUPT_ENABLE_REG);
767 //write-clear event status bits
768 writeb(BUFFER_END_STATUS_BIT | TERM_COUNT_STATUS_BIT,
769 a_priv->gpib_base + EVENT_STATUS_REG);
770 } else {
771 writeb(0, a_priv->gpib_base + EVENT_ENABLE_REG);
772 writeb(ENABLE_TMS9914_INTERRUPTS_BIT,
773 a_priv->gpib_base + INTERRUPT_ENABLE_REG);
774 }
775 board->t1_nano_sec = agilent_82350b_t1_delay(board, 2000);
776 tms9914_board_reset(tms_priv);
777
778 tms9914_online(board, tms_priv);
779
780 return 0;
781 }
782
agilent_82350b_unaccel_attach(gpib_board_t * board,const gpib_board_config_t * config)783 int agilent_82350b_unaccel_attach(gpib_board_t *board, const gpib_board_config_t *config)
784
785 {
786 return agilent_82350b_generic_attach(board, config, 0);
787 }
788
agilent_82350b_accel_attach(gpib_board_t * board,const gpib_board_config_t * config)789 int agilent_82350b_accel_attach(gpib_board_t *board, const gpib_board_config_t *config)
790
791 {
792 return agilent_82350b_generic_attach(board, config, 1);
793 }
794
agilent_82350b_detach(gpib_board_t * board)795 void agilent_82350b_detach(gpib_board_t *board)
796
797 {
798 struct agilent_82350b_priv *a_priv = board->private_data;
799 struct tms9914_priv *tms_priv;
800
801 if (a_priv) {
802 if (a_priv->plx_base) // disable interrupts
803 writel(0, a_priv->plx_base + PLX9050_INTCSR_REG);
804
805 tms_priv = &a_priv->tms9914_priv;
806 if (a_priv->irq)
807 free_irq(a_priv->irq, board);
808 if (a_priv->gpib_base) {
809 tms9914_board_reset(tms_priv);
810 if (a_priv->misc_base)
811 iounmap(a_priv->misc_base);
812 if (a_priv->borg_base)
813 iounmap(a_priv->borg_base);
814 if (a_priv->sram_base)
815 iounmap(a_priv->sram_base);
816 if (a_priv->gpib_base)
817 iounmap(a_priv->gpib_base);
818 if (a_priv->plx_base)
819 iounmap(a_priv->plx_base);
820 pci_release_regions(a_priv->pci_device);
821 }
822 if (a_priv->pci_device)
823 pci_dev_put(a_priv->pci_device);
824 }
825 agilent_82350b_free_private(board);
826 }
827
828 static gpib_interface_t agilent_82350b_unaccel_interface = {
829 .name = "agilent_82350b_unaccel",
830 .attach = agilent_82350b_unaccel_attach,
831 .detach = agilent_82350b_detach,
832 .read = agilent_82350b_read,
833 .write = agilent_82350b_write,
834 .command = agilent_82350b_command,
835 .request_system_control = agilent_82350b_request_system_control,
836 .take_control = agilent_82350b_take_control,
837 .go_to_standby = agilent_82350b_go_to_standby,
838 .interface_clear = agilent_82350b_interface_clear,
839 .remote_enable = agilent_82350b_remote_enable,
840 .enable_eos = agilent_82350b_enable_eos,
841 .disable_eos = agilent_82350b_disable_eos,
842 .parallel_poll = agilent_82350b_parallel_poll,
843 .parallel_poll_configure = agilent_82350b_parallel_poll_configure,
844 .parallel_poll_response = agilent_82350b_parallel_poll_response,
845 .local_parallel_poll_mode = NULL, // XXX
846 .line_status = agilent_82350b_line_status,
847 .update_status = agilent_82350b_update_status,
848 .primary_address = agilent_82350b_primary_address,
849 .secondary_address = agilent_82350b_secondary_address,
850 .serial_poll_response = agilent_82350b_serial_poll_response,
851 .serial_poll_status = agilent_82350b_serial_poll_status,
852 .t1_delay = agilent_82350b_t1_delay,
853 .return_to_local = agilent_82350b_return_to_local,
854 };
855
856 static gpib_interface_t agilent_82350b_interface = {
857 .name = "agilent_82350b",
858 .attach = agilent_82350b_accel_attach,
859 .detach = agilent_82350b_detach,
860 .read = agilent_82350b_accel_read,
861 .write = agilent_82350b_accel_write,
862 .command = agilent_82350b_command,
863 .request_system_control = agilent_82350b_request_system_control,
864 .take_control = agilent_82350b_take_control,
865 .go_to_standby = agilent_82350b_go_to_standby,
866 .interface_clear = agilent_82350b_interface_clear,
867 .remote_enable = agilent_82350b_remote_enable,
868 .enable_eos = agilent_82350b_enable_eos,
869 .disable_eos = agilent_82350b_disable_eos,
870 .parallel_poll = agilent_82350b_parallel_poll,
871 .parallel_poll_configure = agilent_82350b_parallel_poll_configure,
872 .parallel_poll_response = agilent_82350b_parallel_poll_response,
873 .local_parallel_poll_mode = NULL, // XXX
874 .line_status = agilent_82350b_line_status,
875 .update_status = agilent_82350b_update_status,
876 .primary_address = agilent_82350b_primary_address,
877 .secondary_address = agilent_82350b_secondary_address,
878 .serial_poll_response = agilent_82350b_serial_poll_response,
879 .serial_poll_status = agilent_82350b_serial_poll_status,
880 .t1_delay = agilent_82350b_t1_delay,
881 .return_to_local = agilent_82350b_return_to_local,
882 };
883
agilent_82350b_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)884 static int agilent_82350b_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
885
886 {
887 return 0;
888 }
889
890 static const struct pci_device_id agilent_82350b_pci_table[] = {
891 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_HP,
892 PCI_SUBDEVICE_ID_82350A, 0, 0, 0 },
893 { PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_82350B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
894 { PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_82351A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
895 { 0 }
896 };
897 MODULE_DEVICE_TABLE(pci, agilent_82350b_pci_table);
898
899 static struct pci_driver agilent_82350b_pci_driver = {
900 .name = "agilent_82350b",
901 .id_table = agilent_82350b_pci_table,
902 .probe = &agilent_82350b_pci_probe
903 };
904
agilent_82350b_init_module(void)905 static int __init agilent_82350b_init_module(void)
906
907 {
908 int result;
909
910 result = pci_register_driver(&agilent_82350b_pci_driver);
911 if (result) {
912 pr_err("agilent_82350b: pci_register_driver failed: error = %d\n", result);
913 return result;
914 }
915
916 result = gpib_register_driver(&agilent_82350b_unaccel_interface, THIS_MODULE);
917 if (result) {
918 pr_err("agilent_82350b: gpib_register_driver failed: error = %d\n", result);
919 goto err_unaccel;
920 }
921
922 result = gpib_register_driver(&agilent_82350b_interface, THIS_MODULE);
923 if (result) {
924 pr_err("agilent_82350b: gpib_register_driver failed: error = %d\n", result);
925 goto err_interface;
926 }
927
928 return 0;
929
930 err_interface:
931 gpib_unregister_driver(&agilent_82350b_unaccel_interface);
932 err_unaccel:
933 pci_unregister_driver(&agilent_82350b_pci_driver);
934
935 return result;
936 }
937
agilent_82350b_exit_module(void)938 static void __exit agilent_82350b_exit_module(void)
939
940 {
941 gpib_unregister_driver(&agilent_82350b_interface);
942 gpib_unregister_driver(&agilent_82350b_unaccel_interface);
943
944 pci_unregister_driver(&agilent_82350b_pci_driver);
945 }
946
947 module_init(agilent_82350b_init_module);
948 module_exit(agilent_82350b_exit_module);
949