1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DDP_COMMON_H_ 4 #define _DDP_COMMON_H_ 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 struct disp_ovl_regs { 10 u32 sta; 11 u32 inten; 12 u32 intsta; 13 u32 en; 14 u32 trig; 15 u32 rst; 16 u8 reserved0[8]; 17 u32 roi_size; 18 u32 datapath_con; 19 u32 roi_bgclr; 20 u32 src_con; 21 struct { 22 u32 con; 23 u32 srckey; 24 u32 src_size; 25 u32 offset; 26 u32 reserved0; 27 u32 pitch; 28 u32 reserved1[2]; 29 } layer[4]; 30 u8 reserved8[16]; 31 struct { 32 u32 ctrl; 33 u32 mem_start_trig; 34 u32 mem_gmc_setting; 35 u32 mem_slow_con; 36 u32 fifo_ctrl; 37 u8 reserved[12]; 38 } rdma[4]; 39 u8 reserved12[148]; 40 u32 debug_mon_sel; 41 u8 reserved13[8]; 42 u32 rdma_mem_gmc_setting2[4]; 43 u8 reserved14[16]; 44 u32 dummy; 45 u8 reserved15[60]; 46 u32 flow_ctrl_dbg; 47 u32 addcon_dbg; 48 u32 outmux_dbg; 49 u32 rdma_dbg[4]; 50 u8 reserved16[3300]; 51 u32 l0_addr; 52 u8 reserved17[28]; 53 u32 l1_addr; 54 u8 reserved18[28]; 55 u32 l2_addr; 56 u8 reserved19[28]; 57 u32 l3_addr; 58 }; 59 60 check_member(disp_ovl_regs, l3_addr, 0xFA0); 61 static struct disp_ovl_regs *const disp_ovl[2] = { 62 (void *)DISP_OVL0_BASE, (void *)DISP_OVL1_BASE 63 }; 64 65 struct disp_rdma_regs { 66 u32 int_enable; 67 u32 int_status; 68 u8 reserved0[8]; 69 u32 global_con; 70 u32 size_con_0; 71 u32 size_con_1; 72 u32 target_line; 73 u8 reserved1[4]; 74 u32 mem_con; 75 u32 mem_start_addr; 76 u32 mem_src_pitch; 77 u32 mem_gmc_setting_0; 78 u32 mem_slow_con; 79 u32 mem_gmc_setting_1; 80 u8 reserved2[4]; 81 u32 fifo_con; 82 u8 reserved3[16]; 83 u32 cf[3][3]; 84 u32 cf_pre_add[3]; 85 u32 cf_post_add[3]; 86 u32 dummy; 87 u32 debug_out_sel; 88 }; 89 90 enum { 91 RDMA_ENGINE_EN = BIT(0), 92 RDMA_FIFO_UNDERFLOW_EN = BIT(31), 93 RDMA_MEM_GMC = 0x40402020, 94 }; 95 96 check_member(disp_rdma_regs, debug_out_sel, 0x94); 97 static struct disp_rdma_regs *const disp_rdma0 = (void *)DISP_RDMA0_BASE; 98 99 struct disp_color_regs { 100 u8 reserved0[1024]; 101 u32 cfg_main; 102 u8 reserved1[2044]; 103 u32 start; 104 u8 reserved2[76]; 105 u32 width; 106 u32 height; 107 }; 108 109 check_member(disp_color_regs, cfg_main, 0x400); 110 check_member(disp_color_regs, start, 0xC00); 111 check_member(disp_color_regs, width, 0xC50); 112 check_member(disp_color_regs, height, 0xC54); 113 static struct disp_color_regs *const disp_color0 = (void *)DISP_COLOR0_BASE; 114 115 enum { 116 COLOR_BYPASS_ALL = BIT(7), 117 COLOR_SEQ_SEL = BIT(13), 118 }; 119 120 enum OVL_INPUT_FORMAT { 121 OVL_INFMT_RGB565 = 0, 122 OVL_INFMT_RGB888 = 1, 123 OVL_INFMT_RGBA8888 = 2, 124 OVL_INFMT_ARGB8888 = 3, 125 OVL_INFMT_UYVY = 4, 126 OVL_INFMT_YUYV = 5, 127 OVL_INFMT_UNKNOWN = 16, 128 129 OVL_COLOR_BASE = 30, 130 OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, 131 OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, 132 OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, 133 OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, 134 }; 135 136 void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color); 137 void rdma_start(void); 138 void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size); 139 void color_start(u32 width, u32 height); 140 void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height); 141 142 #endif 143