1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #pragma once 26 27 #include <stdint.h> 28 #include <stddef.h> 29 #include <stdbool.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /*********************************************************************** 36 * Note: do *not* add any types which are *not* used for HW programming. 37 * this will ensure separation of Logic layer from HW layer 38 ***********************************************************************/ 39 union large_integer { 40 struct { 41 uint32_t low_part; 42 int32_t high_part; 43 }; 44 45 struct { 46 uint32_t low_part; 47 int32_t high_part; 48 } u; 49 50 int64_t quad_part; 51 }; 52 53 #define PHYSICAL_ADDRESS_LOC union large_integer 54 55 enum vpe_plane_addr_type { 56 VPE_PLN_ADDR_TYPE_GRAPHICS = 0, 57 VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE 58 }; 59 60 struct vpe_plane_address { 61 enum vpe_plane_addr_type type; 62 bool tmz_surface; 63 union { 64 struct { 65 PHYSICAL_ADDRESS_LOC addr; 66 PHYSICAL_ADDRESS_LOC meta_addr; 67 union large_integer dcc_const_color; 68 } grph; 69 70 /*video progressive*/ 71 struct { 72 PHYSICAL_ADDRESS_LOC luma_addr; 73 PHYSICAL_ADDRESS_LOC luma_meta_addr; 74 union large_integer luma_dcc_const_color; 75 76 PHYSICAL_ADDRESS_LOC chroma_addr; 77 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 78 union large_integer chroma_dcc_const_color; 79 } video_progressive; 80 }; 81 }; 82 83 /* Rotation angle */ 84 enum vpe_rotation_angle { 85 VPE_ROTATION_ANGLE_0 = 0, 86 VPE_ROTATION_ANGLE_90, 87 VPE_ROTATION_ANGLE_180, 88 VPE_ROTATION_ANGLE_270, 89 VPE_ROTATION_ANGLE_COUNT 90 }; 91 92 /* mirror */ 93 enum vpe_mirror { 94 VPE_MIRROR_NONE, 95 VPE_MIRROR_HORIZONTAL, 96 VPE_MIRROR_VERTICAL 97 }; 98 99 enum vpe_scan_direction { 100 VPE_SCAN_PATTERN_0_DEGREE = 0, 101 VPE_SCAN_PATTERN_90_DEGREE = 1, 102 VPE_SCAN_PATTERN_180_DEGREE = 2, 103 VPE_SCAN_PATTERN_270_DEGREE = 3, 104 }; 105 106 struct vpe_size { 107 uint32_t width; 108 uint32_t height; 109 }; 110 111 struct vpe_rect { 112 int32_t x; 113 int32_t y; 114 uint32_t width; 115 uint32_t height; 116 }; 117 118 struct vpe_plane_size { 119 struct vpe_rect surface_size; 120 struct vpe_rect chroma_size; 121 122 // actual aligned pitch and height 123 uint32_t surface_pitch; 124 uint32_t chroma_pitch; 125 126 uint32_t surface_aligned_height; 127 uint32_t chrome_aligned_height; 128 }; 129 130 struct vpe_plane_dcc_param { 131 bool enable; 132 133 uint32_t meta_pitch; 134 bool independent_64b_blks; 135 uint8_t dcc_ind_blk; 136 137 uint32_t meta_pitch_c; 138 bool independent_64b_blks_c; 139 uint8_t dcc_ind_blk_c; 140 }; 141 142 /** Displayable pixel format in fb */ 143 enum vpe_surface_pixel_format { 144 VPE_SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 145 /*16 bpp*/ 146 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 147 /*16 bpp*/ 148 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565, 149 /*32 bpp*/ 150 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 151 /*32 bpp swaped*/ 152 VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 153 /*32 bpp alpha rotated*/ 154 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888, 155 /*32 bpp swaped & alpha rotated*/ 156 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, 157 158 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 159 /*swaped*/ 160 VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 161 /*alpha rotated*/ 162 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102, 163 /*swaped & alpha rotated*/ 164 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102, 165 166 /*64 bpp */ 167 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 168 /*float*/ 169 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 170 /*swaped & float*/ 171 VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 172 /*alpha rotated*/ 173 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F, 174 /*swaped & alpha rotated*/ 175 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F, 176 177 VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888, 178 /*swaped*/ 179 VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888, 180 /*rotated*/ 181 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888, 182 /*swaped & rotated*/ 183 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888, 184 /*grow graphics here if necessary */ 185 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 186 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 187 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 188 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 189 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE, 190 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 191 VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 192 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 193 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 194 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 195 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 196 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCrCb, 197 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr, 198 VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr, 199 VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, 200 VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 201 VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 202 VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888, 203 VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888, 204 VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888, 205 VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, //seems to be dummy, not part of surface pixel register values 206 VPE_SURFACE_PIXEL_FORMAT_VIDEO_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, 207 VPE_SURFACE_PIXEL_FORMAT_INVALID 208 209 /*grow 444 video here if necessary */ 210 }; 211 212 enum vpe_swizzle_mode_values { 213 VPE_SW_LINEAR = 0, 214 VPE_SW_256B_S = 1, 215 VPE_SW_256B_D = 2, 216 VPE_SW_256B_R = 3, 217 VPE_SW_4KB_Z = 4, 218 VPE_SW_4KB_S = 5, 219 VPE_SW_4KB_D = 6, 220 VPE_SW_4KB_R = 7, 221 VPE_SW_64KB_Z = 8, 222 VPE_SW_64KB_S = 9, 223 VPE_SW_64KB_D = 10, 224 VPE_SW_64KB_R = 11, 225 VPE_SW_VAR_Z = 12, 226 VPE_SW_VAR_S = 13, 227 VPE_SW_VAR_D = 14, 228 VPE_SW_VAR_R = 15, 229 VPE_SW_64KB_Z_T = 16, 230 VPE_SW_64KB_S_T = 17, 231 VPE_SW_64KB_D_T = 18, 232 VPE_SW_64KB_R_T = 19, 233 VPE_SW_4KB_Z_X = 20, 234 VPE_SW_4KB_S_X = 21, 235 VPE_SW_4KB_D_X = 22, 236 VPE_SW_4KB_R_X = 23, 237 VPE_SW_64KB_Z_X = 24, 238 VPE_SW_64KB_S_X = 25, 239 VPE_SW_64KB_D_X = 26, 240 VPE_SW_64KB_R_X = 27, 241 VPE_SW_VAR_Z_X = 28, 242 VPE_SW_VAR_S_X = 29, 243 VPE_SW_VAR_D_X = 30, 244 VPE_SW_VAR_R_X = 31, 245 VPE_SW_MAX = 32, 246 VPE_SW_UNKNOWN = VPE_SW_MAX 247 }; 248 249 /** specify the number of taps. 250 * if 0 is specified, it will use 4 taps by default */ 251 struct vpe_scaling_taps { 252 uint32_t v_taps; 253 uint32_t h_taps; 254 uint32_t v_taps_c; 255 uint32_t h_taps_c; 256 }; 257 258 #ifdef __cplusplus 259 } 260 #endif 261