1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <cpu/intel/haswell/haswell.h>
5 #include <acpi/acpi.h>
6 #include <device/pci_ops.h>
7 #include <stdint.h>
8 #include <delay.h>
9 #include <device/device.h>
10 #include <device/pci.h>
11 #include <device/pci_ids.h>
12 #include <soc/acpi.h>
13 #include <soc/iomap.h>
14 #include <soc/pci_devs.h>
15 #include <soc/refcode.h>
16 #include <soc/systemagent.h>
17
systemagent_revision(void)18 u8 systemagent_revision(void)
19 {
20 struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
21 return pci_read_config8(sa_dev, PCI_REVISION_ID);
22 }
23
get_pcie_bar(struct device * dev,unsigned int index,u32 * base,u32 * len)24 static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
25 u32 *len)
26 {
27 u32 pciexbar_reg;
28
29 *base = 0;
30 *len = 0;
31
32 pciexbar_reg = pci_read_config32(dev, index);
33
34 if (!(pciexbar_reg & (1 << 0)))
35 return 0;
36
37 switch ((pciexbar_reg >> 1) & 3) {
38 case 0: // 256MB
39 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
40 (1 << 28));
41 *len = 256 * 1024 * 1024;
42 return 1;
43 case 1: // 128M
44 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
45 (1 << 28)|(1 << 27));
46 *len = 128 * 1024 * 1024;
47 return 1;
48 case 2: // 64M
49 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
50 (1 << 28)|(1 << 27)|(1 << 26));
51 *len = 64 * 1024 * 1024;
52 return 1;
53 }
54
55 return 0;
56 }
57
get_bar(struct device * dev,unsigned int index,u32 * base,u32 * len)58 static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
59 {
60 u32 bar;
61
62 bar = pci_read_config32(dev, index);
63
64 /* If not enabled don't report it. */
65 if (!(bar & 0x1))
66 return 0;
67
68 /* Knock down the enable bit. */
69 *base = bar & ~1;
70
71 return 1;
72 }
73
74 /* There are special BARs that actually are programmed in the MCHBAR. These
75 * Intel special features, but they do consume resources that need to be
76 * accounted for. */
get_bar_in_mchbar(struct device * dev,unsigned int index,u32 * base,u32 * len)77 static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
78 u32 *len)
79 {
80 u32 bar;
81
82 bar = mchbar_read32(index);
83
84 /* If not enabled don't report it. */
85 if (!(bar & 0x1))
86 return 0;
87
88 /* Knock down the enable bit. */
89 *base = bar & ~1;
90
91 return 1;
92 }
93
94 struct fixed_mmio_descriptor {
95 unsigned int index;
96 u32 size;
97 int (*get_resource)(struct device *dev, unsigned int index,
98 u32 *base, u32 *size);
99 const char *description;
100 };
101
102 struct fixed_mmio_descriptor mc_fixed_resources[] = {
103 { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
104 { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
105 { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
106 { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
107 { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
108 { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
109 };
110
111 /*
112 * Add all known fixed MMIO ranges that hang off the host bridge/memory
113 * controller device.
114 */
mc_add_fixed_mmio_resources(struct device * dev)115 static void mc_add_fixed_mmio_resources(struct device *dev)
116 {
117 int i;
118
119 for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
120 u32 base;
121 u32 size;
122 struct resource *resource;
123 unsigned int index;
124
125 size = mc_fixed_resources[i].size;
126 index = mc_fixed_resources[i].index;
127 if (!mc_fixed_resources[i].get_resource(dev, index,
128 &base, &size))
129 continue;
130
131 resource = new_resource(dev, mc_fixed_resources[i].index);
132 resource->base = base;
133 resource->size = size;
134 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
135 IORESOURCE_STORED | IORESOURCE_RESERVE |
136 IORESOURCE_ASSIGNED;
137 printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
138 __func__, mc_fixed_resources[i].description, index,
139 (unsigned long)base, (unsigned long)(base + size - 1));
140 }
141 }
142
143 /* Host Memory Map:
144 *
145 * +--------------------------+ TOUUD
146 * | |
147 * +--------------------------+ 4GiB
148 * | PCI Address Space |
149 * +--------------------------+ TOLUD (also maps into MC address space)
150 * | iGD |
151 * +--------------------------+ BDSM
152 * | GTT |
153 * +--------------------------+ BGSM
154 * | TSEG |
155 * +--------------------------+ TSEGMB
156 * | Usage DRAM |
157 * +--------------------------+ 0
158 *
159 * Some of the base registers above can be equal making the size of those
160 * regions 0. The reason is because the memory controller internally subtracts
161 * the base registers from each other to determine sizes of the regions. In
162 * other words, the memory map is in a fixed order no matter what.
163 */
164
165 struct map_entry {
166 int reg;
167 int is_64_bit;
168 int is_limit;
169 const char *description;
170 };
171
read_map_entry(struct device * dev,struct map_entry * entry,uint64_t * result)172 static void read_map_entry(struct device *dev, struct map_entry *entry,
173 uint64_t *result)
174 {
175 uint64_t value;
176 uint64_t mask;
177
178 /* All registers are on a 1MiB granularity. */
179 mask = ((1ULL<<20)-1);
180 mask = ~mask;
181
182 value = 0;
183
184 if (entry->is_64_bit) {
185 value = pci_read_config32(dev, entry->reg + 4);
186 value <<= 32;
187 }
188
189 value |= pci_read_config32(dev, entry->reg);
190 value &= mask;
191
192 if (entry->is_limit)
193 value |= ~mask;
194
195 *result = value;
196 }
197
198 #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
199 { \
200 .reg = reg_, \
201 .is_64_bit = is_64_, \
202 .is_limit = is_limit_, \
203 .description = desc_, \
204 }
205
206 #define MAP_ENTRY_BASE_64(reg_, desc_) \
207 MAP_ENTRY(reg_, 1, 0, desc_)
208 #define MAP_ENTRY_LIMIT_64(reg_, desc_) \
209 MAP_ENTRY(reg_, 1, 1, desc_)
210 #define MAP_ENTRY_BASE_32(reg_, desc_) \
211 MAP_ENTRY(reg_, 0, 0, desc_)
212
213 enum {
214 TOM_REG,
215 TOUUD_REG,
216 MESEG_BASE_REG,
217 MESEG_LIMIT_REG,
218 REMAP_BASE_REG,
219 REMAP_LIMIT_REG,
220 TOLUD_REG,
221 BGSM_REG,
222 BDSM_REG,
223 TSEG_REG,
224 // Must be last.
225 NUM_MAP_ENTRIES
226 };
227
228 static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
229 [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
230 [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
231 [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
232 [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
233 [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
234 [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
235 [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
236 [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
237 [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
238 [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
239 };
240
mc_read_map_entries(struct device * dev,uint64_t * values)241 static void mc_read_map_entries(struct device *dev, uint64_t *values)
242 {
243 int i;
244 for (i = 0; i < NUM_MAP_ENTRIES; i++)
245 read_map_entry(dev, &memory_map[i], &values[i]);
246 }
247
mc_report_map_entries(struct device * dev,uint64_t * values)248 static void mc_report_map_entries(struct device *dev, uint64_t *values)
249 {
250 int i;
251 for (i = 0; i < NUM_MAP_ENTRIES; i++) {
252 printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
253 memory_map[i].description, values[i]);
254 }
255 /* One can validate the BDSM and BGSM against the GGC. */
256 printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
257 }
258
mc_add_dram_resources(struct device * dev,int * resource_cnt)259 static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
260 {
261 unsigned long index;
262 uint64_t mc_values[NUM_MAP_ENTRIES];
263 unsigned long dpr_size = 0;
264 u32 dpr_reg;
265
266 /* Read in the MAP registers and report their values. */
267 mc_read_map_entries(dev, &mc_values[0]);
268 mc_report_map_entries(dev, &mc_values[0]);
269
270 /*
271 * DMA Protected Range can be reserved below TSEG for PCODE patch
272 * or TXT/Boot Guard related data. Rather than report a base address
273 * the DPR register reports the TOP of the region, which is the same
274 * as TSEG base. The region size is reported in MiB in bits 11:4.
275 */
276 dpr_reg = pci_read_config32(dev, DPR);
277 if (dpr_reg & DPR_EPM) {
278 dpr_size = (dpr_reg & DPR_SIZE_MASK) << 26;
279 printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
280 }
281
282 /*
283 * These are the host memory ranges that should be added:
284 * - 0 -> 0xa0000: cacheable
285 * - 0xc0000 -> TSEG : cacheable
286 * - TESG -> BGSM: cacheable with standard MTRRs and reserved
287 * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
288 * - 4GiB -> TOUUD: cacheable
289 *
290 * The default SMRAM space is reserved so that the range doesn't
291 * have to be saved during S3 Resume. Once marked reserved the OS
292 * cannot use the memory. This is a bit of an odd place to reserve
293 * the region, but the CPU devices don't have dev_ops->read_resources()
294 * called on them.
295 *
296 * The range 0xa0000 -> 0xc0000 does not have any resources
297 * associated with it to handle legacy VGA memory. If this range
298 * is not omitted the mtrr code will setup the area as cacheable
299 * causing VGA access to not work.
300 *
301 * The TSEG region is mapped as cacheable so that one can perform
302 * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
303 * precedence over the existing MTRRs covering this region.
304 *
305 * It should be noted that cacheable entry types need to be added in
306 * order. The reason is that the current MTRR code assumes this and
307 * falls over itself if it isn't.
308 *
309 * The resource index starts low and should not meet or exceed
310 * PCI_BASE_ADDRESS_0.
311 */
312 index = *resource_cnt;
313
314
315 /*
316 * 0 - > 0xa0000: RAM
317 * 0xa0000 - 0xbffff: Legacy VGA
318 * 0xc0000 - 0xfffff: RAM
319 */
320 ram_range(dev, index++, 0, 0xa0000);
321 mmio_from_to(dev, index++, 0xa0000, 0xc0000);
322 reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
323
324 /* 1MiB -> TSEG - DPR */
325 ram_from_to(dev, index++, 1 * MiB, mc_values[TSEG_REG] - dpr_size);
326
327 /* TSEG - DPR -> BGSM */
328 reserved_ram_from_to(dev, index++, mc_values[TSEG_REG] - dpr_size, mc_values[BGSM_REG]);
329
330 /* BGSM -> TOLUD */
331 mmio_from_to(dev, index++, mc_values[BGSM_REG], mc_values[TOLUD_REG]);
332
333 /* 4GiB -> TOUUD */
334 upper_ram_end(dev, index++, mc_values[TOUUD_REG]);
335
336 *resource_cnt = index;
337 }
338
systemagent_read_resources(struct device * dev)339 static void systemagent_read_resources(struct device *dev)
340 {
341 int index = 0;
342 const bool vtd_capable =
343 !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
344
345 /* Read standard PCI resources. */
346 pci_dev_read_resources(dev);
347
348 /* Add all fixed MMIO resources. */
349 mc_add_fixed_mmio_resources(dev);
350
351 /* Add VT-d MMIO resources if capable */
352 if (vtd_capable) {
353 mmio_range(dev, index++, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE);
354 mmio_range(dev, index++, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE);
355 }
356
357 /* Calculate and add DRAM resources. */
358 mc_add_dram_resources(dev, &index);
359 }
360
systemagent_init(struct device * dev)361 static void systemagent_init(struct device *dev)
362 {
363 /* Enable Power Aware Interrupt Routing. */
364 mchbar_clrsetbits8(MCH_PAIR, 0x7, 0x4); /* Clear 2:0, set Fixed Priority */
365
366 /*
367 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
368 * that BIOS has initialized memory and power management
369 */
370 mchbar_setbits8(BIOS_RESET_CPL, 3);
371 printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
372
373 /* Configure turbo power limits 1ms after reset complete bit */
374 mdelay(1);
375 set_power_limits(28);
376 }
377
378 static struct device_operations systemagent_ops = {
379 .read_resources = systemagent_read_resources,
380 .set_resources = pci_dev_set_resources,
381 .enable_resources = pci_dev_enable_resources,
382 .init = systemagent_init,
383 .ops_pci = &pci_dev_ops_pci,
384 };
385
386 static const unsigned short systemagent_ids[] = {
387 0x0a04, /* Haswell ULT */
388 0x1604, /* Broadwell-U/Y */
389 0x1610, /* Broadwell-H Desktop */
390 0x1614, /* Broadwell-H Mobile */
391 0
392 };
393
394 static const struct pci_driver systemagent_driver __pci_driver = {
395 .ops = &systemagent_ops,
396 .vendor = PCI_VID_INTEL,
397 .devices = systemagent_ids
398 };
399
400 struct device_operations broadwell_pci_domain_ops = {
401 .read_resources = &pci_domain_read_resources,
402 .set_resources = &pci_domain_set_resources,
403 .scan_bus = &pci_host_bridge_scan_bus,
404 #if CONFIG(HAVE_ACPI_TABLES)
405 .write_acpi_tables = &northbridge_write_acpi_tables,
406 #endif
407 };
408
409 struct device_operations broadwell_cpu_bus_ops = {
410 .read_resources = noop_read_resources,
411 .set_resources = noop_set_resources,
412 .init = mp_cpu_bus_init,
413 .acpi_fill_ssdt = generate_cpu_entries,
414 };
415
broadwell_init_pre_device(void * chip_info)416 static void broadwell_init_pre_device(void *chip_info)
417 {
418 broadwell_run_reference_code();
419 }
420
421 struct chip_operations soc_intel_broadwell_ops = {
422 .name = "Intel Broadwell",
423 .init = &broadwell_init_pre_device,
424 };
425