| /aosp_15_r20/external/coreboot/util/inteltool/ |
| H A D | ivy_memory.c | 71 unsigned int tRCD[2], tXP[2], tXPDLL[2], tRAS[2], tCWL[2], tRP[2], in ivybridge_dump_timings() local
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/haswell/native_raminit/ |
| H A D | raminit_native.h | 77 uint32_t tCWL; member
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| /aosp_15_r20/external/coreboot/src/include/device/dram/ |
| H A D | ddr3.h | 135 u32 tCWL; member
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/sandybridge/ |
| H A D | raminit_common.h | 182 u32 tCWL : 4; /* [15..12] */ member
378 u32 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/jasperlake/ |
| H A D | MemInfoHob.h | 148 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 492 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/ |
| H A D | MemInfoHob.h | 160 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 641 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/ |
| H A D | MemInfoHob.h | 191 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 626 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/ |
| H A D | MemInfoHob.h | 157 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/ |
| H A D | MemInfoHob.h | 172 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 626 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/ |
| H A D | MemInfoHob.h | 162 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 628 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/ |
| H A D | MemInfoHob.h | 162 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 628 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/ |
| H A D | MemInfoHob.h | 162 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| H A D | FspmUpd.h | 628 UINT8 tCWL; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.0.0/ |
| H A D | FspmUpd.h | 75 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.3.1/ |
| H A D | FspmUpd.h | 75 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
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