| /aosp_15_r20/external/coreboot/util/inteltool/ |
| H A D | ivy_memory.c | 65 int tFAW[2], tWTR[2], tCKE[2], tRTP[2], tRRD[2]; in ivybridge_dump_timings() local
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/haswell/native_raminit/ |
| H A D | raminit_native.h | 74 uint32_t tWTR; member
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| /aosp_15_r20/external/coreboot/src/include/device/dram/ |
| H A D | ddr3.h | 132 u32 tWTR; member
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| H A D | ddr2.h | 135 u32 tWTR; member
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/sandybridge/ |
| H A D | raminit_common.h | 194 u32 tWTR : 4; /* [15..12] */ member
375 u32 tWTR; member
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/pineview/ |
| H A D | raminit.h | 53 unsigned int tWTR; member
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/x4x/ |
| H A D | raminit.h | 154 unsigned int tWTR; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/jasperlake/ |
| H A D | MemInfoHob.h | 163 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| H A D | FspmUpd.h | 555 UINT8 tWTR; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/ |
| H A D | MemInfoHob.h | 175 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/ |
| H A D | MemInfoHob.h | 206 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| H A D | FspmUpd.h | 686 UINT8 tWTR; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/ |
| H A D | MemInfoHob.h | 172 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/ |
| H A D | MemInfoHob.h | 187 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| H A D | FspmUpd.h | 686 UINT8 tWTR; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/ |
| H A D | MemInfoHob.h | 177 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| H A D | FspmUpd.h | 693 UINT8 tWTR; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/ |
| H A D | MemInfoHob.h | 177 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| H A D | FspmUpd.h | 693 UINT8 tWTR; member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/ |
| H A D | MemInfoHob.h | 177 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| H A D | FspmUpd.h | 693 UINT8 tWTR; member
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/i945/ |
| H A D | raminit.c | 1354 u32 tWTR; in sdram_set_timing_and_control() local
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| /aosp_15_r20/external/coreboot/src/northbridge/intel/gm45/ |
| H A D | raminit.c | 1102 const int tWTR = (spd_type == DDR2) ? 3 : 4, tRTP = 1; in dram_program_timings() local
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.0.0/ |
| H A D | FspmUpd.h | 90 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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| /aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.3.1/ |
| H A D | FspmUpd.h | 90 …UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read … member
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