1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <[email protected]>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #ifndef VC4_CONTEXT_H
26 #define VC4_CONTEXT_H
27
28 #include <stdio.h>
29
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/slab.h"
33 #include "util/u_debug_cb.h"
34 #include "xf86drm.h"
35
36 #define __user
37 #include "drm-uapi/vc4_drm.h"
38 #include "vc4_bufmgr.h"
39 #include "vc4_resource.h"
40 #include "vc4_cl.h"
41 #include "vc4_qir.h"
42
43 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
44 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4
45 #endif
46 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
47 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
48 #endif
49
50 #define VC4_DIRTY_BLEND (1 << 0)
51 #define VC4_DIRTY_RASTERIZER (1 << 1)
52 #define VC4_DIRTY_ZSA (1 << 2)
53 #define VC4_DIRTY_FRAGTEX (1 << 3)
54 #define VC4_DIRTY_VERTTEX (1 << 4)
55
56 #define VC4_DIRTY_BLEND_COLOR (1 << 7)
57 #define VC4_DIRTY_STENCIL_REF (1 << 8)
58 #define VC4_DIRTY_SAMPLE_MASK (1 << 9)
59 #define VC4_DIRTY_FRAMEBUFFER (1 << 10)
60 #define VC4_DIRTY_STIPPLE (1 << 11)
61 #define VC4_DIRTY_VIEWPORT (1 << 12)
62 #define VC4_DIRTY_CONSTBUF (1 << 13)
63 #define VC4_DIRTY_VTXSTATE (1 << 14)
64 #define VC4_DIRTY_VTXBUF (1 << 15)
65
66 #define VC4_DIRTY_SCISSOR (1 << 17)
67 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
68 #define VC4_DIRTY_PRIM_MODE (1 << 19)
69 #define VC4_DIRTY_CLIP (1 << 20)
70 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
71 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
72 #define VC4_DIRTY_COMPILED_CS (1 << 23)
73 #define VC4_DIRTY_COMPILED_VS (1 << 24)
74 #define VC4_DIRTY_COMPILED_FS (1 << 25)
75 #define VC4_DIRTY_FS_INPUTS (1 << 26)
76 #define VC4_DIRTY_UBO_1_SIZE (1 << 27)
77
78 struct vc4_sampler_view {
79 struct pipe_sampler_view base;
80 uint32_t texture_p0;
81 uint32_t texture_p1;
82 bool force_first_level;
83 /**
84 * Resource containing the actual texture that will be sampled.
85 *
86 * We may need to rebase the .base.texture resource to work around the
87 * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
88 */
89 struct pipe_resource *texture;
90 };
91
92 struct vc4_sampler_state {
93 struct pipe_sampler_state base;
94 uint32_t texture_p1;
95 };
96
97 struct vc4_texture_stateobj {
98 struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
99 unsigned num_textures;
100 struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
101 unsigned num_samplers;
102 };
103
104 struct vc4_shader_uniform_info {
105 enum quniform_contents *contents;
106 uint32_t *data;
107 uint32_t count;
108 uint32_t num_texture_samples;
109 };
110
111 struct vc4_uncompiled_shader {
112 /** A name for this program, so you can track it in shader-db output. */
113 uint32_t program_id;
114 /** How many variants of this program were compiled, for shader-db. */
115 uint32_t compiled_variant_count;
116 struct pipe_shader_state base;
117 };
118
119 struct vc4_fs_inputs {
120 /**
121 * Array of the meanings of the VPM inputs this shader needs.
122 *
123 * It doesn't include those that aren't part of the VPM, like
124 * point/line coordinates.
125 */
126 struct vc4_varying_slot *input_slots;
127 uint32_t num_inputs;
128 };
129
130 struct vc4_compiled_shader {
131 uint64_t program_id;
132 struct vc4_bo *bo;
133
134 struct vc4_shader_uniform_info uniforms;
135
136 /**
137 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
138 * uniforms have to be rewritten (and therefore the shader state
139 * reemitted).
140 */
141 uint32_t uniform_dirty_bits;
142
143 /** bitmask of which inputs are color inputs, for flat shade handling. */
144 uint32_t color_inputs;
145
146 bool disable_early_z;
147
148 /* Set if the compile failed, likely due to register allocation
149 * failure. In this case, we have no shader to run and should not try
150 * to do any draws.
151 */
152 bool failed;
153
154 bool fs_threaded;
155
156 uint8_t num_inputs;
157
158 /* Byte offsets for the start of the vertex attributes 0-7, and the
159 * total size as "attribute" 8.
160 */
161 uint8_t vattr_offsets[9];
162 uint8_t vattrs_live;
163
164 const struct vc4_fs_inputs *fs_inputs;
165 };
166
167 struct vc4_program_stateobj {
168 struct vc4_uncompiled_shader *bind_vs, *bind_fs;
169 struct vc4_compiled_shader *cs, *vs, *fs;
170 };
171
172 struct vc4_constbuf_stateobj {
173 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
174 uint32_t enabled_mask;
175 uint32_t dirty_mask;
176 };
177
178 struct vc4_vertexbuf_stateobj {
179 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
180 unsigned count;
181 uint32_t enabled_mask;
182 uint32_t dirty_mask;
183 };
184
185 struct vc4_vertex_stateobj {
186 struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
187 unsigned num_elements;
188 };
189
190 /* Hash table key for vc4->jobs */
191 struct vc4_job_key {
192 struct pipe_surface *cbuf;
193 struct pipe_surface *zsbuf;
194 };
195
196 struct vc4_hwperfmon {
197 uint32_t id;
198 uint64_t last_seqno;
199 uint8_t events[DRM_VC4_MAX_PERF_COUNTERS];
200 uint64_t counters[DRM_VC4_MAX_PERF_COUNTERS];
201 };
202
203 /**
204 * A complete bin/render job.
205 *
206 * This is all of the state necessary to submit a bin/render to the kernel.
207 * We want to be able to have multiple in progress at a time, so that we don't
208 * need to flush an existing CL just to switch to rendering to a new render
209 * target (which would mean reading back from the old render target when
210 * starting to render to it again).
211 */
212 struct vc4_job {
213 struct vc4_cl bcl;
214 struct vc4_cl shader_rec;
215 struct vc4_cl uniforms;
216 struct vc4_cl bo_handles;
217 struct vc4_cl bo_pointers;
218 uint32_t shader_rec_count;
219 /**
220 * Amount of memory used by the BOs in bo_pointers.
221 *
222 * Used for checking when we should flush the job early so we don't
223 * OOM.
224 */
225 uint32_t bo_space;
226
227 /* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */
228 uint32_t last_gem_handle_hindex;
229
230 /** @{ Surfaces to submit rendering for. */
231 struct pipe_surface *color_read;
232 struct pipe_surface *color_write;
233 struct pipe_surface *zs_read;
234 struct pipe_surface *zs_write;
235 struct pipe_surface *msaa_color_write;
236 struct pipe_surface *msaa_zs_write;
237 /** @} */
238 /** @{
239 * Bounding box of the scissor across all queued drawing.
240 *
241 * Note that the max values are exclusive.
242 */
243 uint32_t draw_min_x;
244 uint32_t draw_min_y;
245 uint32_t draw_max_x;
246 uint32_t draw_max_y;
247 /** @} */
248 /** @{
249 * Width/height of the color framebuffer being rendered to,
250 * for VC4_TILE_RENDERING_MODE_CONFIG.
251 */
252 uint32_t draw_width;
253 uint32_t draw_height;
254 /** @} */
255 /** @{ Tile information, depending on MSAA and float color buffer. */
256 uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
257 uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
258
259 uint32_t tile_width; /** @< Width of a tile. */
260 uint32_t tile_height; /** @< Height of a tile. */
261 /** Whether the current rendering is in a 4X MSAA tile buffer. */
262 bool msaa;
263 /** @} */
264
265 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
266 * first rendering.
267 */
268 uint32_t cleared;
269 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
270 * (either clears or draws).
271 */
272 uint32_t resolve;
273 uint32_t clear_color[2];
274 uint32_t clear_depth; /**< 24-bit unorm depth */
275 uint8_t clear_stencil;
276
277 /**
278 * Set if some drawing (triangles, blits, or just a glClear()) has
279 * been done to the FBO, meaning that we need to
280 * DRM_IOCTL_VC4_SUBMIT_CL.
281 */
282 bool needs_flush;
283
284 /**
285 * Number of draw calls (not counting full buffer clears) queued in
286 * the current job.
287 */
288 uint32_t draw_calls_queued;
289
290 /** Any flags to be passed in drm_vc4_submit_cl.flags. */
291 uint32_t flags;
292
293 /* Performance monitor attached to this job. */
294 struct vc4_hwperfmon *perfmon;
295
296 struct vc4_job_key key;
297 };
298
299 struct vc4_context {
300 struct pipe_context base;
301
302 int fd;
303 struct vc4_screen *screen;
304
305 /** The 3D rendering job for the currently bound FBO. */
306 struct vc4_job *job;
307
308 /* Map from struct vc4_job_key to the job for that FBO.
309 */
310 struct hash_table *jobs;
311
312 /**
313 * Map from vc4_resource to a job writing to that resource.
314 *
315 * Primarily for flushing jobs rendering to textures that are now
316 * being read from.
317 */
318 struct hash_table *write_jobs;
319
320 struct slab_child_pool transfer_pool;
321 struct blitter_context *blitter;
322
323 /** bitfield of VC4_DIRTY_* */
324 uint32_t dirty;
325
326 struct hash_table *fs_cache, *vs_cache;
327 struct set *fs_inputs_set;
328 uint32_t next_uncompiled_program_id;
329 uint64_t next_compiled_program_id;
330
331 struct ra_regs *regs;
332 struct ra_class *reg_class_any[2];
333 struct ra_class *reg_class_a_or_b[2];
334 struct ra_class *reg_class_a_or_b_or_acc[2];
335 struct ra_class *reg_class_r0_r3;
336 struct ra_class *reg_class_r4_or_a[2];
337 struct ra_class *reg_class_a[2];
338
339 uint8_t prim_mode;
340
341 /** Maximum index buffer valid for the current shader_rec. */
342 uint32_t max_index;
343 /** Last index bias baked into the current shader_rec. */
344 uint32_t last_index_bias;
345
346 /** Seqno of the last CL flush's job. */
347 uint64_t last_emit_seqno;
348
349 struct u_upload_mgr *uploader;
350
351 struct pipe_shader_state *yuv_linear_blit_vs;
352 struct pipe_shader_state *yuv_linear_blit_fs_8bit;
353 struct pipe_shader_state *yuv_linear_blit_fs_16bit;
354
355 /** @{ Current pipeline state objects */
356 struct pipe_scissor_state scissor;
357 struct pipe_blend_state *blend;
358 struct vc4_rasterizer_state *rasterizer;
359 struct vc4_depth_stencil_alpha_state *zsa;
360
361 struct vc4_texture_stateobj verttex, fragtex;
362
363 struct vc4_program_stateobj prog;
364
365 struct vc4_vertex_stateobj *vtx;
366
367 struct {
368 struct pipe_blend_color f;
369 uint8_t ub[4];
370 } blend_color;
371 struct pipe_stencil_ref stencil_ref;
372 unsigned sample_mask;
373 struct pipe_framebuffer_state framebuffer;
374 struct pipe_poly_stipple stipple;
375 struct pipe_clip_state clip;
376 struct pipe_viewport_state viewport;
377 struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
378 struct vc4_vertexbuf_stateobj vertexbuf;
379
380 struct vc4_hwperfmon *perfmon;
381 /** @} */
382
383 /** Handle of syncobj containing the last submitted job fence. */
384 uint32_t job_syncobj;
385
386 int in_fence_fd;
387 /** Handle of the syncobj that holds in_fence_fd for submission. */
388 uint32_t in_syncobj;
389 };
390
391 struct vc4_rasterizer_state {
392 struct pipe_rasterizer_state base;
393
394 /* VC4_CONFIGURATION_BITS */
395 uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
396
397 struct PACKED {
398 uint8_t depth_offset[V3D21_DEPTH_OFFSET_length];
399 uint8_t point_size[V3D21_POINT_SIZE_length];
400 uint8_t line_width[V3D21_LINE_WIDTH_length];
401 } packed;
402
403 /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
404 uint32_t tile_raster_order_flags;
405 };
406
407 struct vc4_depth_stencil_alpha_state {
408 struct pipe_depth_stencil_alpha_state base;
409
410 /* VC4_CONFIGURATION_BITS */
411 uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
412
413 /** Uniforms for stencil state.
414 *
415 * Index 0 is either the front config, or the front-and-back config.
416 * Index 1 is the back config if doing separate back stencil.
417 * Index 2 is the writemask config if it's not a common mask value.
418 */
419 uint32_t stencil_uniforms[3];
420 };
421
422 #define perf_debug(...) do { \
423 if (VC4_DBG(PERF)) \
424 fprintf(stderr, __VA_ARGS__); \
425 if (unlikely(vc4->base.debug.debug_message)) \
426 util_debug_message(&vc4->base.debug, PERF_INFO, __VA_ARGS__); \
427 } while (0)
428
429 static inline struct vc4_context *
vc4_context(struct pipe_context * pcontext)430 vc4_context(struct pipe_context *pcontext)
431 {
432 return (struct vc4_context *)pcontext;
433 }
434
435 static inline struct vc4_sampler_view *
vc4_sampler_view(struct pipe_sampler_view * psview)436 vc4_sampler_view(struct pipe_sampler_view *psview)
437 {
438 return (struct vc4_sampler_view *)psview;
439 }
440
441 static inline struct vc4_sampler_state *
vc4_sampler_state(struct pipe_sampler_state * psampler)442 vc4_sampler_state(struct pipe_sampler_state *psampler)
443 {
444 return (struct vc4_sampler_state *)psampler;
445 }
446
447 int vc4_get_driver_query_group_info(struct pipe_screen *pscreen,
448 unsigned index,
449 struct pipe_driver_query_group_info *info);
450 int vc4_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
451 struct pipe_driver_query_info *info);
452
453 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
454 void *priv, unsigned flags);
455 void vc4_draw_init(struct pipe_context *pctx);
456 void vc4_state_init(struct pipe_context *pctx);
457 void vc4_program_init(struct pipe_context *pctx);
458 void vc4_program_fini(struct pipe_context *pctx);
459 void vc4_query_init(struct pipe_context *pctx);
460 void vc4_simulator_init(struct vc4_screen *screen);
461 void vc4_simulator_destroy(struct vc4_screen *screen);
462 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
463 void vc4_simulator_open_from_handle(int fd, int handle, uint32_t size);
464
465 static inline int
vc4_ioctl(int fd,unsigned long request,void * arg)466 vc4_ioctl(int fd, unsigned long request, void *arg)
467 {
468 #ifdef USE_VC4_SIMULATOR
469 return vc4_simulator_ioctl(fd, request, arg);
470 #else
471 return drmIoctl(fd, request, arg);
472 #endif
473 }
474
475 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
476 void vc4_write_uniforms(struct vc4_context *vc4,
477 struct vc4_compiled_shader *shader,
478 struct vc4_constbuf_stateobj *cb,
479 struct vc4_texture_stateobj *texstate);
480
481 void vc4_flush(struct pipe_context *pctx);
482 int vc4_job_init(struct vc4_context *vc4);
483 int vc4_fence_context_init(struct vc4_context *vc4);
484 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
485 struct pipe_surface *cbuf,
486 struct pipe_surface *zsbuf);
487 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
488
489 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
490 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
491 struct pipe_resource *prsc);
492 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
493 struct pipe_resource *prsc);
494 void vc4_emit_state(struct pipe_context *pctx);
495 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
496 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
497 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
498
499 bool vc4_rt_format_supported(enum pipe_format f);
500 bool vc4_rt_format_is_565(enum pipe_format f);
501 bool vc4_tex_format_supported(enum pipe_format f);
502 uint8_t vc4_get_tex_format(enum pipe_format f);
503 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
504 void vc4_init_query_functions(struct vc4_context *vc4);
505 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
506 void vc4_blitter_save(struct vc4_context *vc4);
507 #endif /* VC4_CONTEXT_H */
508