1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __TIMESTAMP_SERIALIZED_H__ 4 #define __TIMESTAMP_SERIALIZED_H__ 5 6 #include <stdint.h> 7 #include <commonlib/bsd/helpers.h> 8 9 struct timestamp_entry { 10 uint32_t entry_id; 11 int64_t entry_stamp; 12 } __packed; 13 14 struct timestamp_table { 15 uint64_t base_time; 16 uint16_t max_entries; 17 uint16_t tick_freq_mhz; 18 uint32_t num_entries; 19 struct timestamp_entry entries[]; /* Variable number of entries */ 20 } __packed; 21 22 enum timestamp_id { 23 TS_ROMSTAGE_START = 1, 24 TS_INITRAM_START = 2, 25 TS_INITRAM_END = 3, 26 TS_ROMSTAGE_END = 4, 27 TS_VBOOT_START = 5, 28 TS_VBOOT_END = 6, 29 TS_COPYRAM_START = 8, 30 TS_COPYRAM_END = 9, 31 TS_RAMSTAGE_START = 10, 32 TS_BOOTBLOCK_START = 11, 33 TS_BOOTBLOCK_END = 12, 34 TS_COPYROM_START = 13, 35 TS_COPYROM_END = 14, 36 TS_ULZMA_START = 15, 37 TS_ULZMA_END = 16, 38 TS_ULZ4F_START = 17, 39 TS_ULZ4F_END = 18, 40 TS_DEVICE_ENUMERATE = 30, 41 TS_DEVICE_CONFIGURE = 40, 42 TS_DEVICE_ENABLE = 50, 43 TS_DEVICE_INITIALIZE = 60, 44 TS_OPROM_INITIALIZE = 65, 45 TS_OPROM_COPY_END = 66, 46 TS_OPROM_END = 67, 47 TS_DEVICE_DONE = 70, 48 TS_CBMEM_POST = 75, 49 TS_WRITE_TABLES = 80, 50 TS_FINALIZE_CHIPS = 85, 51 TS_LOAD_PAYLOAD = 90, 52 TS_ACPI_WAKE_JUMP = 98, 53 TS_SELFBOOT_JUMP = 99, 54 TS_POSTCAR_START = 100, 55 TS_POSTCAR_END = 101, 56 TS_DELAY_START = 110, 57 TS_DELAY_END = 111, 58 TS_READ_UCODE_START = 112, 59 TS_READ_UCODE_END = 113, 60 TS_ELOG_INIT_START = 114, 61 TS_ELOG_INIT_END = 115, 62 63 /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ 64 TS_COPYVER_START = 501, 65 TS_COPYVER_END = 502, 66 TS_TPMINIT_START = 503, 67 TS_TPMINIT_END = 504, 68 TS_VERIFY_SLOT_START = 505, 69 TS_VERIFY_SLOT_END = 506, 70 TS_HASH_BODY_START = 507, 71 TS_LOADING_END = 508, 72 TS_HASHING_END = 509, 73 TS_HASH_BODY_END = 510, 74 TS_TPMPCR_START = 511, 75 TS_TPMPCR_END = 512, 76 TS_TPMLOCK_START = 513, 77 TS_TPMLOCK_END = 514, 78 TS_EC_SYNC_START = 515, 79 TS_EC_HASH_READY = 516, 80 TS_EC_POWER_LIMIT_WAIT = 517, 81 TS_EC_SYNC_END = 518, 82 TS_COPYVPD_START = 550, 83 TS_COPYVPD_RO_END = 551, 84 TS_COPYVPD_RW_END = 552, 85 TS_TPM_ENABLE_UPDATE_START = 553, 86 TS_TPM_ENABLE_UPDATE_END = 554, 87 TS_ESOL_START = 555, 88 TS_ESOL_END = 556, 89 90 /* 900-940 reserved for vendorcode extensions (900-940: AMD) */ 91 TS_AGESA_INIT_RESET_START = 900, 92 TS_AGESA_INIT_RESET_END = 901, 93 TS_AGESA_INIT_EARLY_START = 902, 94 TS_AGESA_INIT_EARLY_END = 903, 95 TS_AGESA_INIT_POST_START = 904, 96 TS_AGESA_INIT_POST_END = 905, 97 TS_AGESA_INIT_ENV_START = 906, 98 TS_AGESA_INIT_ENV_END = 907, 99 TS_AGESA_INIT_MID_START = 908, 100 TS_AGESA_INIT_MID_END = 909, 101 TS_AGESA_INIT_LATE_START = 910, 102 TS_AGESA_INIT_LATE_END = 911, 103 TS_AGESA_INIT_RTB_START = 912, 104 TS_AGESA_INIT_RTB_END = 913, 105 TS_AGESA_INIT_RESUME_START = 914, 106 TS_AGESA_INIT_RESUME_END = 915, 107 TS_AGESA_S3_LATE_START = 916, 108 TS_AGESA_S3_LATE_END = 917, 109 TS_AGESA_S3_FINAL_START = 918, 110 TS_AGESA_S3_FINAL_END = 919, 111 TS_AMD_APOB_READ_START = 920, 112 TS_AMD_APOB_ERASE_START = 921, 113 TS_AMD_APOB_WRITE_START = 922, 114 TS_AMD_APOB_END = 923, 115 116 /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ 117 TS_ME_INFORM_DRAM_START = 940, 118 TS_ME_INFORM_DRAM_END = 941, 119 TS_ME_END_OF_POST_START = 942, 120 TS_ME_END_OF_POST_END = 943, 121 TS_ME_BOOT_STALL_END = 944, 122 TS_ME_ICC_CONFIG_START = 945, 123 TS_ME_HOST_BOOT_PREP_END = 946, 124 TS_ME_RECEIVED_CRDA_FROM_PMC = 947, 125 TS_CSE_FW_SYNC_START = 948, 126 TS_CSE_FW_SYNC_END = 949, 127 128 /* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */ 129 TS_FSP_MEMORY_INIT_START = 950, 130 TS_FSP_MEMORY_INIT_END = 951, 131 TS_FSP_TEMP_RAM_EXIT_START = 952, 132 TS_FSP_TEMP_RAM_EXIT_END = 953, 133 TS_FSP_SILICON_INIT_START = 954, 134 TS_FSP_SILICON_INIT_END = 955, 135 TS_FSP_ENUMERATE_START = 956, 136 TS_FSP_ENUMERATE_END = 957, 137 TS_FSP_FINALIZE_START = 958, 138 TS_FSP_FINALIZE_END = 959, 139 TS_FSP_END_OF_FIRMWARE_START = 960, 140 TS_FSP_END_OF_FIRMWARE_END = 961, 141 TS_FSP_MULTI_PHASE_SI_INIT_START = 962, 142 TS_FSP_MULTI_PHASE_SI_INIT_END = 963, 143 TS_FSP_MULTI_PHASE_MEM_INIT_START = 964, 144 TS_FSP_MULTI_PHASE_MEM_INIT_END = 965, 145 TS_FSP_MEMORY_INIT_LOAD = 970, 146 TS_FSP_SILICON_INIT_LOAD = 971, 147 148 /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ 149 TS_ME_ROM_START = 990, 150 TS_ISSE_DMU_LOAD_END = 991, 151 152 /* 1000+ reserved for payloads */ 153 154 /* 1000-1200: Depthcharge */ 155 TS_DC_START = 1000, 156 157 TS_RO_PARAMS_INIT = 1001, 158 TS_RO_VB_INIT = 1002, 159 TS_RO_VB_SELECT_FIRMWARE = 1003, 160 TS_RO_VB_SELECT_AND_LOAD_KERNEL = 1004, 161 162 TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010, 163 164 TS_VB_SELECT_AND_LOAD_KERNEL = 1020, 165 TS_VB_EC_VBOOT_DONE = 1030, 166 TS_VB_STORAGE_INIT_DONE = 1040, 167 TS_VB_READ_KERNEL_DONE = 1050, 168 TS_VB_AUXFW_SYNC_DONE = 1060, 169 TS_VB_VBOOT_DONE = 1100, 170 171 TS_KERNEL_START = 1101, 172 TS_KERNEL_DECOMPRESSION = 1102, 173 174 /* 1200-1300: ChromeOS Hypervisor */ 175 TS_CRHV_BOOT = 1200, 176 TS_CRHV_PLATFORM_INIT = 1201, 177 TS_CRHV_SERVICES_STARTED = 1202, 178 TS_CRHV_HW_PASSTHROUGH_START = 1203, 179 TS_CRHV_HW_PASSTHROUGH_END = 1204, 180 TS_CRHV_PSTORE_START = 1205, 181 TS_CRHV_PSTORE_END = 1206, 182 TS_CRHV_VMM_START = 1207, 183 }; 184 185 #define TS_NAME_DEF(id, id_end, desc) {(id), (id_end), STRINGIFY(id), (desc)} 186 187 static const struct timestamp_id_to_name { 188 uint32_t id; 189 uint32_t id_end; 190 const char *enum_name; 191 const char *name; 192 } timestamp_ids[] = { 193 /* Marker to report base_time. */ 194 {0, 0, "TS_START", "1st timestamp"}, 195 TS_NAME_DEF(TS_ROMSTAGE_START, TS_ROMSTAGE_END, "start of romstage"), 196 TS_NAME_DEF(TS_INITRAM_START, TS_INITRAM_END, "before RAM initialization"), 197 TS_NAME_DEF(TS_INITRAM_END, 0, "after RAM initialization"), 198 TS_NAME_DEF(TS_ROMSTAGE_END, 0, "end of romstage"), 199 TS_NAME_DEF(TS_VBOOT_START, TS_VBOOT_END, "start of verified boot"), 200 TS_NAME_DEF(TS_VBOOT_END, 0, "end of verified boot"), 201 TS_NAME_DEF(TS_COPYRAM_START, TS_COPYRAM_END, "starting to load ramstage"), 202 TS_NAME_DEF(TS_COPYRAM_END, 0, "finished loading ramstage"), 203 TS_NAME_DEF(TS_RAMSTAGE_START, 0, "start of ramstage"), 204 TS_NAME_DEF(TS_BOOTBLOCK_START, TS_BOOTBLOCK_END, "start of bootblock"), 205 TS_NAME_DEF(TS_BOOTBLOCK_END, 0, "end of bootblock"), 206 TS_NAME_DEF(TS_COPYROM_START, TS_COPYROM_END, "starting to load romstage"), 207 TS_NAME_DEF(TS_COPYROM_END, 0, "finished loading romstage"), 208 /* 209 * "ignore for x86": On platforms with memory-mapped flash, it's 210 * impossible to separate loading times from decompression times because 211 * the flash accesses happen in the background as the decompression is 212 * running. So it makes more sense to consider the total loading + 213 * decompression time by looking at the timestamps before and after the 214 * decompression timestamps. 215 */ 216 TS_NAME_DEF(TS_ULZMA_START, TS_ULZMA_END, "starting LZMA decompress (ignore for x86)"), 217 TS_NAME_DEF(TS_ULZMA_END, 0, "finished LZMA decompress (ignore for x86)"), 218 TS_NAME_DEF(TS_ULZ4F_START, TS_ULZ4F_END, "starting LZ4 decompress (ignore for x86)"), 219 TS_NAME_DEF(TS_ULZ4F_END, 0, "finished LZ4 decompress (ignore for x86)"), 220 TS_NAME_DEF(TS_DEVICE_ENUMERATE, TS_DEVICE_CONFIGURE, "device enumeration"), 221 TS_NAME_DEF(TS_DEVICE_CONFIGURE, TS_DEVICE_ENABLE, "device configuration"), 222 TS_NAME_DEF(TS_DEVICE_ENABLE, TS_DEVICE_INITIALIZE, "device enable"), 223 TS_NAME_DEF(TS_DEVICE_INITIALIZE, TS_DEVICE_DONE, "device initialization"), 224 TS_NAME_DEF(TS_OPROM_INITIALIZE, TS_OPROM_END, "Option ROM initialization"), 225 TS_NAME_DEF(TS_OPROM_COPY_END, 0, "Option ROM copy done"), 226 TS_NAME_DEF(TS_OPROM_END, 0, "Option ROM run done"), 227 TS_NAME_DEF(TS_DEVICE_DONE, 0, "device setup done"), 228 TS_NAME_DEF(TS_CBMEM_POST, 0, "cbmem post"), 229 TS_NAME_DEF(TS_WRITE_TABLES, 0, "write tables"), 230 TS_NAME_DEF(TS_FINALIZE_CHIPS, 0, "finalize chips"), 231 TS_NAME_DEF(TS_LOAD_PAYLOAD, 0, "starting to load payload"), 232 TS_NAME_DEF(TS_ACPI_WAKE_JUMP, 0, "ACPI wake jump"), 233 TS_NAME_DEF(TS_SELFBOOT_JUMP, 0, "selfboot jump"), 234 TS_NAME_DEF(TS_POSTCAR_START, TS_POSTCAR_END, "start of postcar"), 235 TS_NAME_DEF(TS_POSTCAR_END, 0, "end of postcar"), 236 TS_NAME_DEF(TS_DELAY_START, TS_DELAY_END, "Forced delay start"), 237 TS_NAME_DEF(TS_DELAY_END, 0, "Forced delay end"), 238 TS_NAME_DEF(TS_READ_UCODE_START, TS_READ_UCODE_END, "started reading uCode"), 239 TS_NAME_DEF(TS_READ_UCODE_END, 0, "finished reading uCode"), 240 TS_NAME_DEF(TS_ELOG_INIT_START, TS_ELOG_INIT_END, "started elog init"), 241 TS_NAME_DEF(TS_ELOG_INIT_END, 0, "finished elog init"), 242 243 /* Google related timestamps */ 244 TS_NAME_DEF(TS_COPYVER_START, TS_COPYVER_START, "starting to load verstage"), 245 TS_NAME_DEF(TS_COPYVER_END, 0, "finished loading verstage"), 246 TS_NAME_DEF(TS_TPMINIT_START, TS_TPMINIT_END, "starting to initialize TPM"), 247 TS_NAME_DEF(TS_TPMINIT_END, 0, "finished TPM initialization"), 248 TS_NAME_DEF(TS_VERIFY_SLOT_START, TS_VERIFY_SLOT_END, 249 "starting to verify keyblock/preamble (RSA)"), 250 TS_NAME_DEF(TS_VERIFY_SLOT_END, 0, "finished verifying keyblock/preamble (RSA)"), 251 TS_NAME_DEF(TS_HASH_BODY_START, TS_HASH_BODY_END, 252 "starting to verify body (load+SHA2+RSA) "), 253 TS_NAME_DEF(TS_LOADING_END, 0, "finished loading body"), 254 TS_NAME_DEF(TS_HASHING_END, 0, "finished calculating body hash (SHA2)"), 255 TS_NAME_DEF(TS_HASH_BODY_END, 0, "finished verifying body signature (RSA)"), 256 TS_NAME_DEF(TS_TPMPCR_START, TS_TPMPCR_END, "starting TPM PCR extend"), 257 TS_NAME_DEF(TS_TPMPCR_END, 0, "finished TPM PCR extend"), 258 TS_NAME_DEF(TS_TPMLOCK_START, TS_TPMLOCK_END, "starting locking TPM"), 259 TS_NAME_DEF(TS_TPMLOCK_END, 0, "finished locking TPM"), 260 TS_NAME_DEF(TS_EC_SYNC_START, TS_EC_SYNC_END, "starting EC software sync"), 261 TS_NAME_DEF(TS_EC_HASH_READY, 0, "EC vboot hash ready"), 262 TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, 0, "waiting for EC to allow higher power draw"), 263 TS_NAME_DEF(TS_EC_SYNC_END, 0, "finished EC software sync"), 264 TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load ChromeOS VPD"), 265 TS_NAME_DEF(TS_COPYVPD_RO_END, TS_COPYVPD_RW_END, 266 "finished loading ChromeOS VPD (RO)"), 267 TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading ChromeOS VPD (RW)"), 268 TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END, 269 "started TPM enable update"), 270 TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"), 271 TS_NAME_DEF(TS_ESOL_START, 0, "started early sign-off life (eSOL) notification"), 272 TS_NAME_DEF(TS_ESOL_END, 0, "finished early sign-off life (eSOL) notification"), 273 274 /* AMD related timestamps */ 275 TS_NAME_DEF(TS_AGESA_INIT_RESET_START, TS_AGESA_INIT_RESET_END, "calling AmdInitReset"), 276 TS_NAME_DEF(TS_AGESA_INIT_RESET_END, 0, "back from AmdInitReset"), 277 TS_NAME_DEF(TS_AGESA_INIT_EARLY_START, TS_AGESA_INIT_EARLY_END, "calling AmdInitEarly"), 278 TS_NAME_DEF(TS_AGESA_INIT_EARLY_END, 0, "back from AmdInitEarly"), 279 TS_NAME_DEF(TS_AGESA_INIT_POST_START, TS_AGESA_INIT_POST_END, "calling AmdInitPost"), 280 TS_NAME_DEF(TS_AGESA_INIT_POST_END, 0, "back from AmdInitPost"), 281 TS_NAME_DEF(TS_AGESA_INIT_ENV_START, TS_AGESA_INIT_ENV_END, "calling AmdInitEnv"), 282 TS_NAME_DEF(TS_AGESA_INIT_ENV_END, 0, "back from AmdInitEnv"), 283 TS_NAME_DEF(TS_AGESA_INIT_MID_START, TS_AGESA_INIT_MID_END, "calling AmdInitMid"), 284 TS_NAME_DEF(TS_AGESA_INIT_MID_END, 0, "back from AmdInitMid"), 285 TS_NAME_DEF(TS_AGESA_INIT_LATE_START, TS_AGESA_INIT_LATE_END, "calling AmdInitLate"), 286 TS_NAME_DEF(TS_AGESA_INIT_LATE_END, 0, "back from AmdInitLate"), 287 TS_NAME_DEF(TS_AGESA_INIT_RTB_START, TS_AGESA_INIT_RTB_END, 288 "calling AmdInitRtb/AmdS3Save"), 289 TS_NAME_DEF(TS_AGESA_INIT_RTB_END, 0, "back from AmdInitRtb/AmdS3Save"), 290 TS_NAME_DEF(TS_AGESA_INIT_RESUME_START, TS_AGESA_INIT_RESUME_END, 291 "calling AmdInitResume"), 292 TS_NAME_DEF(TS_AGESA_INIT_RESUME_END, 0, "back from AmdInitResume"), 293 TS_NAME_DEF(TS_AGESA_S3_LATE_START, TS_AGESA_S3_LATE_END, "calling AmdS3LateRestore"), 294 TS_NAME_DEF(TS_AGESA_S3_LATE_END, 0, "back from AmdS3LateRestore"), 295 TS_NAME_DEF(TS_AGESA_S3_FINAL_START, TS_AGESA_S3_FINAL_END, 296 "calling AmdS3FinalRestore"), 297 TS_NAME_DEF(TS_AGESA_S3_FINAL_END, 0, "back from AmdS3FinalRestore"), 298 TS_NAME_DEF(TS_AMD_APOB_READ_START, TS_AMD_APOB_END, "starting APOB read"), 299 TS_NAME_DEF(TS_AMD_APOB_ERASE_START, TS_AMD_APOB_WRITE_START, "starting APOB erase"), 300 TS_NAME_DEF(TS_AMD_APOB_WRITE_START, TS_AMD_APOB_END, "starting APOB write"), 301 TS_NAME_DEF(TS_AMD_APOB_END, 0, "finished APOB"), 302 303 /* Intel ME related timestamps */ 304 TS_NAME_DEF(TS_ME_INFORM_DRAM_START, TS_ME_INFORM_DRAM_END, 305 "waiting for ME acknowledgment of raminit"), 306 TS_NAME_DEF(TS_ME_INFORM_DRAM_END, 0, "finished waiting for ME response"), 307 TS_NAME_DEF(TS_ME_END_OF_POST_START, TS_ME_END_OF_POST_END, "before sending EOP to ME"), 308 TS_NAME_DEF(TS_ME_END_OF_POST_END, 0, "after sending EOP to ME"), 309 TS_NAME_DEF(TS_ME_BOOT_STALL_END, 0, "CSE sent 'Boot Stall Done' to PMC"), 310 TS_NAME_DEF(TS_ME_ICC_CONFIG_START, 0, "CSE started to handle ICC configuration"), 311 TS_NAME_DEF(TS_ME_HOST_BOOT_PREP_END, 0, "CSE sent 'Host BIOS Prep Done' to PMC"), 312 TS_NAME_DEF(TS_ME_RECEIVED_CRDA_FROM_PMC, 0, 313 "CSE received 'CPU Reset Done Ack sent' from PMC"), 314 TS_NAME_DEF(TS_CSE_FW_SYNC_START, TS_CSE_FW_SYNC_END, "starting CSE firmware sync"), 315 TS_NAME_DEF(TS_CSE_FW_SYNC_END, 0, "finished CSE firmware sync"), 316 317 /* FSP related timestamps */ 318 TS_NAME_DEF(TS_FSP_MEMORY_INIT_START, TS_FSP_MEMORY_INIT_END, "calling FspMemoryInit"), 319 TS_NAME_DEF(TS_FSP_MEMORY_INIT_END, 0, "returning from FspMemoryInit"), 320 TS_NAME_DEF(TS_FSP_TEMP_RAM_EXIT_START, TS_FSP_TEMP_RAM_EXIT_END, 321 "calling FspTempRamExit"), 322 TS_NAME_DEF(TS_FSP_TEMP_RAM_EXIT_END, 0, "returning from FspTempRamExit"), 323 TS_NAME_DEF(TS_FSP_SILICON_INIT_START, TS_FSP_SILICON_INIT_END, 324 "calling FspSiliconInit"), 325 TS_NAME_DEF(TS_FSP_SILICON_INIT_END, 0, "returning from FspSiliconInit"), 326 TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_START, TS_FSP_MULTI_PHASE_SI_INIT_END, 327 "calling FspMultiPhaseSiInit"), 328 TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_END, 0, "returning from FspMultiPhaseSiInit"), 329 TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_START, TS_FSP_MULTI_PHASE_MEM_INIT_END, 330 "calling FspMultiPhaseMemInit"), 331 TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_END, 0, "returning from FspMultiPhaseMemInit"), 332 TS_NAME_DEF(TS_FSP_ENUMERATE_START, TS_FSP_ENUMERATE_END, 333 "calling FspNotify(AfterPciEnumeration)"), 334 TS_NAME_DEF(TS_FSP_ENUMERATE_END, 0, "returning from FspNotify(AfterPciEnumeration)"), 335 TS_NAME_DEF(TS_FSP_FINALIZE_START, TS_FSP_FINALIZE_END, 336 "calling FspNotify(ReadyToBoot)"), 337 TS_NAME_DEF(TS_FSP_FINALIZE_END, 0, "returning from FspNotify(ReadyToBoot)"), 338 TS_NAME_DEF(TS_FSP_END_OF_FIRMWARE_START, TS_FSP_END_OF_FIRMWARE_END, 339 "calling FspNotify(EndOfFirmware)"), 340 TS_NAME_DEF(TS_FSP_END_OF_FIRMWARE_END, 0, "returning from FspNotify(EndOfFirmware)"), 341 TS_NAME_DEF(TS_FSP_MEMORY_INIT_LOAD, 0, "loading FSP-M"), 342 TS_NAME_DEF(TS_FSP_SILICON_INIT_LOAD, 0, "loading FSP-S"), 343 344 /* Intel ME continued */ 345 TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"), 346 TS_NAME_DEF(TS_ISSE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), 347 348 /* Depthcharge entry timestamp */ 349 TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"), 350 351 TS_NAME_DEF(TS_RO_PARAMS_INIT, 0, "RO parameter init"), 352 TS_NAME_DEF(TS_RO_VB_INIT, 0, "RO vboot init"), 353 TS_NAME_DEF(TS_RO_VB_SELECT_FIRMWARE, 0, "RO vboot select firmware"), 354 TS_NAME_DEF(TS_RO_VB_SELECT_AND_LOAD_KERNEL, 0, "RO vboot select&load kernel"), 355 356 TS_NAME_DEF(TS_RW_VB_SELECT_AND_LOAD_KERNEL, 0, "RW vboot select&load kernel"), 357 358 TS_NAME_DEF(TS_VB_SELECT_AND_LOAD_KERNEL, 0, "vboot select&load kernel"), 359 TS_NAME_DEF(TS_VB_EC_VBOOT_DONE, 0, "finished EC verification"), 360 TS_NAME_DEF(TS_VB_STORAGE_INIT_DONE, 0, "finished storage device initialization"), 361 TS_NAME_DEF(TS_VB_READ_KERNEL_DONE, 0, "finished reading kernel from disk"), 362 TS_NAME_DEF(TS_VB_AUXFW_SYNC_DONE, 0, "finished AuxFW Sync"), 363 TS_NAME_DEF(TS_VB_VBOOT_DONE, 0, "finished vboot kernel verification"), 364 365 TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"), 366 TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"), 367 368 /* ChromeOS hypervisor */ 369 TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"), 370 TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"), 371 TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"), 372 TS_NAME_DEF(TS_CRHV_HW_PASSTHROUGH_START, TS_CRHV_HW_PASSTHROUGH_END, 373 "hypervisor hardware passthrough setup start"), 374 TS_NAME_DEF(TS_CRHV_HW_PASSTHROUGH_END, 0, 375 "hypervisor hardware passthrough setup complete"), 376 TS_NAME_DEF(TS_CRHV_PSTORE_START, TS_CRHV_PSTORE_END, "hypervisor pstore init start"), 377 TS_NAME_DEF(TS_CRHV_PSTORE_END, 0, "hypervisor pstore init complete"), 378 TS_NAME_DEF(TS_CRHV_VMM_START, 0, "hypervisor OS VMM start"), 379 }; 380 381 #endif 382