1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #include "tu_cmd_buffer.h"
11
12 #include "vk_common_entrypoints.h"
13 #include "vk_render_pass.h"
14 #include "vk_util.h"
15
16 #include "tu_buffer.h"
17 #include "tu_clear_blit.h"
18 #include "tu_cs.h"
19 #include "tu_event.h"
20 #include "tu_image.h"
21 #include "tu_tracepoints.h"
22
23 #include "common/freedreno_gpu_event.h"
24 #include "common/freedreno_lrz.h"
25
26 static void
tu_clone_trace_range(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct u_trace_iterator begin,struct u_trace_iterator end)27 tu_clone_trace_range(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
28 struct u_trace_iterator begin, struct u_trace_iterator end)
29 {
30 if (u_trace_iterator_equal(begin, end))
31 return;
32
33 tu_cs_emit_wfi(cs);
34 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
35 u_trace_clone_append(begin, end, &cmd->trace, cs, tu_copy_buffer);
36 }
37
38 static void
tu_clone_trace(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct u_trace * trace)39 tu_clone_trace(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
40 struct u_trace *trace)
41 {
42 tu_clone_trace_range(cmd, cs, u_trace_begin_iterator(trace),
43 u_trace_end_iterator(trace));
44 }
45
46 template <chip CHIP>
47 static void
tu_emit_raw_event_write(struct tu_cmd_buffer * cmd,struct tu_cs * cs,enum vgt_event_type event,bool needs_seqno)48 tu_emit_raw_event_write(struct tu_cmd_buffer *cmd,
49 struct tu_cs *cs,
50 enum vgt_event_type event,
51 bool needs_seqno)
52 {
53 if (CHIP == A6XX) {
54 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, needs_seqno ? 4 : 1);
55 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
56 } else {
57 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, needs_seqno ? 4 : 1);
58 tu_cs_emit(cs,
59 CP_EVENT_WRITE7_0(.event = event,
60 .write_src = EV_WRITE_USER_32B,
61 .write_dst = EV_DST_RAM,
62 .write_enabled = needs_seqno).value);
63 }
64
65 if (needs_seqno) {
66 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy));
67 tu_cs_emit(cs, 0);
68 }
69 }
70
71 template <chip CHIP>
72 void
tu_emit_event_write(struct tu_cmd_buffer * cmd,struct tu_cs * cs,enum fd_gpu_event event)73 tu_emit_event_write(struct tu_cmd_buffer *cmd,
74 struct tu_cs *cs,
75 enum fd_gpu_event event)
76 {
77 struct fd_gpu_event_info event_info = fd_gpu_events<CHIP>[event];
78 tu_emit_raw_event_write<CHIP>(cmd, cs, event_info.raw_event,
79 event_info.needs_seqno);
80 }
81 TU_GENX(tu_emit_event_write);
82
83 /* Emits the tessfactor address to the top-level CS if it hasn't been already.
84 * Updating this register requires a WFI if outstanding drawing is using it, but
85 * tu6_init_hardware() will have WFIed before we started and no other draws
86 * could be using the tessfactor address yet since we only emit one per cmdbuf.
87 */
88 template <chip CHIP>
89 static void
tu6_lazy_emit_tessfactor_addr(struct tu_cmd_buffer * cmd)90 tu6_lazy_emit_tessfactor_addr(struct tu_cmd_buffer *cmd)
91 {
92 if (cmd->state.tessfactor_addr_set)
93 return;
94
95 tu_cs_emit_regs(&cmd->cs, PC_TESSFACTOR_ADDR(CHIP, .qword = cmd->device->tess_bo->iova));
96 /* Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it. */
97 cmd->state.cache.flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
98 cmd->state.tessfactor_addr_set = true;
99 }
100
101 template <chip CHIP>
102 static void
tu6_lazy_emit_vsc(struct tu_cmd_buffer * cmd,struct tu_cs * cs)103 tu6_lazy_emit_vsc(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
104 {
105 struct tu_device *dev = cmd->device;
106 uint32_t num_vsc_pipes = dev->physical_device->info->num_vsc_pipes;
107
108 /* VSC buffers:
109 * use vsc pitches from the largest values used so far with this device
110 * if there hasn't been overflow, there will already be a scratch bo
111 * allocated for these sizes
112 *
113 * if overflow is detected, the stream size is increased by 2x
114 */
115 mtx_lock(&dev->mutex);
116
117 struct tu6_global *global = dev->global_bo_map;
118
119 uint32_t vsc_draw_overflow = global->vsc_draw_overflow;
120 uint32_t vsc_prim_overflow = global->vsc_prim_overflow;
121
122 if (vsc_draw_overflow >= dev->vsc_draw_strm_pitch)
123 dev->vsc_draw_strm_pitch = (dev->vsc_draw_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
124
125 if (vsc_prim_overflow >= dev->vsc_prim_strm_pitch)
126 dev->vsc_prim_strm_pitch = (dev->vsc_prim_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
127
128 cmd->vsc_prim_strm_pitch = dev->vsc_prim_strm_pitch;
129 cmd->vsc_draw_strm_pitch = dev->vsc_draw_strm_pitch;
130
131 mtx_unlock(&dev->mutex);
132
133 struct tu_bo *vsc_bo;
134 uint32_t size0 = cmd->vsc_prim_strm_pitch * num_vsc_pipes +
135 cmd->vsc_draw_strm_pitch * num_vsc_pipes;
136
137 tu_get_scratch_bo(dev, size0 + num_vsc_pipes * 4, &vsc_bo);
138
139 if (CHIP == A6XX) {
140 tu_cs_emit_regs(cs,
141 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = vsc_bo, .bo_offset = size0));
142 tu_cs_emit_regs(cs,
143 A6XX_VSC_PRIM_STRM_ADDRESS(.bo = vsc_bo));
144 tu_cs_emit_regs(
145 cs, A6XX_VSC_DRAW_STRM_ADDRESS(.bo = vsc_bo,
146 .bo_offset = cmd->vsc_prim_strm_pitch *
147 num_vsc_pipes));
148 } else {
149 tu_cs_emit_pkt7(cs, CP_SET_PSEUDO_REG, 3 * 3);
150 tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(DRAW_STRM_ADDRESS));
151 tu_cs_emit_qw(cs, vsc_bo->iova + cmd->vsc_prim_strm_pitch * num_vsc_pipes);
152 tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(DRAW_STRM_SIZE_ADDRESS));
153 tu_cs_emit_qw(cs, vsc_bo->iova + size0);
154 tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(PRIM_STRM_ADDRESS));
155 tu_cs_emit_qw(cs, vsc_bo->iova);
156 }
157
158 cmd->vsc_initialized = true;
159 }
160
161 template <chip CHIP>
162 static void
tu6_emit_flushes(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,struct tu_cache_state * cache)163 tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer,
164 struct tu_cs *cs,
165 struct tu_cache_state *cache)
166 {
167 BITMASK_ENUM(tu_cmd_flush_bits) flushes = cache->flush_bits;
168 cache->flush_bits = 0;
169
170 if (TU_DEBUG(FLUSHALL))
171 flushes |= TU_CMD_FLAG_ALL_CLEAN | TU_CMD_FLAG_ALL_INVALIDATE;
172
173 if (TU_DEBUG(SYNCDRAW))
174 flushes |= TU_CMD_FLAG_WAIT_MEM_WRITES |
175 TU_CMD_FLAG_WAIT_FOR_IDLE |
176 TU_CMD_FLAG_WAIT_FOR_ME;
177
178 /* Experiments show that invalidating CCU while it still has data in it
179 * doesn't work, so make sure to always flush before invalidating in case
180 * any data remains that hasn't yet been made available through a barrier.
181 * However it does seem to work for UCHE.
182 */
183 if (flushes & (TU_CMD_FLAG_CCU_CLEAN_COLOR |
184 TU_CMD_FLAG_CCU_INVALIDATE_COLOR))
185 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_CLEAN_COLOR);
186 if (flushes & (TU_CMD_FLAG_CCU_CLEAN_DEPTH |
187 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH))
188 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_CLEAN_DEPTH);
189 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_COLOR)
190 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_INVALIDATE_COLOR);
191 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_DEPTH)
192 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_INVALIDATE_DEPTH);
193 if (flushes & TU_CMD_FLAG_CACHE_CLEAN)
194 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CACHE_CLEAN);
195 if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
196 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CACHE_INVALIDATE);
197 if (flushes & TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE) {
198 tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
199 .cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
200 .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,
201 ));
202 }
203 if (CHIP >= A7XX && flushes & TU_CMD_FLAG_BLIT_CACHE_CLEAN)
204 /* On A7XX, blit cache flushes are required to ensure blit writes are visible
205 * via UCHE. This isn't necessary on A6XX, all writes should be visible implictly.
206 */
207 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_CLEAN_BLIT_CACHE);
208 if (CHIP >= A7XX && (flushes & TU_CMD_FLAG_CCHE_INVALIDATE) &&
209 /* Invalidating UCHE seems to also invalidate CCHE */
210 !(flushes & TU_CMD_FLAG_CACHE_INVALIDATE))
211 tu_cs_emit_pkt7(cs, CP_CCHE_INVALIDATE, 0);
212 if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES)
213 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
214 if (flushes & TU_CMD_FLAG_WAIT_FOR_IDLE)
215 tu_cs_emit_wfi(cs);
216 if (flushes & TU_CMD_FLAG_WAIT_FOR_ME)
217 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
218 }
219
220 /* "Normal" cache flushes outside the renderpass, that don't require any special handling */
221 template <chip CHIP>
222 void
tu_emit_cache_flush(struct tu_cmd_buffer * cmd_buffer)223 tu_emit_cache_flush(struct tu_cmd_buffer *cmd_buffer)
224 {
225 tu6_emit_flushes<CHIP>(cmd_buffer, &cmd_buffer->cs, &cmd_buffer->state.cache);
226 }
227 TU_GENX(tu_emit_cache_flush);
228
229 /* Renderpass cache flushes inside the draw_cs */
230 template <chip CHIP>
231 void
tu_emit_cache_flush_renderpass(struct tu_cmd_buffer * cmd_buffer)232 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer)
233 {
234 if (!cmd_buffer->state.renderpass_cache.flush_bits &&
235 likely(!tu_env.debug))
236 return;
237 tu6_emit_flushes<CHIP>(cmd_buffer, &cmd_buffer->draw_cs,
238 &cmd_buffer->state.renderpass_cache);
239 }
240 TU_GENX(tu_emit_cache_flush_renderpass);
241
242 template <chip CHIP>
243 static void
emit_rb_ccu_cntl(struct tu_cs * cs,struct tu_device * dev,bool gmem)244 emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem)
245 {
246 /* The CCUs are a cache that allocates memory from GMEM while facilitating
247 * framebuffer caching for sysmem rendering. The CCU is split into two parts,
248 * one for color and one for depth. The size and offset of these in GMEM can
249 * be configured separately.
250 *
251 * The most common configuration for the CCU is to occupy as much as possible
252 * of GMEM (CACHE_SIZE_FULL) during sysmem rendering as GMEM is unused. On
253 * the other hand, when rendering to GMEM, the CCUs can be left enabled at
254 * any configuration as they don't interfere with GMEM rendering and only
255 * overwrite GMEM when sysmem operations are performed.
256 *
257 * The vast majority of GMEM rendering doesn't need any sysmem operations
258 * but there are some cases where it is required. For example, when the
259 * framebuffer isn't aligned to the tile size or with certain MSAA resolves.
260 *
261 * To correctly handle these cases, we need to be able to switch between
262 * sysmem and GMEM rendering. We do this by allocating a carveout at the
263 * end of GMEM for the color CCU (as none of these operations are depth)
264 * which the color CCU offset is set to and the GMEM size available to the
265 * GMEM layout calculations is adjusted accordingly.
266 */
267 uint32_t color_offset = gmem ? dev->physical_device->ccu_offset_gmem
268 : dev->physical_device->ccu_offset_bypass;
269
270 uint32_t color_offset_hi = color_offset >> 21;
271 color_offset &= 0x1fffff;
272
273 uint32_t depth_offset = gmem ? 0
274 : dev->physical_device->ccu_depth_offset_bypass;
275
276 uint32_t depth_offset_hi = depth_offset >> 21;
277 depth_offset &= 0x1fffff;
278
279 enum a6xx_ccu_cache_size color_cache_size = !gmem ? CCU_CACHE_SIZE_FULL : !gmem ? CCU_CACHE_SIZE_FULL :
280 (a6xx_ccu_cache_size)(dev->physical_device->info->a6xx.gmem_ccu_color_cache_fraction);
281
282 if (CHIP == A7XX) {
283 tu_cs_emit_regs(cs, A7XX_RB_CCU_CNTL2(
284 .depth_offset_hi = depth_offset_hi,
285 .color_offset_hi = color_offset_hi,
286 .depth_cache_size = CCU_CACHE_SIZE_FULL,
287 .depth_offset = depth_offset,
288 .color_cache_size = color_cache_size,
289 .color_offset = color_offset
290 ));
291
292 if (dev->physical_device->info->a7xx.has_gmem_vpc_attr_buf) {
293 tu_cs_emit_regs(cs,
294 A7XX_VPC_ATTR_BUF_SIZE_GMEM(
295 .size_gmem =
296 gmem ? dev->physical_device->vpc_attr_buf_size_gmem
297 : dev->physical_device->vpc_attr_buf_size_bypass),
298 A7XX_VPC_ATTR_BUF_BASE_GMEM(
299 .base_gmem =
300 gmem ? dev->physical_device->vpc_attr_buf_offset_gmem
301 : dev->physical_device->vpc_attr_buf_offset_bypass), );
302 tu_cs_emit_regs(cs,
303 A7XX_PC_ATTR_BUF_SIZE_GMEM(
304 .size_gmem =
305 gmem ? dev->physical_device->vpc_attr_buf_size_gmem
306 : dev->physical_device->vpc_attr_buf_size_bypass), );
307 }
308 } else {
309 tu_cs_emit_regs(cs, RB_CCU_CNTL(CHIP,
310 .gmem_fast_clear_disable =
311 !dev->physical_device->info->a6xx.has_gmem_fast_clear,
312 .concurrent_resolve =
313 dev->physical_device->info->a6xx.concurrent_resolve,
314 .depth_offset_hi = 0,
315 .color_offset_hi = color_offset_hi,
316 .depth_cache_size = CCU_CACHE_SIZE_FULL,
317 .depth_offset = 0,
318 .color_cache_size = color_cache_size,
319 .color_offset = color_offset
320 ));
321 }
322 }
323
324 /* Cache flushes for things that use the color/depth read/write path (i.e.
325 * blits and draws). This deals with changing CCU state as well as the usual
326 * cache flushing.
327 */
328 template <chip CHIP>
329 void
tu_emit_cache_flush_ccu(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,enum tu_cmd_ccu_state ccu_state)330 tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
331 struct tu_cs *cs,
332 enum tu_cmd_ccu_state ccu_state)
333 {
334 assert(ccu_state != TU_CMD_CCU_UNKNOWN);
335 /* It's unsafe to flush inside condition because we clear flush_bits */
336 assert(!cs->cond_stack_depth);
337
338 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
339 * the CCU may also contain data that we haven't flushed out yet, so we
340 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
341 * emit a WFI as it isn't pipelined.
342 *
343 * Note: On A7XX, with the introduction of RB_CCU_CNTL2, we no longer need
344 * to emit a WFI when changing a subset of CCU state.
345 */
346 if (ccu_state != cmd_buffer->state.ccu_state) {
347 if (cmd_buffer->state.ccu_state != TU_CMD_CCU_GMEM) {
348 cmd_buffer->state.cache.flush_bits |=
349 TU_CMD_FLAG_CCU_CLEAN_COLOR |
350 TU_CMD_FLAG_CCU_CLEAN_DEPTH;
351 cmd_buffer->state.cache.pending_flush_bits &= ~(
352 TU_CMD_FLAG_CCU_CLEAN_COLOR |
353 TU_CMD_FLAG_CCU_CLEAN_DEPTH);
354 }
355 cmd_buffer->state.cache.flush_bits |=
356 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
357 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
358 (CHIP == A6XX ? TU_CMD_FLAG_WAIT_FOR_IDLE : 0);
359 cmd_buffer->state.cache.pending_flush_bits &= ~(
360 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
361 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
362 (CHIP == A6XX ? TU_CMD_FLAG_WAIT_FOR_IDLE : 0));
363 }
364
365 tu6_emit_flushes<CHIP>(cmd_buffer, cs, &cmd_buffer->state.cache);
366
367 if (ccu_state != cmd_buffer->state.ccu_state) {
368 emit_rb_ccu_cntl<CHIP>(cs, cmd_buffer->device,
369 ccu_state == TU_CMD_CCU_GMEM);
370 cmd_buffer->state.ccu_state = ccu_state;
371 }
372 }
373 TU_GENX(tu_emit_cache_flush_ccu);
374
375 template <chip CHIP>
376 static void
tu6_emit_zs(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)377 tu6_emit_zs(struct tu_cmd_buffer *cmd,
378 const struct tu_subpass *subpass,
379 struct tu_cs *cs)
380 {
381 const uint32_t a = subpass->depth_stencil_attachment.attachment;
382 if (a == VK_ATTACHMENT_UNUSED) {
383 tu_cs_emit_regs(cs,
384 RB_DEPTH_BUFFER_INFO(CHIP, .depth_format = DEPTH6_NONE),
385 A6XX_RB_DEPTH_BUFFER_PITCH(0),
386 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
387 A6XX_RB_DEPTH_BUFFER_BASE(0),
388 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
389
390 tu_cs_emit_regs(cs,
391 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
392
393 tu_cs_emit_regs(cs, RB_STENCIL_INFO(CHIP, 0));
394
395 return;
396 }
397
398 const struct tu_image_view *iview = cmd->state.attachments[a];
399 const struct tu_render_pass_attachment *attachment =
400 &cmd->state.pass->attachments[a];
401 enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
402
403 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
404 tu_cs_emit(cs, RB_DEPTH_BUFFER_INFO(CHIP,
405 .depth_format = fmt,
406 .tilemode = TILE6_3,
407 .losslesscompen = iview->view.ubwc_enabled,
408 ).value);
409 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
410 tu_cs_image_depth_ref(cs, iview, 0);
411 else
412 tu_cs_image_ref(cs, &iview->view, 0);
413 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment, 0));
414
415 tu_cs_emit_regs(cs,
416 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
417
418 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
419 tu_cs_image_flag_ref(cs, &iview->view, 0);
420
421 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
422 attachment->format == VK_FORMAT_S8_UINT) {
423
424 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
425 tu_cs_emit(cs, RB_STENCIL_INFO(CHIP,
426 .separate_stencil = true,
427 .tilemode = TILE6_3,
428 ).value);
429 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
430 tu_cs_image_stencil_ref(cs, iview, 0);
431 tu_cs_emit(cs, tu_attachment_gmem_offset_stencil(cmd, attachment, 0));
432 } else {
433 tu_cs_image_ref(cs, &iview->view, 0);
434 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment, 0));
435 }
436 } else {
437 tu_cs_emit_regs(cs,
438 RB_STENCIL_INFO(CHIP, 0));
439 }
440 }
441
442 template <chip CHIP>
443 static void
tu6_emit_mrt(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)444 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
445 const struct tu_subpass *subpass,
446 struct tu_cs *cs)
447 {
448 const struct tu_framebuffer *fb = cmd->state.framebuffer;
449
450 enum a6xx_format mrt0_format = FMT6_NONE;
451
452 for (uint32_t i = 0; i < subpass->color_count; ++i) {
453 uint32_t a = subpass->color_attachments[i].attachment;
454 if (a == VK_ATTACHMENT_UNUSED) {
455 /* From the VkPipelineRenderingCreateInfo definition:
456 *
457 * Valid formats indicate that an attachment can be used - but it
458 * is still valid to set the attachment to NULL when beginning
459 * rendering.
460 *
461 * This means that with dynamic rendering, pipelines may write to
462 * some attachments that are UNUSED here. Setting the format to 0
463 * here should prevent them from writing to anything. This also seems
464 * to also be required for alpha-to-coverage which can use the alpha
465 * value for an otherwise-unused attachment.
466 */
467 tu_cs_emit_regs(cs,
468 RB_MRT_BUF_INFO(CHIP, i),
469 A6XX_RB_MRT_PITCH(i),
470 A6XX_RB_MRT_ARRAY_PITCH(i),
471 A6XX_RB_MRT_BASE(i),
472 A6XX_RB_MRT_BASE_GMEM(i),
473 );
474
475 tu_cs_emit_regs(cs,
476 A6XX_SP_FS_MRT_REG(i, .dword = 0));
477 continue;
478 }
479
480 const struct tu_image_view *iview = cmd->state.attachments[a];
481
482 tu_cs_emit_regs(cs,
483 RB_MRT_BUF_INFO(CHIP, i, .dword = iview->view.RB_MRT_BUF_INFO),
484 A6XX_RB_MRT_PITCH(i, iview->view.pitch),
485 A6XX_RB_MRT_ARRAY_PITCH(i, iview->view.layer_size),
486 A6XX_RB_MRT_BASE(i, .qword = tu_layer_address(&iview->view, 0)),
487 A6XX_RB_MRT_BASE_GMEM(i,
488 tu_attachment_gmem_offset(cmd, &cmd->state.pass->attachments[a], 0)
489 ),
490 );
491
492 tu_cs_emit_regs(cs,
493 A6XX_SP_FS_MRT_REG(i, .dword = iview->view.SP_FS_MRT_REG));
494
495 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3);
496 tu_cs_image_flag_ref(cs, &iview->view, 0);
497
498 if (i == 0)
499 mrt0_format = (enum a6xx_format) (iview->view.SP_FS_MRT_REG & 0xff);
500 }
501
502 tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = mrt0_format));
503
504 const bool dither = subpass->legacy_dithering_enabled;
505 const uint32_t dither_cntl =
506 A6XX_RB_DITHER_CNTL(
507 .dither_mode_mrt0 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
508 .dither_mode_mrt1 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
509 .dither_mode_mrt2 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
510 .dither_mode_mrt3 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
511 .dither_mode_mrt4 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
512 .dither_mode_mrt5 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
513 .dither_mode_mrt6 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
514 .dither_mode_mrt7 = dither ? DITHER_ALWAYS : DITHER_DISABLE, )
515 .value;
516 tu_cs_emit_regs(cs, A6XX_RB_DITHER_CNTL(.dword = dither_cntl));
517 if (CHIP >= A7XX) {
518 tu_cs_emit_regs(cs, A7XX_SP_DITHER_CNTL(.dword = dither_cntl));
519 }
520
521 tu_cs_emit_regs(cs,
522 A6XX_RB_SRGB_CNTL(.dword = subpass->srgb_cntl));
523 tu_cs_emit_regs(cs,
524 A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
525
526 unsigned layers = MAX2(fb->layers, util_logbase2(subpass->multiview_mask) + 1);
527 tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(layers - 1));
528 }
529
530 struct tu_bin_size_params {
531 enum a6xx_render_mode render_mode;
532 bool force_lrz_write_dis;
533 enum a6xx_buffers_location buffers_location;
534 enum a6xx_lrz_feedback_mask lrz_feedback_zmode_mask;
535 };
536
537 template <chip CHIP>
538 static void
tu6_emit_bin_size(struct tu_cs * cs,uint32_t bin_w,uint32_t bin_h,struct tu_bin_size_params && p)539 tu6_emit_bin_size(struct tu_cs *cs,
540 uint32_t bin_w,
541 uint32_t bin_h,
542 struct tu_bin_size_params &&p)
543 {
544 if (CHIP == A6XX) {
545 tu_cs_emit_regs(
546 cs, A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
547 .binh = bin_h,
548 .render_mode = p.render_mode,
549 .force_lrz_write_dis = p.force_lrz_write_dis,
550 .buffers_location = p.buffers_location,
551 .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, ));
552 } else {
553 tu_cs_emit_regs(cs,
554 A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
555 .binh = bin_h,
556 .render_mode = p.render_mode,
557 .force_lrz_write_dis = p.force_lrz_write_dis,
558 .lrz_feedback_zmode_mask =
559 p.lrz_feedback_zmode_mask, ));
560 }
561
562 tu_cs_emit_regs(cs, RB_BIN_CONTROL(CHIP,
563 .binw = bin_w,
564 .binh = bin_h,
565 .render_mode = p.render_mode,
566 .force_lrz_write_dis = p.force_lrz_write_dis,
567 .buffers_location = p.buffers_location,
568 .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, ));
569
570 /* no flag for RB_BIN_CONTROL2... */
571 tu_cs_emit_regs(cs,
572 A6XX_RB_BIN_CONTROL2(.binw = bin_w,
573 .binh = bin_h));
574 }
575
576 template <chip CHIP>
577 static void
578 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
579 const struct tu_subpass *subpass,
580 struct tu_cs *cs,
581 bool binning);
582
583 template <>
584 void
tu6_emit_render_cntl(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs,bool binning)585 tu6_emit_render_cntl<A6XX>(struct tu_cmd_buffer *cmd,
586 const struct tu_subpass *subpass,
587 struct tu_cs *cs,
588 bool binning)
589 {
590 /* doesn't RB_RENDER_CNTL set differently for binning pass: */
591 bool no_track = !cmd->device->physical_device->info->a6xx.has_cp_reg_write;
592 uint32_t cntl = 0;
593 cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
594 if (binning) {
595 if (no_track)
596 return;
597 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
598 } else {
599 uint32_t mrts_ubwc_enable = 0;
600 for (uint32_t i = 0; i < subpass->color_count; ++i) {
601 uint32_t a = subpass->color_attachments[i].attachment;
602 if (a == VK_ATTACHMENT_UNUSED)
603 continue;
604
605 const struct tu_image_view *iview = cmd->state.attachments[a];
606 if (iview->view.ubwc_enabled)
607 mrts_ubwc_enable |= 1 << i;
608 }
609
610 cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
611
612 const uint32_t a = subpass->depth_stencil_attachment.attachment;
613 if (a != VK_ATTACHMENT_UNUSED) {
614 const struct tu_image_view *iview = cmd->state.attachments[a];
615 if (iview->view.ubwc_enabled)
616 cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
617 }
618
619 if (no_track) {
620 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CNTL, 1);
621 tu_cs_emit(cs, cntl);
622 return;
623 }
624
625 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
626 * in order to set it correctly for the different subpasses. However,
627 * that means the packets we're emitting also happen during binning. So
628 * we need to guard the write on !BINNING at CP execution time.
629 */
630 tu_cs_reserve(cs, 3 + 4);
631 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
632 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
633 CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
634 tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(4));
635 }
636
637 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
638 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
639 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
640 tu_cs_emit(cs, cntl);
641 }
642
643 template <>
644 void
tu6_emit_render_cntl(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs,bool binning)645 tu6_emit_render_cntl<A7XX>(struct tu_cmd_buffer *cmd,
646 const struct tu_subpass *subpass,
647 struct tu_cs *cs,
648 bool binning)
649 {
650 tu_cs_emit_regs(
651 cs, RB_RENDER_CNTL(A7XX, .binning = binning, .raster_mode = TYPE_TILED,
652 .raster_direction = LR_TB));
653 tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL(.binning = binning));
654 }
655
656 static void
tu6_emit_blit_scissor(struct tu_cmd_buffer * cmd,struct tu_cs * cs,bool align)657 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
658 {
659 struct tu_physical_device *phys_dev = cmd->device->physical_device;
660 const VkRect2D *render_area = &cmd->state.render_area;
661
662 /* Avoid assertion fails with an empty render area at (0, 0) where the
663 * subtraction below wraps around. Empty render areas should be forced to
664 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
665 * an empty scissor here works, and the blob seems to force sysmem too as
666 * it sets something wrong (non-empty) for the scissor.
667 */
668 if (render_area->extent.width == 0 ||
669 render_area->extent.height == 0)
670 return;
671
672 uint32_t x1 = render_area->offset.x;
673 uint32_t y1 = render_area->offset.y;
674 uint32_t x2 = x1 + render_area->extent.width - 1;
675 uint32_t y2 = y1 + render_area->extent.height - 1;
676
677 if (align) {
678 x1 = x1 & ~(phys_dev->info->gmem_align_w - 1);
679 y1 = y1 & ~(phys_dev->info->gmem_align_h - 1);
680 x2 = ALIGN_POT(x2 + 1, phys_dev->info->gmem_align_w) - 1;
681 y2 = ALIGN_POT(y2 + 1, phys_dev->info->gmem_align_h) - 1;
682 }
683
684 tu_cs_emit_regs(cs,
685 A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
686 A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
687 }
688
689 void
tu6_emit_window_scissor(struct tu_cs * cs,uint32_t x1,uint32_t y1,uint32_t x2,uint32_t y2)690 tu6_emit_window_scissor(struct tu_cs *cs,
691 uint32_t x1,
692 uint32_t y1,
693 uint32_t x2,
694 uint32_t y2)
695 {
696 tu_cs_emit_regs(cs,
697 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
698 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
699
700 tu_cs_emit_regs(cs,
701 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
702 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
703 }
704
705 template <chip CHIP>
706 void
tu6_emit_window_offset(struct tu_cs * cs,uint32_t x1,uint32_t y1)707 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
708 {
709 tu_cs_emit_regs(cs,
710 A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
711
712 tu_cs_emit_regs(cs,
713 A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
714
715 tu_cs_emit_regs(cs,
716 SP_WINDOW_OFFSET(CHIP, .x = x1, .y = y1));
717
718 tu_cs_emit_regs(cs,
719 A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
720
721 tu_cs_emit_regs(cs,
722 A7XX_SP_PS_2D_WINDOW_OFFSET(.x = x1, .y = y1));
723 }
724
725 void
tu6_apply_depth_bounds_workaround(struct tu_device * device,uint32_t * rb_depth_cntl)726 tu6_apply_depth_bounds_workaround(struct tu_device *device,
727 uint32_t *rb_depth_cntl)
728 {
729 if (!device->physical_device->info->a6xx.depth_bounds_require_depth_test_quirk)
730 return;
731
732 /* On some GPUs it is necessary to enable z test for depth bounds test when
733 * UBWC is enabled. Otherwise, the GPU would hang. FUNC_ALWAYS is required to
734 * pass z test. Relevant tests:
735 * dEQP-VK.pipeline.extended_dynamic_state.two_draws_dynamic.depth_bounds_test_disable
736 * dEQP-VK.dynamic_state.ds_state.depth_bounds_1
737 */
738 *rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE |
739 A6XX_RB_DEPTH_CNTL_ZFUNC(FUNC_ALWAYS);
740 }
741
742 static void
tu_cs_emit_draw_state(struct tu_cs * cs,uint32_t id,struct tu_draw_state state)743 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
744 {
745 uint32_t enable_mask;
746 switch (id) {
747 case TU_DRAW_STATE_VS:
748 case TU_DRAW_STATE_FS:
749 case TU_DRAW_STATE_VPC:
750 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
751 * when resources would actually be used in the binning shader.
752 * Presumably the overhead of prefetching the resources isn't
753 * worth it.
754 */
755 case TU_DRAW_STATE_DESC_SETS_LOAD:
756 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
757 CP_SET_DRAW_STATE__0_SYSMEM;
758 break;
759 case TU_DRAW_STATE_VS_BINNING:
760 case TU_DRAW_STATE_GS_BINNING:
761 enable_mask = CP_SET_DRAW_STATE__0_BINNING;
762 break;
763 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM:
764 enable_mask = CP_SET_DRAW_STATE__0_GMEM;
765 break;
766 case TU_DRAW_STATE_PRIM_MODE_GMEM:
767 /* On a7xx the prim mode is the same for gmem and sysmem, and it no
768 * longer depends on dynamic state, so we reuse the gmem state for
769 * everything:
770 */
771 if (cs->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
772 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
773 CP_SET_DRAW_STATE__0_SYSMEM |
774 CP_SET_DRAW_STATE__0_BINNING;
775 } else {
776 enable_mask = CP_SET_DRAW_STATE__0_GMEM;
777 }
778 break;
779 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM:
780 enable_mask = CP_SET_DRAW_STATE__0_SYSMEM;
781 break;
782 case TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM:
783 /* By also applying the state during binning we ensure that there
784 * is no rotation applied, by previous A6XX_GRAS_SC_CNTL::rotation.
785 */
786 enable_mask =
787 CP_SET_DRAW_STATE__0_SYSMEM | CP_SET_DRAW_STATE__0_BINNING;
788 break;
789 default:
790 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
791 CP_SET_DRAW_STATE__0_SYSMEM |
792 CP_SET_DRAW_STATE__0_BINNING;
793 break;
794 }
795
796 STATIC_ASSERT(TU_DRAW_STATE_COUNT <= 32);
797
798 /* We need to reload the descriptors every time the descriptor sets
799 * change. However, the commands we send only depend on the pipeline
800 * because the whole point is to cache descriptors which are used by the
801 * pipeline. There's a problem here, in that the firmware has an
802 * "optimization" which skips executing groups that are set to the same
803 * value as the last draw. This means that if the descriptor sets change
804 * but not the pipeline, we'd try to re-execute the same buffer which
805 * the firmware would ignore and we wouldn't pre-load the new
806 * descriptors. Set the DIRTY bit to avoid this optimization.
807 *
808 * We set the dirty bit for shader draw states because they contain
809 * CP_LOAD_STATE packets that are invalidated by the PROGRAM_CONFIG draw
810 * state, so if PROGRAM_CONFIG changes but one of the shaders stays the
811 * same then we still need to re-emit everything. The GLES blob which
812 * implements separate shader draw states does the same thing.
813 *
814 * We also need to set this bit for draw states which may be patched by the
815 * GPU, because their underlying memory may change between setting the draw
816 * state.
817 */
818 if (id == TU_DRAW_STATE_DESC_SETS_LOAD ||
819 id == TU_DRAW_STATE_VS ||
820 id == TU_DRAW_STATE_VS_BINNING ||
821 id == TU_DRAW_STATE_HS ||
822 id == TU_DRAW_STATE_DS ||
823 id == TU_DRAW_STATE_GS ||
824 id == TU_DRAW_STATE_GS_BINNING ||
825 id == TU_DRAW_STATE_FS ||
826 state.writeable)
827 enable_mask |= CP_SET_DRAW_STATE__0_DIRTY;
828
829 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) |
830 enable_mask |
831 CP_SET_DRAW_STATE__0_GROUP_ID(id) |
832 COND(!state.size || !state.iova, CP_SET_DRAW_STATE__0_DISABLE));
833 tu_cs_emit_qw(cs, state.iova);
834 }
835
836 void
tu6_emit_msaa(struct tu_cs * cs,VkSampleCountFlagBits vk_samples,bool msaa_disable)837 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples,
838 bool msaa_disable)
839 {
840 const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
841 msaa_disable |= (samples == MSAA_ONE);
842 tu_cs_emit_regs(cs,
843 A6XX_SP_TP_RAS_MSAA_CNTL(samples),
844 A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
845 .msaa_disable = msaa_disable));
846
847 tu_cs_emit_regs(cs,
848 A6XX_GRAS_RAS_MSAA_CNTL(samples),
849 A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
850 .msaa_disable = msaa_disable));
851
852 tu_cs_emit_regs(cs,
853 A6XX_RB_RAS_MSAA_CNTL(samples),
854 A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
855 .msaa_disable = msaa_disable));
856 }
857
858 static void
tu6_update_msaa(struct tu_cmd_buffer * cmd)859 tu6_update_msaa(struct tu_cmd_buffer *cmd)
860 {
861 VkSampleCountFlagBits samples =
862 cmd->vk.dynamic_graphics_state.ms.rasterization_samples;;
863
864 /* The samples may not be set by the pipeline or dynamically if raster
865 * discard is enabled. We can set any valid value, but don't set the
866 * default invalid value of 0.
867 */
868 if (samples == 0)
869 samples = VK_SAMPLE_COUNT_1_BIT;
870 tu6_emit_msaa(&cmd->draw_cs, samples, cmd->state.msaa_disable);
871 }
872
873 static void
tu6_update_msaa_disable(struct tu_cmd_buffer * cmd)874 tu6_update_msaa_disable(struct tu_cmd_buffer *cmd)
875 {
876 VkPrimitiveTopology topology =
877 (VkPrimitiveTopology)cmd->vk.dynamic_graphics_state.ia.primitive_topology;
878 bool is_line =
879 topology == VK_PRIMITIVE_TOPOLOGY_LINE_LIST ||
880 topology == VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY ||
881 topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP ||
882 topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY ||
883 (topology == VK_PRIMITIVE_TOPOLOGY_PATCH_LIST &&
884 cmd->state.shaders[MESA_SHADER_TESS_EVAL] &&
885 cmd->state.shaders[MESA_SHADER_TESS_EVAL]->variant &&
886 cmd->state.shaders[MESA_SHADER_TESS_EVAL]->variant->key.tessellation == IR3_TESS_ISOLINES);
887 bool msaa_disable = is_line &&
888 cmd->vk.dynamic_graphics_state.rs.line.mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_KHR;
889
890 if (cmd->state.msaa_disable != msaa_disable) {
891 cmd->state.msaa_disable = msaa_disable;
892 tu6_update_msaa(cmd);
893 }
894 }
895
896 static bool
use_hw_binning(struct tu_cmd_buffer * cmd)897 use_hw_binning(struct tu_cmd_buffer *cmd)
898 {
899 const struct tu_framebuffer *fb = cmd->state.framebuffer;
900 const struct tu_tiling_config *tiling = &fb->tiling[cmd->state.gmem_layout];
901
902 /* XFB commands are emitted for BINNING || SYSMEM, which makes it
903 * incompatible with non-hw binning GMEM rendering. this is required because
904 * some of the XFB commands need to only be executed once.
905 * use_sysmem_rendering() should have made sure we only ended up here if no
906 * XFB was used.
907 */
908 if (cmd->state.rp.xfb_used) {
909 assert(tiling->binning_possible);
910 return true;
911 }
912
913 /* VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT emulates GL_PRIMITIVES_GENERATED,
914 * which wasn't designed to care about tilers and expects the result not to
915 * be multiplied by tile count.
916 * See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3131
917 */
918 if (cmd->state.rp.has_prim_generated_query_in_rp ||
919 cmd->state.prim_generated_query_running_before_rp) {
920 assert(tiling->binning_possible);
921 return true;
922 }
923
924 return tiling->binning;
925 }
926
927 static bool
use_sysmem_rendering(struct tu_cmd_buffer * cmd,struct tu_renderpass_result ** autotune_result)928 use_sysmem_rendering(struct tu_cmd_buffer *cmd,
929 struct tu_renderpass_result **autotune_result)
930 {
931 if (TU_DEBUG(SYSMEM))
932 return true;
933
934 /* can't fit attachments into gmem */
935 if (!cmd->state.tiling->possible)
936 return true;
937
938 if (cmd->state.framebuffer->layers > 1)
939 return true;
940
941 /* Use sysmem for empty render areas */
942 if (cmd->state.render_area.extent.width == 0 ||
943 cmd->state.render_area.extent.height == 0)
944 return true;
945
946 if (cmd->state.rp.has_tess)
947 return true;
948
949 if (cmd->state.rp.disable_gmem)
950 return true;
951
952 /* XFB is incompatible with non-hw binning GMEM rendering, see use_hw_binning */
953 if (cmd->state.rp.xfb_used && !cmd->state.tiling->binning_possible)
954 return true;
955
956 /* QUERY_TYPE_PRIMITIVES_GENERATED is incompatible with non-hw binning
957 * GMEM rendering, see use_hw_binning.
958 */
959 if ((cmd->state.rp.has_prim_generated_query_in_rp ||
960 cmd->state.prim_generated_query_running_before_rp) &&
961 !cmd->state.tiling->binning_possible)
962 return true;
963
964 if (TU_DEBUG(GMEM))
965 return false;
966
967 bool use_sysmem = tu_autotune_use_bypass(&cmd->device->autotune,
968 cmd, autotune_result);
969 if (*autotune_result) {
970 list_addtail(&(*autotune_result)->node, &cmd->renderpass_autotune_results);
971 }
972
973 return use_sysmem;
974 }
975
976 /* Optimization: there is no reason to load gmem if there is no
977 * geometry to process. COND_REG_EXEC predicate is set here,
978 * but the actual skip happens in tu_load_gmem_attachment() and tile_store_cs,
979 * for each blit separately.
980 */
981 static void
tu6_emit_cond_for_load_stores(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t pipe,uint32_t slot,bool skip_wfm)982 tu6_emit_cond_for_load_stores(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
983 uint32_t pipe, uint32_t slot, bool skip_wfm)
984 {
985 if (cmd->state.tiling->binning_possible &&
986 cmd->state.pass->has_cond_load_store) {
987 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
988 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(pipe)) |
989 A6XX_CP_REG_TEST_0_BIT(slot) |
990 COND(skip_wfm, A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME));
991 } else {
992 /* COND_REG_EXECs are not emitted in non-binning case */
993 }
994 }
995
996 template <chip CHIP>
997 static void
tu6_emit_tile_select(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t tx,uint32_t ty,uint32_t pipe,uint32_t slot,const struct tu_image_view * fdm)998 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
999 struct tu_cs *cs,
1000 uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot,
1001 const struct tu_image_view *fdm)
1002 {
1003 const struct tu_tiling_config *tiling = cmd->state.tiling;
1004
1005 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1006 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
1007
1008 const uint32_t x1 = tiling->tile0.width * tx;
1009 const uint32_t y1 = tiling->tile0.height * ty;
1010 const uint32_t x2 = MIN2(x1 + tiling->tile0.width, MAX_VIEWPORT_SIZE);
1011 const uint32_t y2 = MIN2(y1 + tiling->tile0.height, MAX_VIEWPORT_SIZE);
1012 tu6_emit_window_scissor(cs, x1, y1, x2 - 1, y2 - 1);
1013 tu6_emit_window_offset<CHIP>(cs, x1, y1);
1014
1015 bool hw_binning = use_hw_binning(cmd);
1016
1017 if (hw_binning) {
1018 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1019
1020 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1021 tu_cs_emit(cs, 0x0);
1022
1023 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5_OFFSET, 4);
1024 tu_cs_emit(cs, tiling->pipe_sizes[pipe] |
1025 CP_SET_BIN_DATA5_0_VSC_N(slot));
1026 tu_cs_emit(cs, pipe * cmd->vsc_draw_strm_pitch);
1027 tu_cs_emit(cs, pipe * 4);
1028 tu_cs_emit(cs, pipe * cmd->vsc_prim_strm_pitch);
1029 }
1030
1031 tu6_emit_cond_for_load_stores(cmd, cs, pipe, slot, hw_binning);
1032
1033 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1034 tu_cs_emit(cs, !hw_binning);
1035
1036 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1037 tu_cs_emit(cs, 0x0);
1038
1039 if (fdm || (TU_DEBUG(FDM) && cmd->state.pass->has_fdm)) {
1040 unsigned views =
1041 cmd->state.pass->num_views ? cmd->state.pass->num_views : 1;
1042 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1043 struct tu_frag_area raw_areas[views];
1044 if (fdm) {
1045 tu_fragment_density_map_sample(fdm,
1046 (x1 + MIN2(x2, fb->width)) / 2,
1047 (y1 + MIN2(y2, fb->height)) / 2,
1048 fb->width, fb->height, views,
1049 raw_areas);
1050 } else {
1051 for (unsigned i = 0; i < views; i++)
1052 raw_areas[i].width = raw_areas[i].height = 1.0f;
1053 }
1054
1055 VkExtent2D frag_areas[views];
1056 for (unsigned i = 0; i < views; i++) {
1057 float floor_x, floor_y;
1058 float area = raw_areas[i].width * raw_areas[i].height;
1059 float frac_x = modff(raw_areas[i].width, &floor_x);
1060 float frac_y = modff(raw_areas[i].height, &floor_y);
1061 /* The spec allows rounding up one of the axes as long as the total
1062 * area is less than or equal to the original area. Take advantage of
1063 * this to try rounding up the number with the largest fraction.
1064 */
1065 if ((frac_x > frac_y ? (floor_x + 1.f) * floor_y :
1066 floor_x * (floor_y + 1.f)) <= area) {
1067 if (frac_x > frac_y)
1068 floor_x += 1.f;
1069 else
1070 floor_y += 1.f;
1071 }
1072 frag_areas[i].width = floor_x;
1073 frag_areas[i].height = floor_y;
1074
1075 /* Make sure that the width/height divides the tile width/height so
1076 * we don't have to do extra awkward clamping of the edges of each
1077 * bin when resolving. Note that because the tile width is rounded to
1078 * a multiple of 32 any power of two 32 or less will work.
1079 *
1080 * TODO: Try to take advantage of the total area allowance here, too.
1081 */
1082 while (tiling->tile0.width % frag_areas[i].width != 0)
1083 frag_areas[i].width--;
1084 while (tiling->tile0.height % frag_areas[i].height != 0)
1085 frag_areas[i].height--;
1086 }
1087
1088 /* If at any point we were forced to use the same scaling for all
1089 * viewports, we need to make sure that any users *not* using shared
1090 * scaling, including loads/stores, also consistently share the scaling.
1091 */
1092 if (cmd->state.rp.shared_viewport) {
1093 VkExtent2D frag_area = { UINT32_MAX, UINT32_MAX };
1094 for (unsigned i = 0; i < views; i++) {
1095 frag_area.width = MIN2(frag_area.width, frag_areas[i].width);
1096 frag_area.height = MIN2(frag_area.height, frag_areas[i].height);
1097 }
1098
1099 for (unsigned i = 0; i < views; i++)
1100 frag_areas[i] = frag_area;
1101 }
1102
1103 VkRect2D bin = { { x1, y1 }, { x2 - x1, y2 - y1 } };
1104 util_dynarray_foreach (&cmd->fdm_bin_patchpoints,
1105 struct tu_fdm_bin_patchpoint, patch) {
1106 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + patch->size);
1107 tu_cs_emit_qw(cs, patch->iova);
1108 patch->apply(cmd, cs, patch->data, bin, views, frag_areas);
1109 }
1110
1111 /* Make the CP wait until the CP_MEM_WRITE's to the command buffers
1112 * land. When loading FS params via UBOs, we also need to invalidate
1113 * UCHE because the FS param patchpoint is read through UCHE.
1114 */
1115 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1116 if (cmd->device->compiler->load_shader_consts_via_preamble) {
1117 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1118 tu_cs_emit_wfi(cs);
1119 }
1120 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1121 }
1122 }
1123
1124 template <chip CHIP>
1125 static void
tu6_emit_sysmem_resolve(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t layer_mask,uint32_t a,uint32_t gmem_a)1126 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
1127 struct tu_cs *cs,
1128 uint32_t layer_mask,
1129 uint32_t a,
1130 uint32_t gmem_a)
1131 {
1132 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1133 const struct tu_image_view *dst = cmd->state.attachments[a];
1134 const struct tu_image_view *src = cmd->state.attachments[gmem_a];
1135
1136 tu_resolve_sysmem<CHIP>(cmd, cs, src, dst, layer_mask, fb->layers, &cmd->state.render_area);
1137 }
1138
1139 template <chip CHIP>
1140 static void
tu6_emit_sysmem_resolves(struct tu_cmd_buffer * cmd,struct tu_cs * cs,const struct tu_subpass * subpass)1141 tu6_emit_sysmem_resolves(struct tu_cmd_buffer *cmd,
1142 struct tu_cs *cs,
1143 const struct tu_subpass *subpass)
1144 {
1145 if (subpass->resolve_attachments) {
1146 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
1147 * Commands":
1148 *
1149 * End-of-subpass multisample resolves are treated as color
1150 * attachment writes for the purposes of synchronization.
1151 * This applies to resolve operations for both color and
1152 * depth/stencil attachments. That is, they are considered to
1153 * execute in the VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
1154 * pipeline stage and their writes are synchronized with
1155 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
1156 * rendering within a subpass and any resolve operations at the end
1157 * of the subpass occurs automatically, without need for explicit
1158 * dependencies or pipeline barriers. However, if the resolve
1159 * attachment is also used in a different subpass, an explicit
1160 * dependency is needed.
1161 *
1162 * We use the CP_BLIT path for sysmem resolves, which is really a
1163 * transfer command, so we have to manually flush similar to the gmem
1164 * resolve case. However, a flush afterwards isn't needed because of the
1165 * last sentence and the fact that we're in sysmem mode.
1166 */
1167 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_COLOR);
1168 if (subpass->resolve_depth_stencil)
1169 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_DEPTH);
1170
1171 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1172
1173 /* Wait for the flushes to land before using the 2D engine */
1174 tu_cs_emit_wfi(cs);
1175
1176 for (unsigned i = 0; i < subpass->resolve_count; i++) {
1177 uint32_t a = subpass->resolve_attachments[i].attachment;
1178 if (a == VK_ATTACHMENT_UNUSED)
1179 continue;
1180
1181 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
1182
1183 tu6_emit_sysmem_resolve<CHIP>(cmd, cs, subpass->multiview_mask, a, gmem_a);
1184 }
1185 }
1186 }
1187
1188 template <chip CHIP>
1189 static void
tu6_emit_tile_store(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1190 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1191 {
1192 const struct tu_render_pass *pass = cmd->state.pass;
1193 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
1194 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1195
1196 if (pass->has_fdm)
1197 tu_cs_set_writeable(cs, true);
1198
1199 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1200 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1201
1202 tu6_emit_blit_scissor(cmd, cs, true);
1203
1204 /* Resolve should happen before store in case BLIT_EVENT_STORE_AND_CLEAR is
1205 * used for a store.
1206 */
1207 if (subpass->resolve_attachments) {
1208 for (unsigned i = 0; i < subpass->resolve_count; i++) {
1209 uint32_t a = subpass->resolve_attachments[i].attachment;
1210 if (a != VK_ATTACHMENT_UNUSED) {
1211 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
1212 tu_store_gmem_attachment<CHIP>(cmd, cs, a, gmem_a, fb->layers,
1213 subpass->multiview_mask, false);
1214 }
1215 }
1216 }
1217
1218 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
1219 if (pass->attachments[a].gmem) {
1220 const bool cond_exec_allowed = cmd->state.tiling->binning_possible &&
1221 cmd->state.pass->has_cond_load_store;
1222 tu_store_gmem_attachment<CHIP>(cmd, cs, a, a,
1223 fb->layers, subpass->multiview_mask,
1224 cond_exec_allowed);
1225 }
1226 }
1227
1228 if (pass->has_fdm)
1229 tu_cs_set_writeable(cs, false);
1230 }
1231
1232 void
tu_disable_draw_states(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1233 tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1234 {
1235 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1236 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1237 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1238 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1239 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1240 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1241
1242 cmd->state.dirty |= TU_CMD_DIRTY_DRAW_STATE;
1243 }
1244
1245 template <chip CHIP>
1246 static void
tu6_init_hw(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1247 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1248 {
1249 struct tu_device *dev = cmd->device;
1250 const struct tu_physical_device *phys_dev = dev->physical_device;
1251
1252 if (CHIP == A6XX) {
1253 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1254 } else {
1255 tu_cs_emit_pkt7(cs, CP_THREAD_CONTROL, 1);
1256 tu_cs_emit(cs, CP_THREAD_CONTROL_0_THREAD(CP_SET_THREAD_BR) |
1257 CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE);
1258
1259 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_INVALIDATE_COLOR);
1260 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_INVALIDATE_DEPTH);
1261 tu_emit_raw_event_write<CHIP>(cmd, cs, UNK_40, false);
1262 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1263 tu_cs_emit_wfi(cs);
1264 }
1265
1266 tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
1267 .vs_state = true,
1268 .hs_state = true,
1269 .ds_state = true,
1270 .gs_state = true,
1271 .fs_state = true,
1272 .cs_state = true,
1273 .cs_ibo = true,
1274 .gfx_ibo = true,
1275 .cs_shared_const = true,
1276 .gfx_shared_const = true,
1277 .cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
1278 .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,));
1279
1280 tu_cs_emit_wfi(cs);
1281
1282 if (dev->dbg_cmdbuf_stomp_cs) {
1283 tu_cs_emit_call(cs, dev->dbg_cmdbuf_stomp_cs);
1284 }
1285
1286 cmd->state.cache.pending_flush_bits &=
1287 ~(TU_CMD_FLAG_WAIT_FOR_IDLE | TU_CMD_FLAG_CACHE_INVALIDATE);
1288
1289 if (CHIP >= A7XX) {
1290 /* On A7XX, RB_CCU_CNTL was broken into two registers, RB_CCU_CNTL which has
1291 * static properties that can be set once, this requires a WFI to take effect.
1292 * While the newly introduced register RB_CCU_CNTL2 has properties that may
1293 * change per-RP and don't require a WFI to take effect, only CCU inval/flush
1294 * events are required.
1295 */
1296 tu_cs_emit_regs(cs, RB_CCU_CNTL(CHIP,
1297 .gmem_fast_clear_disable =
1298 !dev->physical_device->info->a6xx.has_gmem_fast_clear,
1299 .concurrent_resolve = dev->physical_device->info->a6xx.concurrent_resolve,
1300 ));
1301 tu_cs_emit_wfi(cs);
1302 }
1303
1304 emit_rb_ccu_cntl<CHIP>(cs, cmd->device, false);
1305 cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
1306
1307 for (size_t i = 0; i < ARRAY_SIZE(phys_dev->info->a6xx.magic_raw); i++) {
1308 auto magic_reg = phys_dev->info->a6xx.magic_raw[i];
1309 if (!magic_reg.reg)
1310 break;
1311
1312 uint32_t value = magic_reg.value;
1313 switch(magic_reg.reg) {
1314 case REG_A6XX_TPL1_DBG_ECO_CNTL1:
1315 value = (value & ~A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT) |
1316 (phys_dev->info->a7xx.enable_tp_ubwc_flag_hint
1317 ? A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT
1318 : 0);
1319 break;
1320 }
1321
1322 tu_cs_emit_write_reg(cs, magic_reg.reg, value);
1323 }
1324
1325 tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,
1326 phys_dev->info->a6xx.magic.RB_DBG_ECO_CNTL);
1327 tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
1328 tu_cs_emit_write_reg(cs, REG_A6XX_SP_DBG_ECO_CNTL,
1329 phys_dev->info->a6xx.magic.SP_DBG_ECO_CNTL);
1330 tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
1331 if (CHIP == A6XX)
1332 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
1333 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
1334 phys_dev->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
1335 if (CHIP == A6XX) {
1336 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1337 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1338 }
1339
1340 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_DBG_ECO_CNTL,
1341 phys_dev->info->a6xx.magic.VPC_DBG_ECO_CNTL);
1342 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL,
1343 phys_dev->info->a6xx.magic.GRAS_DBG_ECO_CNTL);
1344 if (CHIP == A6XX) {
1345 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_DBG_ECO_CNTL,
1346 phys_dev->info->a6xx.magic.HLSQ_DBG_ECO_CNTL);
1347 }
1348 tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS,
1349 phys_dev->info->a6xx.magic.SP_CHICKEN_BITS);
1350 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0); // 2 on a740 ???
1351 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
1352 if (CHIP == A6XX)
1353 tu_cs_emit_regs(cs, A6XX_HLSQ_SHARED_CONSTS(.enable = false));
1354 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12,
1355 phys_dev->info->a6xx.magic.UCHE_UNKNOWN_0E12);
1356 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF,
1357 phys_dev->info->a6xx.magic.UCHE_CLIENT_PF);
1358 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01,
1359 phys_dev->info->a6xx.magic.RB_UNKNOWN_8E01);
1360 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
1361 tu_cs_emit_regs(cs, A6XX_SP_MODE_CONTROL(.constant_demotion_enable = true,
1362 .isammode = ISAMMODE_GL,
1363 .shared_consts_enable = false));
1364
1365 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
1366 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1367 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1368 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL,
1369 phys_dev->info->a6xx.magic.PC_MODE_CNTL);
1370
1371 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
1372
1373 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
1374
1375 if (CHIP == A6XX) {
1376 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
1377 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
1378 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
1379 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
1380 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
1381 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
1382 }
1383
1384 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
1385
1386 tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false));
1387 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1388
1389 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
1390
1391 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1392
1393 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
1394 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1395 if (CHIP == A6XX) {
1396 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1397 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1398 }
1399 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1400 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1401 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_MODE_CNTL,
1402 0x000000a0 |
1403 A6XX_SP_TP_MODE_CNTL_ISAMMODE(ISAMMODE_GL));
1404 tu_cs_emit_regs(cs, HLSQ_CONTROL_5_REG(CHIP, .dword = 0xfc));
1405
1406 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1407
1408 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, phys_dev->info->a6xx.magic.PC_MODE_CNTL);
1409
1410 tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL()); /* always disable alpha test */
1411
1412 tu_disable_draw_states(cmd, cs);
1413
1414 tu_cs_emit_regs(cs,
1415 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = dev->global_bo,
1416 .bo_offset = gb_offset(bcolor_builtin)));
1417 tu_cs_emit_regs(cs,
1418 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = dev->global_bo,
1419 .bo_offset = gb_offset(bcolor_builtin)));
1420
1421 if (CHIP == A7XX) {
1422 tu_cs_emit_regs(cs, TPL1_BICUBIC_WEIGHTS_TABLE_0(CHIP, 0),
1423 TPL1_BICUBIC_WEIGHTS_TABLE_1(CHIP, 0x3fe05ff4),
1424 TPL1_BICUBIC_WEIGHTS_TABLE_2(CHIP, 0x3fa0ebee),
1425 TPL1_BICUBIC_WEIGHTS_TABLE_3(CHIP, 0x3f5193ed),
1426 TPL1_BICUBIC_WEIGHTS_TABLE_4(CHIP, 0x3f0243f0), );
1427 }
1428
1429 if (phys_dev->info->a7xx.cmdbuf_start_a725_quirk) {
1430 tu_cs_reserve(cs, 3 + 4);
1431 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1432 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(THREAD_MODE) |
1433 CP_COND_REG_EXEC_0_BR | CP_COND_REG_EXEC_0_LPAC);
1434 tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(4));
1435 tu_cs_emit_ib(cs, dev->cmdbuf_start_a725_quirk_entry);
1436 }
1437
1438 if (CHIP >= A7XX) {
1439 /* Blob sets these two per draw. */
1440 tu_cs_emit_regs(cs, A7XX_PC_TESS_PARAM_SIZE(TU_TESS_PARAM_SIZE));
1441 /* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
1442 * but the meaning of this additional space is not known,
1443 * so we play safe and don't add it.
1444 */
1445 tu_cs_emit_regs(cs, A7XX_PC_TESS_FACTOR_SIZE(TU_TESS_FACTOR_SIZE));
1446 }
1447
1448 /* There is an optimization to skip executing draw states for draws with no
1449 * instances. Instead of simply skipping the draw, internally the firmware
1450 * sets a bit in PC_DRAW_INITIATOR that seemingly skips the draw. However
1451 * there is a hardware bug where this bit does not always cause the FS
1452 * early preamble to be skipped. Because the draw states were skipped,
1453 * SP_FS_CTRL_REG0, SP_FS_OBJ_START and so on are never updated and a
1454 * random FS preamble from the last draw is executed. If the last visible
1455 * draw is from the same submit, it shouldn't be a problem because we just
1456 * re-execute the same preamble and preambles don't have side effects, but
1457 * if it's from another process then we could execute a garbage preamble
1458 * leading to hangs and faults. To make sure this doesn't happen, we reset
1459 * SP_FS_CTRL_REG0 here, making sure that the EARLYPREAMBLE bit isn't set
1460 * so any leftover early preamble doesn't get executed. Other stages don't
1461 * seem to be affected.
1462 */
1463 if (phys_dev->info->a6xx.has_early_preamble) {
1464 tu_cs_emit_regs(cs, A6XX_SP_FS_CTRL_REG0());
1465 }
1466
1467 tu_cs_sanity_check(cs);
1468 }
1469
1470 static void
update_vsc_pipe(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t num_vsc_pipes)1471 update_vsc_pipe(struct tu_cmd_buffer *cmd,
1472 struct tu_cs *cs,
1473 uint32_t num_vsc_pipes)
1474 {
1475 const struct tu_tiling_config *tiling = cmd->state.tiling;
1476
1477 tu_cs_emit_regs(cs,
1478 A6XX_VSC_BIN_SIZE(.width = tiling->tile0.width,
1479 .height = tiling->tile0.height));
1480
1481 tu_cs_emit_regs(cs,
1482 A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1483 .ny = tiling->tile_count.height));
1484
1485 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), num_vsc_pipes);
1486 tu_cs_emit_array(cs, tiling->pipe_config, num_vsc_pipes);
1487
1488 tu_cs_emit_regs(cs,
1489 A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
1490 A6XX_VSC_PRIM_STRM_LIMIT(cmd->vsc_prim_strm_pitch - VSC_PAD));
1491
1492 tu_cs_emit_regs(cs,
1493 A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
1494 A6XX_VSC_DRAW_STRM_LIMIT(cmd->vsc_draw_strm_pitch - VSC_PAD));
1495
1496 tu_cs_emit_regs(cs, A7XX_VSC_UNKNOWN_0D08(0));
1497 }
1498
1499 static void
emit_vsc_overflow_test(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1500 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1501 {
1502 const struct tu_tiling_config *tiling = cmd->state.tiling;
1503 const uint32_t used_pipe_count =
1504 tiling->pipe_count.width * tiling->pipe_count.height;
1505
1506 for (int i = 0; i < used_pipe_count; i++) {
1507 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1508 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1509 CP_COND_WRITE5_0_WRITE_MEMORY);
1510 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
1511 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1512 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD));
1513 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1514 tu_cs_emit_qw(cs, global_iova(cmd, vsc_draw_overflow));
1515 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_draw_strm_pitch));
1516
1517 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1518 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1519 CP_COND_WRITE5_0_WRITE_MEMORY);
1520 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
1521 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1522 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD));
1523 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1524 tu_cs_emit_qw(cs, global_iova(cmd, vsc_prim_overflow));
1525 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_prim_strm_pitch));
1526 }
1527
1528 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1529 }
1530
1531 template <chip CHIP>
1532 static void
tu6_emit_binning_pass(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1533 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1534 {
1535 struct tu_physical_device *phys_dev = cmd->device->physical_device;
1536 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1537
1538 /* If this command buffer may be executed multiple times, then
1539 * viewports/scissor states may have been changed by previous executions
1540 * and we need to reset them before executing the binning IB.
1541 */
1542 if (!(cmd->usage_flags & VK_COMMAND_BUFFER_USAGE_ONE_TIME_SUBMIT_BIT) &&
1543 cmd->fdm_bin_patchpoints.size != 0) {
1544 unsigned num_views = MAX2(cmd->state.pass->num_views, 1);
1545 VkExtent2D unscaled_frag_areas[num_views];
1546 for (unsigned i = 0; i < num_views; i++)
1547 unscaled_frag_areas[i] = (VkExtent2D) { 1, 1 };
1548 VkRect2D bin = { { 0, 0 }, { fb->width, fb->height } };
1549 util_dynarray_foreach (&cmd->fdm_bin_patchpoints,
1550 struct tu_fdm_bin_patchpoint, patch) {
1551 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + patch->size);
1552 tu_cs_emit_qw(cs, patch->iova);
1553 patch->apply(cmd, cs, patch->data, bin, num_views, unscaled_frag_areas);
1554 }
1555
1556 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1557 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1558 }
1559
1560 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1561
1562 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1563 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1564
1565 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1566 tu_cs_emit(cs, 0x1);
1567
1568 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1569 tu_cs_emit(cs, 0x1);
1570
1571 tu_cs_emit_wfi(cs);
1572
1573 tu_cs_emit_regs(cs,
1574 A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
1575
1576 update_vsc_pipe(cmd, cs, phys_dev->info->num_vsc_pipes);
1577
1578 if (CHIP == A6XX) {
1579 tu_cs_emit_regs(cs,
1580 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1581
1582 tu_cs_emit_regs(cs,
1583 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1584 }
1585
1586 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1587 tu_cs_emit(cs, UNK_2C);
1588
1589 tu_cs_emit_regs(cs,
1590 A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1591
1592 tu_cs_emit_regs(cs,
1593 A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1594
1595 trace_start_binning_ib(&cmd->trace, cs);
1596
1597 /* emit IB to binning drawcmds: */
1598 tu_cs_emit_call(cs, &cmd->draw_cs);
1599
1600 trace_end_binning_ib(&cmd->trace, cs);
1601
1602 /* switching from binning pass to GMEM pass will cause a switch from
1603 * PROGRAM_BINNING to PROGRAM, which invalidates const state (XS_CONST states)
1604 * so make sure these states are re-emitted
1605 * (eventually these states shouldn't exist at all with shader prologue)
1606 * only VS and GS are invalidated, as FS isn't emitted in binning pass,
1607 * and we don't use HW binning when tesselation is used
1608 */
1609 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1610 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1611 CP_SET_DRAW_STATE__0_DISABLE |
1612 CP_SET_DRAW_STATE__0_GROUP_ID(TU_DRAW_STATE_CONST));
1613 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1614 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1615
1616 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1617 tu_cs_emit(cs, UNK_2D);
1618
1619 /* This flush is probably required because the VSC, which produces the
1620 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1621 * visibility stream (without caching) to do draw skipping. The
1622 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1623 * submitted are finished before reading the VSC regs (in
1624 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1625 * part of draws).
1626 */
1627 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_CLEAN);
1628
1629 tu_cs_emit_wfi(cs);
1630
1631 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1632
1633 emit_vsc_overflow_test(cmd, cs);
1634
1635 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1636 tu_cs_emit(cs, 0x0);
1637
1638 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1639 tu_cs_emit(cs, 0x0);
1640 }
1641
1642 static struct tu_draw_state
tu_emit_input_attachments(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,bool gmem)1643 tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
1644 const struct tu_subpass *subpass,
1645 bool gmem)
1646 {
1647 const struct tu_tiling_config *tiling = cmd->state.tiling;
1648
1649 /* note: we can probably emit input attachments just once for the whole
1650 * renderpass, this would avoid emitting both sysmem/gmem versions
1651 *
1652 * emit two texture descriptors for each input, as a workaround for
1653 * d24s8/d32s8, which can be sampled as both float (depth) and integer (stencil)
1654 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1655 * in the pair
1656 * TODO: a smarter workaround
1657 */
1658
1659 if (!subpass->input_count)
1660 return (struct tu_draw_state) {};
1661
1662 struct tu_cs_memory texture;
1663 VkResult result = tu_cs_alloc(&cmd->sub_cs, subpass->input_count * 2,
1664 A6XX_TEX_CONST_DWORDS, &texture);
1665 if (result != VK_SUCCESS) {
1666 vk_command_buffer_set_error(&cmd->vk, result);
1667 return (struct tu_draw_state) {};
1668 }
1669
1670 for (unsigned i = 0; i < subpass->input_count * 2; i++) {
1671 uint32_t a = subpass->input_attachments[i / 2].attachment;
1672 if (a == VK_ATTACHMENT_UNUSED)
1673 continue;
1674
1675 const struct tu_image_view *iview = cmd->state.attachments[a];
1676 const struct tu_render_pass_attachment *att =
1677 &cmd->state.pass->attachments[a];
1678 uint32_t *dst = &texture.map[A6XX_TEX_CONST_DWORDS * i];
1679 uint32_t gmem_offset = tu_attachment_gmem_offset(cmd, att, 0);
1680 uint32_t cpp = att->cpp;
1681
1682 memcpy(dst, iview->view.descriptor, A6XX_TEX_CONST_DWORDS * 4);
1683
1684 /* Cube descriptors require a different sampling instruction in shader,
1685 * however we don't know whether image is a cube or not until the start
1686 * of a renderpass. We have to patch the descriptor to make it compatible
1687 * with how it is sampled in shader.
1688 */
1689 enum a6xx_tex_type tex_type =
1690 (enum a6xx_tex_type)((dst[2] & A6XX_TEX_CONST_2_TYPE__MASK) >>
1691 A6XX_TEX_CONST_2_TYPE__SHIFT);
1692 if (tex_type == A6XX_TEX_CUBE) {
1693 dst[2] &= ~A6XX_TEX_CONST_2_TYPE__MASK;
1694 dst[2] |= A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D);
1695
1696 uint32_t depth = (dst[5] & A6XX_TEX_CONST_5_DEPTH__MASK) >>
1697 A6XX_TEX_CONST_5_DEPTH__SHIFT;
1698 dst[5] &= ~A6XX_TEX_CONST_5_DEPTH__MASK;
1699 dst[5] |= A6XX_TEX_CONST_5_DEPTH(depth * 6);
1700 }
1701
1702 if (i % 2 == 1 && att->format == VK_FORMAT_D24_UNORM_S8_UINT) {
1703 /* note this works because spec says fb and input attachments
1704 * must use identity swizzle
1705 *
1706 * Also we clear swap to WZYX. This is because the view might have
1707 * picked XYZW to work better with border colors.
1708 */
1709 dst[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
1710 A6XX_TEX_CONST_0_SWAP__MASK |
1711 A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
1712 A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
1713 if (!cmd->device->physical_device->info->a6xx.has_z24uint_s8uint) {
1714 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_8_8_8_UINT) |
1715 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_W) |
1716 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
1717 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
1718 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
1719 } else {
1720 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_Z24_UINT_S8_UINT) |
1721 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y) |
1722 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
1723 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
1724 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
1725 }
1726 }
1727
1728 if (i % 2 == 1 && att->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
1729 dst[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
1730 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_UINT);
1731 dst[2] &= ~(A6XX_TEX_CONST_2_PITCHALIGN__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
1732 dst[2] |= A6XX_TEX_CONST_2_PITCH(iview->stencil_pitch);
1733 dst[3] = 0;
1734 dst[4] = iview->stencil_base_addr;
1735 dst[5] = (dst[5] & 0xffff) | iview->stencil_base_addr >> 32;
1736
1737 cpp = att->samples;
1738 gmem_offset = att->gmem_offset_stencil[cmd->state.gmem_layout];
1739 }
1740
1741 if (!gmem || !subpass->input_attachments[i / 2].patch_input_gmem)
1742 continue;
1743
1744 /* patched for gmem */
1745 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
1746 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
1747 dst[2] =
1748 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
1749 A6XX_TEX_CONST_2_PITCH(tiling->tile0.width * cpp);
1750 /* Note: it seems the HW implicitly calculates the array pitch with the
1751 * GMEM tiling, so we don't need to specify the pitch ourselves.
1752 */
1753 dst[3] = 0;
1754 dst[4] = cmd->device->physical_device->gmem_base + gmem_offset;
1755 dst[5] &= A6XX_TEX_CONST_5_DEPTH__MASK;
1756 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
1757 dst[i] = 0;
1758 }
1759
1760 struct tu_cs cs;
1761 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 9);
1762
1763 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3);
1764 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1765 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1766 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1767 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX) |
1768 CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
1769 tu_cs_emit_qw(&cs, texture.iova);
1770
1771 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
1772
1773 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
1774
1775 assert(cs.cur == cs.end); /* validate draw state size */
1776
1777 return ds;
1778 }
1779
1780 static void
tu_set_input_attachments(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass)1781 tu_set_input_attachments(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass)
1782 {
1783 struct tu_cs *cs = &cmd->draw_cs;
1784
1785 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 6);
1786 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
1787 tu_emit_input_attachments(cmd, subpass, true));
1788 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
1789 tu_emit_input_attachments(cmd, subpass, false));
1790 }
1791
1792 static void
tu_trace_start_render_pass(struct tu_cmd_buffer * cmd)1793 tu_trace_start_render_pass(struct tu_cmd_buffer *cmd)
1794 {
1795 if (!u_trace_enabled(&cmd->device->trace_context))
1796 return;
1797
1798 uint32_t load_cpp = 0;
1799 uint32_t store_cpp = 0;
1800 uint32_t clear_cpp = 0;
1801 bool has_depth = false;
1802 char ubwc[MAX_RTS + 3];
1803 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; i++) {
1804 const struct tu_render_pass_attachment *attachment =
1805 &cmd->state.pass->attachments[i];
1806 if (attachment->load) {
1807 load_cpp += attachment->cpp;
1808 }
1809
1810 if (attachment->store) {
1811 store_cpp += attachment->cpp;
1812 }
1813
1814 if (attachment->clear_mask) {
1815 clear_cpp += attachment->cpp;
1816 }
1817
1818 has_depth |= vk_format_has_depth(attachment->format);
1819 }
1820
1821 uint8_t ubwc_len = 0;
1822 const struct tu_subpass *subpass = &cmd->state.pass->subpasses[0];
1823 for (uint32_t i = 0; i < subpass->color_count; i++) {
1824 uint32_t att = subpass->color_attachments[i].attachment;
1825 ubwc[ubwc_len++] = att == VK_ATTACHMENT_UNUSED ? '-'
1826 : cmd->state.attachments[att]->view.ubwc_enabled
1827 ? 'y'
1828 : 'n';
1829 }
1830 if (subpass->depth_used) {
1831 ubwc[ubwc_len++] = '|';
1832 ubwc[ubwc_len++] =
1833 cmd->state.attachments[subpass->depth_stencil_attachment.attachment]
1834 ->view.ubwc_enabled
1835 ? 'y'
1836 : 'n';
1837 }
1838 ubwc[ubwc_len] = '\0';
1839
1840 uint32_t max_samples = 0;
1841 for (uint32_t i = 0; i < cmd->state.pass->subpass_count; i++) {
1842 max_samples = MAX2(max_samples, cmd->state.pass->subpasses[i].samples);
1843 }
1844
1845 trace_start_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer,
1846 cmd->state.tiling, max_samples, clear_cpp,
1847 load_cpp, store_cpp, has_depth, ubwc);
1848 }
1849
1850 template <chip CHIP>
1851 static void
tu_trace_end_render_pass(struct tu_cmd_buffer * cmd,bool gmem)1852 tu_trace_end_render_pass(struct tu_cmd_buffer *cmd, bool gmem)
1853 {
1854 if (!u_trace_enabled(&cmd->device->trace_context))
1855 return;
1856
1857 uint32_t avg_per_sample_bandwidth =
1858 cmd->state.rp.drawcall_bandwidth_per_sample_sum /
1859 MAX2(cmd->state.rp.drawcall_count, 1);
1860
1861 struct u_trace_address addr = {};
1862 if (cmd->state.lrz.image_view) {
1863 struct tu_image *image = cmd->state.lrz.image_view->image;
1864 addr.bo = image->bo;
1865 addr.offset = (image->iova - image->bo->iova) + image->lrz_fc_offset +
1866 offsetof(fd_lrzfc_layout<CHIP>, dir_track);
1867 }
1868
1869 trace_end_render_pass(&cmd->trace, &cmd->cs, gmem,
1870 cmd->state.rp.drawcall_count,
1871 avg_per_sample_bandwidth, cmd->state.lrz.valid,
1872 cmd->state.rp.lrz_disable_reason, addr);
1873 }
1874
1875 static void
tu_emit_renderpass_begin(struct tu_cmd_buffer * cmd)1876 tu_emit_renderpass_begin(struct tu_cmd_buffer *cmd)
1877 {
1878 /* We need to re-emit any draw states that are patched in order for them to
1879 * be correctly added to the per-renderpass patchpoint list, even if they
1880 * are the same as before.
1881 */
1882 if (cmd->state.pass->has_fdm)
1883 cmd->state.dirty |= TU_CMD_DIRTY_FDM;
1884
1885 /* We need to re-emit MSAA at the beginning of every renderpass because it
1886 * isn't part of a draw state that gets automatically re-emitted.
1887 */
1888 BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
1889 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES);
1890 /* PC_PRIMITIVE_CNTL_0 isn't a part of a draw state and may be changed
1891 * by blits.
1892 */
1893 BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
1894 MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE);
1895 }
1896
1897 template <chip CHIP>
1898 static void
tu6_sysmem_render_begin(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)1899 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1900 struct tu_renderpass_result *autotune_result)
1901 {
1902 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1903
1904 tu_lrz_sysmem_begin<CHIP>(cmd, cs);
1905
1906 assert(fb->width > 0 && fb->height > 0);
1907 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1908 tu6_emit_window_offset<CHIP>(cs, 0, 0);
1909
1910 tu6_emit_bin_size<CHIP>(cs, 0, 0, {
1911 .render_mode = RENDERING_PASS,
1912 .force_lrz_write_dis =
1913 !cmd->device->physical_device->info->a6xx.has_lrz_feedback,
1914 .buffers_location = BUFFERS_IN_SYSMEM,
1915 .lrz_feedback_zmode_mask =
1916 cmd->device->physical_device->info->a6xx.has_lrz_feedback
1917 ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
1918 : LRZ_FEEDBACK_NONE,
1919 });
1920
1921 if (CHIP == A7XX) {
1922 tu_cs_emit_regs(cs,
1923 A7XX_RB_UNKNOWN_8812(0x3ff)); // all buffers in sysmem
1924 tu_cs_emit_regs(cs,
1925 A7XX_RB_UNKNOWN_8E06(cmd->device->physical_device->info->a6xx.magic.RB_UNKNOWN_8E06));
1926
1927 tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
1928
1929 tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
1930 tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
1931
1932 tu_cs_emit_regs(cs, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_SYSMEM));
1933 }
1934
1935 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1936 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1937
1938 /* A7XX TODO: blob doesn't use CP_SKIP_IB2_ENABLE_* */
1939 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1940 tu_cs_emit(cs, 0x0);
1941
1942 tu_emit_cache_flush_ccu<CHIP>(cmd, cs, TU_CMD_CCU_SYSMEM);
1943
1944 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1945 tu_cs_emit(cs, 0x1);
1946
1947 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1948 tu_cs_emit(cs, 0x0);
1949
1950 tu_autotune_begin_renderpass<CHIP>(cmd, cs, autotune_result);
1951
1952 tu_cs_sanity_check(cs);
1953 }
1954
1955 template <chip CHIP>
1956 static void
tu6_sysmem_render_end(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)1957 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1958 struct tu_renderpass_result *autotune_result)
1959 {
1960 tu_autotune_end_renderpass<CHIP>(cmd, cs, autotune_result);
1961
1962 /* Do any resolves of the last subpass. These are handled in the
1963 * tile_store_cs in the gmem path.
1964 */
1965 tu6_emit_sysmem_resolves<CHIP>(cmd, cs, cmd->state.subpass);
1966
1967 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1968
1969 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1970 tu_cs_emit(cs, 0x0);
1971
1972 tu_lrz_sysmem_end<CHIP>(cmd, cs);
1973
1974 tu_cs_sanity_check(cs);
1975 }
1976
1977 template <chip CHIP>
1978 static void
tu6_tile_render_begin(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)1979 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1980 struct tu_renderpass_result *autotune_result)
1981 {
1982 struct tu_physical_device *phys_dev = cmd->device->physical_device;
1983 const struct tu_tiling_config *tiling = cmd->state.tiling;
1984 tu_lrz_tiling_begin<CHIP>(cmd, cs);
1985
1986 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1987 tu_cs_emit(cs, 0x0);
1988
1989 if (CHIP >= A7XX) {
1990 tu_cs_emit_regs(cs,
1991 A7XX_RB_UNKNOWN_8812(0x0));
1992 tu_cs_emit_regs(cs,
1993 A7XX_RB_UNKNOWN_8E06(0x0));
1994
1995 tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
1996
1997 tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
1998 tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
1999
2000 tu_cs_emit_regs(cs, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_GMEM));
2001 }
2002
2003 tu_emit_cache_flush_ccu<CHIP>(cmd, cs, TU_CMD_CCU_GMEM);
2004
2005 if (use_hw_binning(cmd)) {
2006 if (!cmd->vsc_initialized) {
2007 tu6_lazy_emit_vsc<CHIP>(cmd, cs);
2008 }
2009
2010 tu6_emit_bin_size<CHIP>(cs, tiling->tile0.width, tiling->tile0.height,
2011 {
2012 .render_mode = BINNING_PASS,
2013 .buffers_location = BUFFERS_IN_GMEM,
2014 .lrz_feedback_zmode_mask =
2015 phys_dev->info->a6xx.has_lrz_feedback
2016 ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
2017 : LRZ_FEEDBACK_NONE
2018 });
2019
2020 tu6_emit_render_cntl<CHIP>(cmd, cmd->state.subpass, cs, true);
2021
2022 tu6_emit_binning_pass<CHIP>(cmd, cs);
2023
2024 tu6_emit_bin_size<CHIP>(
2025 cs, tiling->tile0.width, tiling->tile0.height,
2026 {
2027 .render_mode = RENDERING_PASS,
2028 .force_lrz_write_dis = !phys_dev->info->a6xx.has_lrz_feedback,
2029 .buffers_location = BUFFERS_IN_GMEM,
2030 .lrz_feedback_zmode_mask =
2031 phys_dev->info->a6xx.has_lrz_feedback
2032 ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
2033 : LRZ_FEEDBACK_NONE,
2034 });
2035
2036 tu_cs_emit_regs(cs,
2037 A6XX_VFD_MODE_CNTL(RENDERING_PASS));
2038
2039 if (CHIP == A6XX) {
2040 tu_cs_emit_regs(cs,
2041 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
2042
2043 tu_cs_emit_regs(cs,
2044 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
2045 }
2046
2047 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2048 tu_cs_emit(cs, 0x1);
2049 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_LOCAL, 1);
2050 tu_cs_emit(cs, 0x1);
2051 } else {
2052 tu6_emit_bin_size<CHIP>(
2053 cs, tiling->tile0.width, tiling->tile0.height,
2054 {
2055 .render_mode = RENDERING_PASS,
2056 .force_lrz_write_dis = !phys_dev->info->a6xx.has_lrz_feedback,
2057 .buffers_location = BUFFERS_IN_GMEM,
2058 .lrz_feedback_zmode_mask =
2059 phys_dev->info->a6xx.has_lrz_feedback
2060 ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
2061 : LRZ_FEEDBACK_NONE,
2062 });
2063
2064 if (tiling->binning_possible) {
2065 /* Mark all tiles as visible for tu6_emit_cond_for_load_stores(), since
2066 * the actual binner didn't run.
2067 */
2068 int pipe_count = tiling->pipe_count.width * tiling->pipe_count.height;
2069 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_STATE_REG(0), pipe_count);
2070 for (int i = 0; i < pipe_count; i++)
2071 tu_cs_emit(cs, ~0);
2072 }
2073 }
2074
2075 tu_autotune_begin_renderpass<CHIP>(cmd, cs, autotune_result);
2076
2077 tu_cs_sanity_check(cs);
2078 }
2079
2080 template <chip CHIP>
2081 static void
tu6_render_tile(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t tx,uint32_t ty,uint32_t pipe,uint32_t slot,const struct tu_image_view * fdm)2082 tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2083 uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot,
2084 const struct tu_image_view *fdm)
2085 {
2086 tu6_emit_tile_select<CHIP>(cmd, &cmd->cs, tx, ty, pipe, slot, fdm);
2087
2088 trace_start_draw_ib_gmem(&cmd->trace, &cmd->cs);
2089
2090 /* Primitives that passed all tests are still counted in in each
2091 * tile even with HW binning beforehand. Do not permit it.
2092 */
2093 if (cmd->state.prim_generated_query_running_before_rp)
2094 tu_emit_event_write<CHIP>(cmd, cs, FD_STOP_PRIMITIVE_CTRS);
2095
2096 tu_cs_emit_call(cs, &cmd->draw_cs);
2097
2098 if (cmd->state.prim_generated_query_running_before_rp)
2099 tu_emit_event_write<CHIP>(cmd, cs, FD_START_PRIMITIVE_CTRS);
2100
2101 if (use_hw_binning(cmd)) {
2102 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
2103 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
2104 }
2105
2106 /* Predicate is changed in draw_cs so we have to re-emit it */
2107 if (cmd->state.rp.draw_cs_writes_to_cond_pred)
2108 tu6_emit_cond_for_load_stores(cmd, cs, pipe, slot, false);
2109
2110 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2111 tu_cs_emit(cs, 0x0);
2112
2113 tu_cs_emit_call(cs, &cmd->tile_store_cs);
2114
2115 tu_clone_trace_range(cmd, cs, cmd->trace_renderpass_start,
2116 cmd->trace_renderpass_end);
2117
2118 tu_cs_sanity_check(cs);
2119
2120 trace_end_draw_ib_gmem(&cmd->trace, &cmd->cs);
2121 }
2122
2123 template <chip CHIP>
2124 static void
tu6_tile_render_end(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)2125 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2126 struct tu_renderpass_result *autotune_result)
2127 {
2128 tu_autotune_end_renderpass<CHIP>(cmd, cs, autotune_result);
2129
2130 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
2131
2132 tu_lrz_tiling_end<CHIP>(cmd, cs);
2133
2134 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_BLIT_CACHE);
2135
2136 tu_cs_sanity_check(cs);
2137 }
2138
2139 template <chip CHIP>
2140 static void
tu_cmd_render_tiles(struct tu_cmd_buffer * cmd,struct tu_renderpass_result * autotune_result)2141 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd,
2142 struct tu_renderpass_result *autotune_result)
2143 {
2144 const struct tu_tiling_config *tiling = cmd->state.tiling;
2145 const struct tu_image_view *fdm = NULL;
2146
2147 if (cmd->state.pass->fragment_density_map.attachment != VK_ATTACHMENT_UNUSED) {
2148 fdm = cmd->state.attachments[cmd->state.pass->fragment_density_map.attachment];
2149 }
2150
2151 /* Create gmem stores now (at EndRenderPass time)) because they needed to
2152 * know whether to allow their conditional execution, which was tied to a
2153 * state that was known only at the end of the renderpass. They will be
2154 * called from tu6_render_tile().
2155 */
2156 tu_cs_begin(&cmd->tile_store_cs);
2157 tu6_emit_tile_store<CHIP>(cmd, &cmd->tile_store_cs);
2158 tu_cs_end(&cmd->tile_store_cs);
2159
2160 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
2161
2162 tu6_tile_render_begin<CHIP>(cmd, &cmd->cs, autotune_result);
2163
2164 /* Note: we reverse the order of walking the pipes and tiles on every
2165 * other row, to improve texture cache locality compared to raster order.
2166 */
2167 for (uint32_t py = 0; py < tiling->pipe_count.height; py++) {
2168 uint32_t pipe_row = py * tiling->pipe_count.width;
2169 for (uint32_t pipe_row_i = 0; pipe_row_i < tiling->pipe_count.width; pipe_row_i++) {
2170 uint32_t px;
2171 if (py & 1)
2172 px = tiling->pipe_count.width - 1 - pipe_row_i;
2173 else
2174 px = pipe_row_i;
2175 uint32_t pipe = pipe_row + px;
2176 uint32_t tx1 = px * tiling->pipe0.width;
2177 uint32_t ty1 = py * tiling->pipe0.height;
2178 uint32_t tx2 = MIN2(tx1 + tiling->pipe0.width, tiling->tile_count.width);
2179 uint32_t ty2 = MIN2(ty1 + tiling->pipe0.height, tiling->tile_count.height);
2180 uint32_t tile_row_stride = tx2 - tx1;
2181 uint32_t slot_row = 0;
2182 for (uint32_t ty = ty1; ty < ty2; ty++) {
2183 for (uint32_t tile_row_i = 0; tile_row_i < tile_row_stride; tile_row_i++) {
2184 uint32_t tx;
2185 if (ty & 1)
2186 tx = tile_row_stride - 1 - tile_row_i;
2187 else
2188 tx = tile_row_i;
2189 uint32_t slot = slot_row + tx;
2190 tu6_render_tile<CHIP>(cmd, &cmd->cs, tx1 + tx, ty, pipe, slot, fdm);
2191 }
2192 slot_row += tile_row_stride;
2193 }
2194 }
2195 }
2196
2197 tu6_tile_render_end<CHIP>(cmd, &cmd->cs, autotune_result);
2198
2199 tu_trace_end_render_pass<CHIP>(cmd, true);
2200
2201 /* We have trashed the dynamically-emitted viewport, scissor, and FS params
2202 * via the patchpoints, so we need to re-emit them if they are reused for a
2203 * later render pass.
2204 */
2205 if (cmd->state.pass->has_fdm)
2206 cmd->state.dirty |= TU_CMD_DIRTY_FDM;
2207
2208 /* tu6_render_tile has cloned these tracepoints for each tile */
2209 if (!u_trace_iterator_equal(cmd->trace_renderpass_start, cmd->trace_renderpass_end))
2210 u_trace_disable_event_range(cmd->trace_renderpass_start,
2211 cmd->trace_renderpass_end);
2212
2213 /* Reset the gmem store CS entry lists so that the next render pass
2214 * does its own stores.
2215 */
2216 tu_cs_discard_entries(&cmd->tile_store_cs);
2217 }
2218
2219 template <chip CHIP>
2220 static void
tu_cmd_render_sysmem(struct tu_cmd_buffer * cmd,struct tu_renderpass_result * autotune_result)2221 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd,
2222 struct tu_renderpass_result *autotune_result)
2223 {
2224 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
2225
2226 tu6_sysmem_render_begin<CHIP>(cmd, &cmd->cs, autotune_result);
2227
2228 trace_start_draw_ib_sysmem(&cmd->trace, &cmd->cs);
2229
2230 tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
2231
2232 trace_end_draw_ib_sysmem(&cmd->trace, &cmd->cs);
2233
2234 tu6_sysmem_render_end<CHIP>(cmd, &cmd->cs, autotune_result);
2235
2236 tu_trace_end_render_pass<CHIP>(cmd, false);
2237 }
2238
2239 template <chip CHIP>
2240 void
tu_cmd_render(struct tu_cmd_buffer * cmd_buffer)2241 tu_cmd_render(struct tu_cmd_buffer *cmd_buffer)
2242 {
2243 if (cmd_buffer->state.rp.has_tess)
2244 tu6_lazy_emit_tessfactor_addr<CHIP>(cmd_buffer);
2245
2246 struct tu_renderpass_result *autotune_result = NULL;
2247 if (use_sysmem_rendering(cmd_buffer, &autotune_result))
2248 tu_cmd_render_sysmem<CHIP>(cmd_buffer, autotune_result);
2249 else
2250 tu_cmd_render_tiles<CHIP>(cmd_buffer, autotune_result);
2251
2252 /* Outside of renderpasses we assume all draw states are disabled. We do
2253 * this outside the draw CS for the normal case where 3d gmem stores aren't
2254 * used.
2255 */
2256 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs);
2257
2258 }
2259
tu_reset_render_pass(struct tu_cmd_buffer * cmd_buffer)2260 static void tu_reset_render_pass(struct tu_cmd_buffer *cmd_buffer)
2261 {
2262 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
2263 rendered */
2264 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2265 tu_cs_begin(&cmd_buffer->draw_cs);
2266 tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
2267 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2268
2269 cmd_buffer->state.pass = NULL;
2270 cmd_buffer->state.subpass = NULL;
2271 cmd_buffer->state.framebuffer = NULL;
2272 cmd_buffer->state.attachments = NULL;
2273 cmd_buffer->state.clear_values = NULL;
2274 cmd_buffer->state.gmem_layout = TU_GMEM_LAYOUT_COUNT; /* invalid value to prevent looking up gmem offsets */
2275 memset(&cmd_buffer->state.rp, 0, sizeof(cmd_buffer->state.rp));
2276
2277 /* LRZ is not valid next time we use it */
2278 cmd_buffer->state.lrz.valid = false;
2279 cmd_buffer->state.dirty |= TU_CMD_DIRTY_LRZ;
2280
2281 /* Patchpoints have been executed */
2282 util_dynarray_clear(&cmd_buffer->fdm_bin_patchpoints);
2283 ralloc_free(cmd_buffer->patchpoints_ctx);
2284 cmd_buffer->patchpoints_ctx = NULL;
2285 }
2286
2287 static VkResult
tu_create_cmd_buffer(struct vk_command_pool * pool,VkCommandBufferLevel level,struct vk_command_buffer ** cmd_buffer_out)2288 tu_create_cmd_buffer(struct vk_command_pool *pool,
2289 VkCommandBufferLevel level,
2290 struct vk_command_buffer **cmd_buffer_out)
2291 {
2292 struct tu_device *device =
2293 container_of(pool->base.device, struct tu_device, vk);
2294 struct tu_cmd_buffer *cmd_buffer;
2295
2296 cmd_buffer = (struct tu_cmd_buffer *) vk_zalloc2(
2297 &device->vk.alloc, NULL, sizeof(*cmd_buffer), 8,
2298 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2299
2300 if (cmd_buffer == NULL)
2301 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
2302
2303 VkResult result = vk_command_buffer_init(pool, &cmd_buffer->vk,
2304 &tu_cmd_buffer_ops, level);
2305 if (result != VK_SUCCESS) {
2306 vk_free2(&device->vk.alloc, NULL, cmd_buffer);
2307 return result;
2308 }
2309
2310 cmd_buffer->device = device;
2311
2312 u_trace_init(&cmd_buffer->trace, &device->trace_context);
2313 list_inithead(&cmd_buffer->renderpass_autotune_results);
2314
2315 tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096, "cmd cs");
2316 tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096, "draw cs");
2317 tu_cs_init(&cmd_buffer->tile_store_cs, device, TU_CS_MODE_GROW, 2048, "tile store cs");
2318 tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096, "draw epilogue cs");
2319 tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048, "draw sub cs");
2320 tu_cs_init(&cmd_buffer->pre_chain.draw_cs, device, TU_CS_MODE_GROW, 4096, "prechain draw cs");
2321 tu_cs_init(&cmd_buffer->pre_chain.draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096, "prechain draw epiligoue cs");
2322
2323 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
2324 cmd_buffer->descriptors[i].push_set.base.type = VK_OBJECT_TYPE_DESCRIPTOR_SET;
2325
2326 *cmd_buffer_out = &cmd_buffer->vk;
2327
2328 return VK_SUCCESS;
2329 }
2330
2331 static void
tu_cmd_buffer_destroy(struct vk_command_buffer * vk_cmd_buffer)2332 tu_cmd_buffer_destroy(struct vk_command_buffer *vk_cmd_buffer)
2333 {
2334 struct tu_cmd_buffer *cmd_buffer =
2335 container_of(vk_cmd_buffer, struct tu_cmd_buffer, vk);
2336
2337 tu_cs_finish(&cmd_buffer->cs);
2338 tu_cs_finish(&cmd_buffer->draw_cs);
2339 tu_cs_finish(&cmd_buffer->tile_store_cs);
2340 tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
2341 tu_cs_finish(&cmd_buffer->sub_cs);
2342 tu_cs_finish(&cmd_buffer->pre_chain.draw_cs);
2343 tu_cs_finish(&cmd_buffer->pre_chain.draw_epilogue_cs);
2344
2345 u_trace_fini(&cmd_buffer->trace);
2346
2347 tu_autotune_free_results(cmd_buffer->device, &cmd_buffer->renderpass_autotune_results);
2348
2349 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
2350 if (cmd_buffer->descriptors[i].push_set.layout)
2351 vk_descriptor_set_layout_unref(&cmd_buffer->device->vk,
2352 &cmd_buffer->descriptors[i].push_set.layout->vk);
2353 vk_free(&cmd_buffer->device->vk.alloc,
2354 cmd_buffer->descriptors[i].push_set.mapped_ptr);
2355 }
2356
2357 ralloc_free(cmd_buffer->patchpoints_ctx);
2358 util_dynarray_fini(&cmd_buffer->fdm_bin_patchpoints);
2359
2360 vk_command_buffer_finish(&cmd_buffer->vk);
2361 vk_free2(&cmd_buffer->device->vk.alloc, &cmd_buffer->vk.pool->alloc,
2362 cmd_buffer);
2363 }
2364
2365 static void
tu_reset_cmd_buffer(struct vk_command_buffer * vk_cmd_buffer,UNUSED VkCommandBufferResetFlags flags)2366 tu_reset_cmd_buffer(struct vk_command_buffer *vk_cmd_buffer,
2367 UNUSED VkCommandBufferResetFlags flags)
2368 {
2369 struct tu_cmd_buffer *cmd_buffer =
2370 container_of(vk_cmd_buffer, struct tu_cmd_buffer, vk);
2371
2372 vk_command_buffer_reset(&cmd_buffer->vk);
2373
2374 tu_cs_reset(&cmd_buffer->cs);
2375 tu_cs_reset(&cmd_buffer->draw_cs);
2376 tu_cs_reset(&cmd_buffer->tile_store_cs);
2377 tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
2378 tu_cs_reset(&cmd_buffer->sub_cs);
2379 tu_cs_reset(&cmd_buffer->pre_chain.draw_cs);
2380 tu_cs_reset(&cmd_buffer->pre_chain.draw_epilogue_cs);
2381
2382 tu_autotune_free_results(cmd_buffer->device, &cmd_buffer->renderpass_autotune_results);
2383
2384 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
2385 memset(&cmd_buffer->descriptors[i].sets, 0, sizeof(cmd_buffer->descriptors[i].sets));
2386 if (cmd_buffer->descriptors[i].push_set.layout) {
2387 vk_descriptor_set_layout_unref(&cmd_buffer->device->vk,
2388 &cmd_buffer->descriptors[i].push_set.layout->vk);
2389 }
2390 memset(&cmd_buffer->descriptors[i].push_set, 0, sizeof(cmd_buffer->descriptors[i].push_set));
2391 cmd_buffer->descriptors[i].push_set.base.type = VK_OBJECT_TYPE_DESCRIPTOR_SET;
2392 cmd_buffer->descriptors[i].max_sets_bound = 0;
2393 cmd_buffer->descriptors[i].max_dynamic_offset_size = 0;
2394 }
2395
2396 u_trace_fini(&cmd_buffer->trace);
2397 u_trace_init(&cmd_buffer->trace, &cmd_buffer->device->trace_context);
2398
2399 cmd_buffer->state.max_vbs_bound = 0;
2400
2401 cmd_buffer->vsc_initialized = false;
2402
2403 ralloc_free(cmd_buffer->patchpoints_ctx);
2404 cmd_buffer->patchpoints_ctx = NULL;
2405 util_dynarray_clear(&cmd_buffer->fdm_bin_patchpoints);
2406 }
2407
2408 const struct vk_command_buffer_ops tu_cmd_buffer_ops = {
2409 .create = tu_create_cmd_buffer,
2410 .reset = tu_reset_cmd_buffer,
2411 .destroy = tu_cmd_buffer_destroy,
2412 };
2413
2414 /* Initialize the cache, assuming all necessary flushes have happened but *not*
2415 * invalidations.
2416 */
2417 static void
tu_cache_init(struct tu_cache_state * cache)2418 tu_cache_init(struct tu_cache_state *cache)
2419 {
2420 cache->flush_bits = 0;
2421 cache->pending_flush_bits = TU_CMD_FLAG_ALL_INVALIDATE;
2422 }
2423
2424 /* Unlike the public entrypoint, this doesn't handle cache tracking, and
2425 * tracking the CCU state. It's used for the driver to insert its own command
2426 * buffer in the middle of a submit.
2427 */
2428 VkResult
tu_cmd_buffer_begin(struct tu_cmd_buffer * cmd_buffer,const VkCommandBufferBeginInfo * pBeginInfo)2429 tu_cmd_buffer_begin(struct tu_cmd_buffer *cmd_buffer,
2430 const VkCommandBufferBeginInfo *pBeginInfo)
2431 {
2432 vk_command_buffer_begin(&cmd_buffer->vk, pBeginInfo);
2433
2434 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2435 vk_dynamic_graphics_state_init(&cmd_buffer->vk.dynamic_graphics_state);
2436 cmd_buffer->vk.dynamic_graphics_state.vi = &cmd_buffer->state.vi;
2437 cmd_buffer->vk.dynamic_graphics_state.ms.sample_locations = &cmd_buffer->state.sl;
2438 cmd_buffer->state.index_size = 0xff; /* dirty restart index */
2439 cmd_buffer->state.gmem_layout = TU_GMEM_LAYOUT_COUNT; /* dirty value */
2440
2441 tu_cache_init(&cmd_buffer->state.cache);
2442 tu_cache_init(&cmd_buffer->state.renderpass_cache);
2443 cmd_buffer->usage_flags = pBeginInfo->flags;
2444
2445 tu_cs_begin(&cmd_buffer->cs);
2446 tu_cs_begin(&cmd_buffer->draw_cs);
2447 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2448
2449 return VK_SUCCESS;
2450 }
2451
2452 VKAPI_ATTR VkResult VKAPI_CALL
tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,const VkCommandBufferBeginInfo * pBeginInfo)2453 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
2454 const VkCommandBufferBeginInfo *pBeginInfo)
2455 {
2456 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2457 VkResult result = tu_cmd_buffer_begin(cmd_buffer, pBeginInfo);
2458 if (result != VK_SUCCESS)
2459 return result;
2460
2461 /* setup initial configuration into command buffer */
2462 if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2463 trace_start_cmd_buffer(&cmd_buffer->trace, &cmd_buffer->cs, cmd_buffer);
2464
2465 switch (cmd_buffer->queue_family_index) {
2466 case TU_QUEUE_GENERAL:
2467 TU_CALLX(cmd_buffer->device, tu6_init_hw)(cmd_buffer, &cmd_buffer->cs);
2468 break;
2469 default:
2470 break;
2471 }
2472 } else if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
2473 const bool pass_continue =
2474 pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT;
2475
2476 trace_start_cmd_buffer(&cmd_buffer->trace,
2477 pass_continue ? &cmd_buffer->draw_cs : &cmd_buffer->cs, cmd_buffer);
2478
2479 assert(pBeginInfo->pInheritanceInfo);
2480
2481 cmd_buffer->inherited_pipeline_statistics =
2482 pBeginInfo->pInheritanceInfo->pipelineStatistics;
2483
2484 vk_foreach_struct_const(ext, pBeginInfo->pInheritanceInfo) {
2485 switch (ext->sType) {
2486 case VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT: {
2487 const VkCommandBufferInheritanceConditionalRenderingInfoEXT *cond_rend =
2488 (VkCommandBufferInheritanceConditionalRenderingInfoEXT *) ext;
2489 cmd_buffer->state.predication_active = cond_rend->conditionalRenderingEnable;
2490 break;
2491 }
2492 default:
2493 break;
2494 }
2495 }
2496
2497 if (pass_continue) {
2498 const VkCommandBufferInheritanceRenderingInfo *rendering_info =
2499 vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext,
2500 COMMAND_BUFFER_INHERITANCE_RENDERING_INFO);
2501
2502 if (TU_DEBUG(DYNAMIC)) {
2503 rendering_info =
2504 vk_get_command_buffer_inheritance_rendering_info(cmd_buffer->vk.level,
2505 pBeginInfo);
2506 }
2507
2508 if (rendering_info) {
2509 tu_setup_dynamic_inheritance(cmd_buffer, rendering_info);
2510 cmd_buffer->state.pass = &cmd_buffer->dynamic_pass;
2511 cmd_buffer->state.subpass = &cmd_buffer->dynamic_subpass;
2512 } else {
2513 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2514 cmd_buffer->state.subpass =
2515 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2516 }
2517 tu_fill_render_pass_state(&cmd_buffer->state.vk_rp,
2518 cmd_buffer->state.pass,
2519 cmd_buffer->state.subpass);
2520 vk_cmd_set_cb_attachment_count(&cmd_buffer->vk,
2521 cmd_buffer->state.subpass->color_count);
2522 cmd_buffer->state.dirty |= TU_CMD_DIRTY_SUBPASS;
2523
2524 cmd_buffer->patchpoints_ctx = ralloc_parent(NULL);
2525
2526 /* We can't set the gmem layout here, because the state.pass only has
2527 * to be compatible (same formats/sample counts) with the primary's
2528 * renderpass, rather than exactly equal.
2529 */
2530
2531 tu_lrz_begin_secondary_cmdbuf(cmd_buffer);
2532 } else {
2533 /* When executing in the middle of another command buffer, the CCU
2534 * state is unknown.
2535 */
2536 cmd_buffer->state.ccu_state = TU_CMD_CCU_UNKNOWN;
2537 }
2538 }
2539
2540 return VK_SUCCESS;
2541 }
2542
2543 static struct tu_cs
tu_cmd_dynamic_state(struct tu_cmd_buffer * cmd,uint32_t id,uint32_t size)2544 tu_cmd_dynamic_state(struct tu_cmd_buffer *cmd, uint32_t id, uint32_t size)
2545 {
2546 struct tu_cs cs;
2547
2548 assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
2549 cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size);
2550
2551 /* note: this also avoids emitting draw states before renderpass clears,
2552 * which may use the 3D clear path (for MSAA cases)
2553 */
2554 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)
2555 return cs;
2556
2557 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2558 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
2559
2560 return cs;
2561 }
2562
2563 static void
tu_cmd_end_dynamic_state(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t id)2564 tu_cmd_end_dynamic_state(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2565 uint32_t id)
2566 {
2567 assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
2568 cmd->state.dynamic_state[id] = tu_cs_end_draw_state(&cmd->sub_cs, cs);
2569
2570 /* note: this also avoids emitting draw states before renderpass clears,
2571 * which may use the 3D clear path (for MSAA cases)
2572 */
2573 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)
2574 return;
2575
2576 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2577 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
2578 }
2579
2580 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets,const VkDeviceSize * pSizes,const VkDeviceSize * pStrides)2581 tu_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer,
2582 uint32_t firstBinding,
2583 uint32_t bindingCount,
2584 const VkBuffer *pBuffers,
2585 const VkDeviceSize *pOffsets,
2586 const VkDeviceSize *pSizes,
2587 const VkDeviceSize *pStrides)
2588 {
2589 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2590 struct tu_cs cs;
2591
2592 cmd->state.max_vbs_bound = MAX2(
2593 cmd->state.max_vbs_bound, firstBinding + bindingCount);
2594
2595 if (pStrides) {
2596 vk_cmd_set_vertex_binding_strides(&cmd->vk, firstBinding, bindingCount,
2597 pStrides);
2598 }
2599
2600 cmd->state.vertex_buffers.iova =
2601 tu_cs_draw_state(&cmd->sub_cs, &cs, 4 * cmd->state.max_vbs_bound).iova;
2602
2603 for (uint32_t i = 0; i < bindingCount; i++) {
2604 if (pBuffers[i] == VK_NULL_HANDLE) {
2605 cmd->state.vb[firstBinding + i].base = 0;
2606 cmd->state.vb[firstBinding + i].size = 0;
2607 } else {
2608 struct tu_buffer *buf = tu_buffer_from_handle(pBuffers[i]);
2609 cmd->state.vb[firstBinding + i].base = buf->iova + pOffsets[i];
2610 cmd->state.vb[firstBinding + i].size =
2611 vk_buffer_range(&buf->vk, pOffsets[i], pSizes ? pSizes[i] : VK_WHOLE_SIZE);
2612 }
2613 }
2614
2615 for (uint32_t i = 0; i < cmd->state.max_vbs_bound; i++) {
2616 tu_cs_emit_regs(&cs,
2617 A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
2618 A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
2619 }
2620
2621 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2622 }
2623
2624 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindIndexBuffer2KHR(VkCommandBuffer commandBuffer,VkBuffer buffer,VkDeviceSize offset,VkDeviceSize size,VkIndexType indexType)2625 tu_CmdBindIndexBuffer2KHR(VkCommandBuffer commandBuffer,
2626 VkBuffer buffer,
2627 VkDeviceSize offset,
2628 VkDeviceSize size,
2629 VkIndexType indexType)
2630 {
2631 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2632 VK_FROM_HANDLE(tu_buffer, buf, buffer);
2633
2634 size = buf ? vk_buffer_range(&buf->vk, offset, size) : 0;
2635
2636 uint32_t index_size, index_shift;
2637 uint32_t restart_index = vk_index_to_restart(indexType);
2638
2639 switch (indexType) {
2640 case VK_INDEX_TYPE_UINT16:
2641 index_size = INDEX4_SIZE_16_BIT;
2642 index_shift = 1;
2643 break;
2644 case VK_INDEX_TYPE_UINT32:
2645 index_size = INDEX4_SIZE_32_BIT;
2646 index_shift = 2;
2647 break;
2648 case VK_INDEX_TYPE_UINT8_KHR:
2649 index_size = INDEX4_SIZE_8_BIT;
2650 index_shift = 0;
2651 break;
2652 default:
2653 unreachable("invalid VkIndexType");
2654 }
2655
2656 if (buf) {
2657 /* initialize/update the restart index */
2658 if (cmd->state.index_size != index_size)
2659 tu_cs_emit_regs(&cmd->draw_cs, A6XX_PC_RESTART_INDEX(restart_index));
2660
2661 cmd->state.index_va = buf->iova + offset;
2662 cmd->state.max_index_count = size >> index_shift;
2663 cmd->state.index_size = index_size;
2664 } else {
2665 cmd->state.index_va = 0;
2666 cmd->state.max_index_count = 0;
2667 cmd->state.index_size = 0;
2668 }
2669 }
2670
2671 template <chip CHIP>
2672 static void
tu6_emit_descriptor_sets(struct tu_cmd_buffer * cmd,VkPipelineBindPoint bind_point)2673 tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
2674 VkPipelineBindPoint bind_point)
2675 {
2676 struct tu_descriptor_state *descriptors_state =
2677 tu_get_descriptors_state(cmd, bind_point);
2678 uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
2679 struct tu_cs *cs, state_cs;
2680
2681 if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) {
2682 sp_bindless_base_reg = __SP_BINDLESS_BASE_DESCRIPTOR<CHIP>(0, {}).reg;
2683 hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
2684
2685 if (CHIP == A6XX) {
2686 cmd->state.desc_sets =
2687 tu_cs_draw_state(&cmd->sub_cs, &state_cs,
2688 4 + 4 * descriptors_state->max_sets_bound +
2689 (descriptors_state->max_dynamic_offset_size ? 6 : 0));
2690 } else {
2691 cmd->state.desc_sets =
2692 tu_cs_draw_state(&cmd->sub_cs, &state_cs,
2693 3 + 2 * descriptors_state->max_sets_bound +
2694 (descriptors_state->max_dynamic_offset_size ? 3 : 0));
2695 }
2696 cs = &state_cs;
2697 } else {
2698 assert(bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
2699
2700 sp_bindless_base_reg = __SP_CS_BINDLESS_BASE_DESCRIPTOR<CHIP>(0, {}).reg;
2701 hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2702
2703 cs = &cmd->cs;
2704 }
2705
2706 tu_cs_emit_pkt4(cs, sp_bindless_base_reg, 2 * descriptors_state->max_sets_bound);
2707 tu_cs_emit_array(cs, (const uint32_t*)descriptors_state->set_iova, 2 * descriptors_state->max_sets_bound);
2708 if (CHIP == A6XX) {
2709 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg, 2 * descriptors_state->max_sets_bound);
2710 tu_cs_emit_array(cs, (const uint32_t*)descriptors_state->set_iova, 2 * descriptors_state->max_sets_bound);
2711 }
2712
2713 /* Dynamic descriptors get the reserved descriptor set. */
2714 if (descriptors_state->max_dynamic_offset_size) {
2715 int reserved_set_idx = cmd->device->physical_device->reserved_set_idx;
2716 assert(reserved_set_idx >= 0); /* reserved set must be bound */
2717
2718 tu_cs_emit_pkt4(cs, sp_bindless_base_reg + reserved_set_idx * 2, 2);
2719 tu_cs_emit_qw(cs, descriptors_state->set_iova[reserved_set_idx]);
2720 if (CHIP == A6XX) {
2721 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg + reserved_set_idx * 2, 2);
2722 tu_cs_emit_qw(cs, descriptors_state->set_iova[reserved_set_idx]);
2723 }
2724 }
2725
2726 tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
2727 .cs_bindless = bind_point == VK_PIPELINE_BIND_POINT_COMPUTE ? CHIP == A6XX ? 0x1f : 0xff : 0,
2728 .gfx_bindless = bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ? CHIP == A6XX ? 0x1f : 0xff : 0,
2729 ));
2730
2731 if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) {
2732 assert(cs->cur == cs->end); /* validate draw state size */
2733 /* note: this also avoids emitting draw states before renderpass clears,
2734 * which may use the 3D clear path (for MSAA cases)
2735 */
2736 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
2737 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2738 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
2739 }
2740 }
2741 }
2742
2743 /* We lazily emit the draw state for desciptor sets at draw time, so that we can
2744 * batch together multiple tu_CmdBindDescriptorSets() calls. ANGLE and zink
2745 * will often emit multiple bind calls in a draw.
2746 */
2747 static void
tu_dirty_desc_sets(struct tu_cmd_buffer * cmd,VkPipelineBindPoint pipelineBindPoint)2748 tu_dirty_desc_sets(struct tu_cmd_buffer *cmd,
2749 VkPipelineBindPoint pipelineBindPoint)
2750 {
2751 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE) {
2752 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESC_SETS;
2753 } else {
2754 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS);
2755 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS;
2756 }
2757 }
2758
2759 static void
tu_bind_descriptor_sets(struct tu_cmd_buffer * cmd,const VkBindDescriptorSetsInfoKHR * info,VkPipelineBindPoint bind_point)2760 tu_bind_descriptor_sets(struct tu_cmd_buffer *cmd,
2761 const VkBindDescriptorSetsInfoKHR *info,
2762 VkPipelineBindPoint bind_point)
2763 {
2764 VK_FROM_HANDLE(tu_pipeline_layout, layout, info->layout);
2765 unsigned dyn_idx = 0;
2766
2767 struct tu_descriptor_state *descriptors_state =
2768 tu_get_descriptors_state(cmd, bind_point);
2769
2770 descriptors_state->max_sets_bound =
2771 MAX2(descriptors_state->max_sets_bound,
2772 info->firstSet + info->descriptorSetCount);
2773
2774 unsigned dynamic_offset_offset = 0;
2775 for (unsigned i = 0; i < info->firstSet; i++) {
2776 dynamic_offset_offset += layout->set[i].layout->dynamic_offset_size;
2777 }
2778
2779 for (unsigned i = 0; i < info->descriptorSetCount; ++i) {
2780 unsigned idx = i + info->firstSet;
2781 VK_FROM_HANDLE(tu_descriptor_set, set, info->pDescriptorSets[i]);
2782
2783 descriptors_state->sets[idx] = set;
2784 descriptors_state->set_iova[idx] = set ?
2785 (set->va | BINDLESS_DESCRIPTOR_64B) : 0;
2786
2787 if (!set)
2788 continue;
2789
2790 if (set->layout->has_inline_uniforms)
2791 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
2792
2793 if (!set->layout->dynamic_offset_size)
2794 continue;
2795
2796 uint32_t *src = set->dynamic_descriptors;
2797 uint32_t *dst = descriptors_state->dynamic_descriptors +
2798 dynamic_offset_offset / 4;
2799 for (unsigned j = 0; j < set->layout->binding_count; j++) {
2800 struct tu_descriptor_set_binding_layout *binding =
2801 &set->layout->binding[j];
2802 if (binding->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2803 binding->type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2804 for (unsigned k = 0; k < binding->array_size; k++, dyn_idx++) {
2805 assert(dyn_idx < info->dynamicOffsetCount);
2806 uint32_t offset = info->pDynamicOffsets[dyn_idx];
2807 memcpy(dst, src, binding->size);
2808
2809 if (binding->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC) {
2810 /* Note: we can assume here that the addition won't roll
2811 * over and change the SIZE field.
2812 */
2813 uint64_t va = src[0] | ((uint64_t)src[1] << 32);
2814 va += offset;
2815 dst[0] = va;
2816 dst[1] = va >> 32;
2817 } else {
2818 uint32_t *dst_desc = dst;
2819 for (unsigned i = 0;
2820 i < binding->size / (4 * A6XX_TEX_CONST_DWORDS);
2821 i++, dst_desc += A6XX_TEX_CONST_DWORDS) {
2822 /* Note: A6XX_TEX_CONST_5_DEPTH is always 0 */
2823 uint64_t va = dst_desc[4] | ((uint64_t)dst_desc[5] << 32);
2824 uint32_t desc_offset =
2825 (dst_desc[2] &
2826 A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK) >>
2827 A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT;
2828
2829 /* Use descriptor's format to determine the shift amount
2830 * that's to be used on the offset value.
2831 */
2832 uint32_t format = (dst_desc[0] &
2833 A6XX_TEX_CONST_0_FMT__MASK) >>
2834 A6XX_TEX_CONST_0_FMT__SHIFT;
2835 unsigned offset_shift;
2836 switch (format) {
2837 case FMT6_16_UINT:
2838 offset_shift = 1;
2839 break;
2840 case FMT6_32_UINT:
2841 offset_shift = 2;
2842 break;
2843 case FMT6_8_UINT:
2844 default:
2845 offset_shift = 0;
2846 break;
2847 }
2848
2849 va += desc_offset << offset_shift;
2850 va += offset;
2851 unsigned new_offset = (va & 0x3f) >> offset_shift;
2852 va &= ~0x3full;
2853 dst_desc[4] = va;
2854 dst_desc[5] = va >> 32;
2855 dst_desc[2] =
2856 (dst_desc[2] & ~A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK) |
2857 A6XX_TEX_CONST_2_STARTOFFSETTEXELS(new_offset);
2858 }
2859 }
2860
2861 dst += binding->size / 4;
2862 src += binding->size / 4;
2863 }
2864 }
2865 }
2866
2867 dynamic_offset_offset += layout->set[idx].layout->dynamic_offset_size;
2868 }
2869 assert(dyn_idx == info->dynamicOffsetCount);
2870
2871 if (dynamic_offset_offset) {
2872 descriptors_state->max_dynamic_offset_size =
2873 MAX2(descriptors_state->max_dynamic_offset_size, dynamic_offset_offset);
2874
2875 /* allocate and fill out dynamic descriptor set */
2876 struct tu_cs_memory dynamic_desc_set;
2877 int reserved_set_idx = cmd->device->physical_device->reserved_set_idx;
2878 VkResult result =
2879 tu_cs_alloc(&cmd->sub_cs,
2880 descriptors_state->max_dynamic_offset_size /
2881 (4 * A6XX_TEX_CONST_DWORDS),
2882 A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
2883 if (result != VK_SUCCESS) {
2884 vk_command_buffer_set_error(&cmd->vk, result);
2885 return;
2886 }
2887
2888 memcpy(dynamic_desc_set.map, descriptors_state->dynamic_descriptors,
2889 descriptors_state->max_dynamic_offset_size);
2890 assert(reserved_set_idx >= 0); /* reserved set must be bound */
2891 descriptors_state->set_iova[reserved_set_idx] = dynamic_desc_set.iova | BINDLESS_DESCRIPTOR_64B;
2892 }
2893
2894 tu_dirty_desc_sets(cmd, bind_point);
2895 }
2896
2897 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorSets2KHR(VkCommandBuffer commandBuffer,const VkBindDescriptorSetsInfoKHR * pBindDescriptorSetsInfo)2898 tu_CmdBindDescriptorSets2KHR(
2899 VkCommandBuffer commandBuffer,
2900 const VkBindDescriptorSetsInfoKHR *pBindDescriptorSetsInfo)
2901 {
2902 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2903
2904 if (pBindDescriptorSetsInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) {
2905 tu_bind_descriptor_sets(cmd, pBindDescriptorSetsInfo,
2906 VK_PIPELINE_BIND_POINT_COMPUTE);
2907 }
2908
2909 if (pBindDescriptorSetsInfo->stageFlags & VK_SHADER_STAGE_ALL_GRAPHICS) {
2910 tu_bind_descriptor_sets(cmd, pBindDescriptorSetsInfo,
2911 VK_PIPELINE_BIND_POINT_GRAPHICS);
2912 }
2913 }
2914
2915 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorBuffersEXT(VkCommandBuffer commandBuffer,uint32_t bufferCount,const VkDescriptorBufferBindingInfoEXT * pBindingInfos)2916 tu_CmdBindDescriptorBuffersEXT(
2917 VkCommandBuffer commandBuffer,
2918 uint32_t bufferCount,
2919 const VkDescriptorBufferBindingInfoEXT *pBindingInfos)
2920 {
2921 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2922
2923 for (unsigned i = 0; i < bufferCount; i++)
2924 cmd->state.descriptor_buffer_iova[i] = pBindingInfos[i].address;
2925 }
2926
2927 static void
tu_set_descriptor_buffer_offsets(struct tu_cmd_buffer * cmd,const VkSetDescriptorBufferOffsetsInfoEXT * info,VkPipelineBindPoint bind_point)2928 tu_set_descriptor_buffer_offsets(
2929 struct tu_cmd_buffer *cmd,
2930 const VkSetDescriptorBufferOffsetsInfoEXT *info,
2931 VkPipelineBindPoint bind_point)
2932 {
2933 VK_FROM_HANDLE(tu_pipeline_layout, layout, info->layout);
2934
2935 struct tu_descriptor_state *descriptors_state =
2936 tu_get_descriptors_state(cmd, bind_point);
2937
2938 descriptors_state->max_sets_bound = MAX2(descriptors_state->max_sets_bound,
2939 info->firstSet + info->setCount);
2940
2941 for (unsigned i = 0; i < info->setCount; ++i) {
2942 unsigned idx = i + info->firstSet;
2943 struct tu_descriptor_set_layout *set_layout = layout->set[idx].layout;
2944
2945 descriptors_state->set_iova[idx] =
2946 (cmd->state.descriptor_buffer_iova[info->pBufferIndices[i]] +
2947 info->pOffsets[i]) |
2948 BINDLESS_DESCRIPTOR_64B;
2949
2950 if (set_layout->has_inline_uniforms)
2951 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
2952 }
2953
2954 tu_dirty_desc_sets(cmd, bind_point);
2955 }
2956
2957 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDescriptorBufferOffsets2EXT(VkCommandBuffer commandBuffer,const VkSetDescriptorBufferOffsetsInfoEXT * pSetDescriptorBufferOffsetsInfo)2958 tu_CmdSetDescriptorBufferOffsets2EXT(
2959 VkCommandBuffer commandBuffer,
2960 const VkSetDescriptorBufferOffsetsInfoEXT *pSetDescriptorBufferOffsetsInfo)
2961 {
2962 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2963
2964 if (pSetDescriptorBufferOffsetsInfo->stageFlags &
2965 VK_SHADER_STAGE_COMPUTE_BIT) {
2966 tu_set_descriptor_buffer_offsets(cmd, pSetDescriptorBufferOffsetsInfo,
2967 VK_PIPELINE_BIND_POINT_COMPUTE);
2968 }
2969
2970 if (pSetDescriptorBufferOffsetsInfo->stageFlags &
2971 VK_SHADER_STAGE_ALL_GRAPHICS) {
2972 tu_set_descriptor_buffer_offsets(cmd, pSetDescriptorBufferOffsetsInfo,
2973 VK_PIPELINE_BIND_POINT_GRAPHICS);
2974 }
2975 }
2976
2977 static void
tu_bind_descriptor_buffer_embedded_samplers(struct tu_cmd_buffer * cmd,const VkBindDescriptorBufferEmbeddedSamplersInfoEXT * info,VkPipelineBindPoint bind_point)2978 tu_bind_descriptor_buffer_embedded_samplers(
2979 struct tu_cmd_buffer *cmd,
2980 const VkBindDescriptorBufferEmbeddedSamplersInfoEXT *info,
2981 VkPipelineBindPoint bind_point)
2982 {
2983 VK_FROM_HANDLE(tu_pipeline_layout, layout, info->layout);
2984
2985 struct tu_descriptor_set_layout *set_layout =
2986 layout->set[info->set].layout;
2987
2988 struct tu_descriptor_state *descriptors_state =
2989 tu_get_descriptors_state(cmd, bind_point);
2990
2991 descriptors_state->max_sets_bound =
2992 MAX2(descriptors_state->max_sets_bound, info->set + 1);
2993
2994 descriptors_state->set_iova[info->set] =
2995 set_layout->embedded_samplers->iova | BINDLESS_DESCRIPTOR_64B;
2996
2997 tu_dirty_desc_sets(cmd, bind_point);
2998 }
2999
3000 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorBufferEmbeddedSamplers2EXT(VkCommandBuffer commandBuffer,const VkBindDescriptorBufferEmbeddedSamplersInfoEXT * pBindDescriptorBufferEmbeddedSamplersInfo)3001 tu_CmdBindDescriptorBufferEmbeddedSamplers2EXT(
3002 VkCommandBuffer commandBuffer,
3003 const VkBindDescriptorBufferEmbeddedSamplersInfoEXT
3004 *pBindDescriptorBufferEmbeddedSamplersInfo)
3005 {
3006 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3007
3008 if (pBindDescriptorBufferEmbeddedSamplersInfo->stageFlags &
3009 VK_SHADER_STAGE_COMPUTE_BIT) {
3010 tu_bind_descriptor_buffer_embedded_samplers(
3011 cmd, pBindDescriptorBufferEmbeddedSamplersInfo,
3012 VK_PIPELINE_BIND_POINT_COMPUTE);
3013 }
3014
3015 if (pBindDescriptorBufferEmbeddedSamplersInfo->stageFlags &
3016 VK_SHADER_STAGE_ALL_GRAPHICS) {
3017 tu_bind_descriptor_buffer_embedded_samplers(
3018 cmd, pBindDescriptorBufferEmbeddedSamplersInfo,
3019 VK_PIPELINE_BIND_POINT_GRAPHICS);
3020 }
3021 }
3022
3023 static enum VkResult
tu_push_descriptor_set_update_layout(struct tu_device * device,struct tu_descriptor_set * set,struct tu_descriptor_set_layout * layout)3024 tu_push_descriptor_set_update_layout(struct tu_device *device,
3025 struct tu_descriptor_set *set,
3026 struct tu_descriptor_set_layout *layout)
3027 {
3028 if (set->layout == layout)
3029 return VK_SUCCESS;
3030
3031 if (set->layout)
3032 vk_descriptor_set_layout_unref(&device->vk, &set->layout->vk);
3033 vk_descriptor_set_layout_ref(&layout->vk);
3034 set->layout = layout;
3035
3036 if (set->host_size < layout->size) {
3037 void *new_buf =
3038 vk_realloc(&device->vk.alloc, set->mapped_ptr, layout->size, 8,
3039 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3040 if (!new_buf)
3041 return VK_ERROR_OUT_OF_HOST_MEMORY;
3042 set->mapped_ptr = (uint32_t *) new_buf;
3043 set->host_size = layout->size;
3044 }
3045 return VK_SUCCESS;
3046 }
3047
3048 static void
tu_push_descriptor_set(struct tu_cmd_buffer * cmd,const VkPushDescriptorSetInfoKHR * info,VkPipelineBindPoint bind_point)3049 tu_push_descriptor_set(struct tu_cmd_buffer *cmd,
3050 const VkPushDescriptorSetInfoKHR *info,
3051 VkPipelineBindPoint bind_point)
3052 {
3053 VK_FROM_HANDLE(tu_pipeline_layout, pipe_layout, info->layout);
3054 struct tu_descriptor_set_layout *layout =
3055 pipe_layout->set[info->set].layout;
3056 struct tu_descriptor_set *set =
3057 &tu_get_descriptors_state(cmd, bind_point)->push_set;
3058
3059 struct tu_cs_memory set_mem;
3060 VkResult result = tu_cs_alloc(&cmd->sub_cs,
3061 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS * 4),
3062 A6XX_TEX_CONST_DWORDS, &set_mem);
3063 if (result != VK_SUCCESS) {
3064 vk_command_buffer_set_error(&cmd->vk, result);
3065 return;
3066 }
3067
3068 result = tu_push_descriptor_set_update_layout(cmd->device, set, layout);
3069 if (result != VK_SUCCESS) {
3070 vk_command_buffer_set_error(&cmd->vk, result);
3071 return;
3072 }
3073
3074 tu_update_descriptor_sets(cmd->device, tu_descriptor_set_to_handle(set),
3075 info->descriptorWriteCount,
3076 info->pDescriptorWrites, 0, NULL);
3077
3078 memcpy(set_mem.map, set->mapped_ptr, layout->size);
3079 set->va = set_mem.iova;
3080
3081 const VkDescriptorSet desc_set[] = { tu_descriptor_set_to_handle(set) };
3082 vk_common_CmdBindDescriptorSets(tu_cmd_buffer_to_handle(cmd), bind_point,
3083 info->layout, info->set, 1, desc_set, 0,
3084 NULL);
3085 }
3086
3087 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushDescriptorSet2KHR(VkCommandBuffer commandBuffer,const VkPushDescriptorSetInfoKHR * pPushDescriptorSetInfo)3088 tu_CmdPushDescriptorSet2KHR(
3089 VkCommandBuffer commandBuffer,
3090 const VkPushDescriptorSetInfoKHR *pPushDescriptorSetInfo)
3091 {
3092 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3093
3094 if (pPushDescriptorSetInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) {
3095 tu_push_descriptor_set(cmd, pPushDescriptorSetInfo,
3096 VK_PIPELINE_BIND_POINT_COMPUTE);
3097 }
3098
3099 if (pPushDescriptorSetInfo->stageFlags & VK_SHADER_STAGE_ALL_GRAPHICS) {
3100 tu_push_descriptor_set(cmd, pPushDescriptorSetInfo,
3101 VK_PIPELINE_BIND_POINT_GRAPHICS);
3102 }
3103 }
3104
3105 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushDescriptorSetWithTemplate2KHR(VkCommandBuffer commandBuffer,const VkPushDescriptorSetWithTemplateInfoKHR * pPushDescriptorSetWithTemplateInfo)3106 tu_CmdPushDescriptorSetWithTemplate2KHR(
3107 VkCommandBuffer commandBuffer,
3108 const VkPushDescriptorSetWithTemplateInfoKHR
3109 *pPushDescriptorSetWithTemplateInfo)
3110 {
3111 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3112 VK_FROM_HANDLE(tu_pipeline_layout, pipe_layout,
3113 pPushDescriptorSetWithTemplateInfo->layout);
3114 VK_FROM_HANDLE(
3115 tu_descriptor_update_template, templ,
3116 pPushDescriptorSetWithTemplateInfo->descriptorUpdateTemplate);
3117 struct tu_descriptor_set_layout *layout =
3118 pipe_layout->set[pPushDescriptorSetWithTemplateInfo->set].layout;
3119 struct tu_descriptor_set *set =
3120 &tu_get_descriptors_state(cmd, templ->bind_point)->push_set;
3121
3122 struct tu_cs_memory set_mem;
3123 VkResult result = tu_cs_alloc(&cmd->sub_cs,
3124 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS * 4),
3125 A6XX_TEX_CONST_DWORDS, &set_mem);
3126 if (result != VK_SUCCESS) {
3127 vk_command_buffer_set_error(&cmd->vk, result);
3128 return;
3129 }
3130
3131 result = tu_push_descriptor_set_update_layout(cmd->device, set, layout);
3132 if (result != VK_SUCCESS) {
3133 vk_command_buffer_set_error(&cmd->vk, result);
3134 return;
3135 }
3136
3137 tu_update_descriptor_set_with_template(
3138 cmd->device, set,
3139 pPushDescriptorSetWithTemplateInfo->descriptorUpdateTemplate,
3140 pPushDescriptorSetWithTemplateInfo->pData);
3141
3142 memcpy(set_mem.map, set->mapped_ptr, layout->size);
3143 set->va = set_mem.iova;
3144
3145 const VkDescriptorSet desc_set[] = { tu_descriptor_set_to_handle(set) };
3146 vk_common_CmdBindDescriptorSets(
3147 tu_cmd_buffer_to_handle(cmd), templ->bind_point,
3148 pPushDescriptorSetWithTemplateInfo->layout,
3149 pPushDescriptorSetWithTemplateInfo->set, 1, desc_set, 0, NULL);
3150 }
3151
3152 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets,const VkDeviceSize * pSizes)3153 tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
3154 uint32_t firstBinding,
3155 uint32_t bindingCount,
3156 const VkBuffer *pBuffers,
3157 const VkDeviceSize *pOffsets,
3158 const VkDeviceSize *pSizes)
3159 {
3160 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3161 struct tu_cs *cs = &cmd->draw_cs;
3162
3163 /* using COND_REG_EXEC for xfb commands matches the blob behavior
3164 * presumably there isn't any benefit using a draw state when the
3165 * condition is (SYSMEM | BINNING)
3166 */
3167 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
3168 CP_COND_REG_EXEC_0_SYSMEM |
3169 CP_COND_REG_EXEC_0_BINNING);
3170
3171 for (uint32_t i = 0; i < bindingCount; i++) {
3172 VK_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
3173 uint64_t iova = buf->iova + pOffsets[i];
3174 uint32_t size = buf->bo->size - (iova - buf->bo->iova);
3175 uint32_t idx = i + firstBinding;
3176
3177 if (pSizes && pSizes[i] != VK_WHOLE_SIZE)
3178 size = pSizes[i];
3179
3180 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
3181 uint32_t offset = iova & 0x1f;
3182 iova &= ~(uint64_t) 0x1f;
3183
3184 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE(idx), 3);
3185 tu_cs_emit_qw(cs, iova);
3186 tu_cs_emit(cs, size + offset);
3187
3188 cmd->state.streamout_offset[idx] = offset;
3189 }
3190
3191 tu_cond_exec_end(cs);
3192 }
3193
3194 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,uint32_t firstCounterBuffer,uint32_t counterBufferCount,const VkBuffer * pCounterBuffers,const VkDeviceSize * pCounterBufferOffsets)3195 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
3196 uint32_t firstCounterBuffer,
3197 uint32_t counterBufferCount,
3198 const VkBuffer *pCounterBuffers,
3199 const VkDeviceSize *pCounterBufferOffsets)
3200 {
3201 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3202 struct tu_cs *cs = &cmd->draw_cs;
3203
3204 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
3205 CP_COND_REG_EXEC_0_SYSMEM |
3206 CP_COND_REG_EXEC_0_BINNING);
3207
3208 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
3209
3210 /* TODO: only update offset for active buffers */
3211 for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++)
3212 tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i]));
3213
3214 for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) {
3215 uint32_t idx = firstCounterBuffer + i;
3216 uint32_t offset = cmd->state.streamout_offset[idx];
3217 uint64_t counter_buffer_offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0u;
3218
3219 if (!pCounterBuffers[i])
3220 continue;
3221
3222 VK_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
3223
3224 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
3225 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
3226 CP_MEM_TO_REG_0_UNK31 |
3227 CP_MEM_TO_REG_0_CNT(1));
3228 tu_cs_emit_qw(cs, buf->iova + counter_buffer_offset);
3229
3230 if (offset) {
3231 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
3232 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
3233 CP_REG_RMW_0_SRC1_ADD);
3234 tu_cs_emit(cs, 0xffffffff);
3235 tu_cs_emit(cs, offset);
3236 }
3237 }
3238
3239 tu_cond_exec_end(cs);
3240 }
3241
3242 template <chip CHIP>
3243 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,uint32_t firstCounterBuffer,uint32_t counterBufferCount,const VkBuffer * pCounterBuffers,const VkDeviceSize * pCounterBufferOffsets)3244 tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
3245 uint32_t firstCounterBuffer,
3246 uint32_t counterBufferCount,
3247 const VkBuffer *pCounterBuffers,
3248 const VkDeviceSize *pCounterBufferOffsets)
3249 {
3250 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3251 struct tu_cs *cs = &cmd->draw_cs;
3252
3253 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
3254 CP_COND_REG_EXEC_0_SYSMEM |
3255 CP_COND_REG_EXEC_0_BINNING);
3256
3257 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
3258
3259 /* TODO: only flush buffers that need to be flushed */
3260 for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3261 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
3262 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
3263 tu_cs_emit_qw(cs, global_iova_arr(cmd, flush_base, i));
3264 tu_emit_event_write<CHIP>(cmd, cs, (enum fd_gpu_event) (FD_FLUSH_SO_0 + i));
3265 }
3266
3267 for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) {
3268 uint32_t idx = firstCounterBuffer + i;
3269 uint32_t offset = cmd->state.streamout_offset[idx];
3270 uint64_t counter_buffer_offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0u;
3271
3272 if (!pCounterBuffers[i])
3273 continue;
3274
3275 VK_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
3276
3277 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
3278 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
3279 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
3280 COND(CHIP == A6XX, CP_MEM_TO_REG_0_SHIFT_BY_2) |
3281 0x40000 | /* ??? */
3282 CP_MEM_TO_REG_0_UNK31 |
3283 CP_MEM_TO_REG_0_CNT(1));
3284 tu_cs_emit_qw(cs, global_iova_arr(cmd, flush_base, idx));
3285
3286 if (offset) {
3287 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
3288 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
3289 CP_REG_RMW_0_SRC1_ADD);
3290 tu_cs_emit(cs, 0xffffffff);
3291 tu_cs_emit(cs, -offset);
3292 }
3293
3294 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
3295 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
3296 CP_REG_TO_MEM_0_CNT(1));
3297 tu_cs_emit_qw(cs, buf->iova + counter_buffer_offset);
3298 }
3299
3300 tu_cond_exec_end(cs);
3301
3302 cmd->state.rp.xfb_used = true;
3303 }
3304 TU_GENX(tu_CmdEndTransformFeedbackEXT);
3305
3306 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushConstants2KHR(VkCommandBuffer commandBuffer,const VkPushConstantsInfoKHR * pPushConstantsInfo)3307 tu_CmdPushConstants2KHR(VkCommandBuffer commandBuffer,
3308 const VkPushConstantsInfoKHR *pPushConstantsInfo)
3309 {
3310 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3311 memcpy((char *) cmd->push_constants + pPushConstantsInfo->offset,
3312 pPushConstantsInfo->pValues, pPushConstantsInfo->size);
3313 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
3314 }
3315
3316 /* Clean everything which has been made available but we haven't actually
3317 * cleaned yet.
3318 */
3319 static void
tu_clean_all_pending(struct tu_cache_state * cache)3320 tu_clean_all_pending(struct tu_cache_state *cache)
3321 {
3322 cache->flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_CLEAN;
3323 cache->pending_flush_bits &= ~TU_CMD_FLAG_ALL_CLEAN;
3324 }
3325
3326 template <chip CHIP>
3327 VKAPI_ATTR VkResult VKAPI_CALL
tu_EndCommandBuffer(VkCommandBuffer commandBuffer)3328 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
3329 {
3330 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3331
3332 /* We currently flush CCU at the end of the command buffer, like
3333 * what the blob does. There's implicit synchronization around every
3334 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
3335 * know yet if this command buffer will be the last in the submit so we
3336 * have to defensively flush everything else.
3337 *
3338 * TODO: We could definitely do better than this, since these flushes
3339 * aren't required by Vulkan, but we'd need kernel support to do that.
3340 * Ideally, we'd like the kernel to flush everything afterwards, so that we
3341 * wouldn't have to do any flushes here, and when submitting multiple
3342 * command buffers there wouldn't be any unnecessary flushes in between.
3343 */
3344 if (cmd_buffer->state.pass) {
3345 tu_clean_all_pending(&cmd_buffer->state.renderpass_cache);
3346 tu_emit_cache_flush_renderpass<CHIP>(cmd_buffer);
3347
3348 trace_end_cmd_buffer(&cmd_buffer->trace, &cmd_buffer->draw_cs);
3349 } else {
3350 tu_clean_all_pending(&cmd_buffer->state.cache);
3351 cmd_buffer->state.cache.flush_bits |=
3352 TU_CMD_FLAG_CCU_CLEAN_COLOR |
3353 TU_CMD_FLAG_CCU_CLEAN_DEPTH;
3354 tu_emit_cache_flush<CHIP>(cmd_buffer);
3355
3356 trace_end_cmd_buffer(&cmd_buffer->trace, &cmd_buffer->cs);
3357 }
3358
3359 tu_cs_end(&cmd_buffer->cs);
3360 tu_cs_end(&cmd_buffer->draw_cs);
3361 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3362
3363 return vk_command_buffer_end(&cmd_buffer->vk);
3364 }
3365 TU_GENX(tu_EndCommandBuffer);
3366
3367 static void
tu_bind_vs(struct tu_cmd_buffer * cmd,struct tu_shader * vs)3368 tu_bind_vs(struct tu_cmd_buffer *cmd, struct tu_shader *vs)
3369 {
3370 cmd->state.shaders[MESA_SHADER_VERTEX] = vs;
3371 }
3372
3373 static void
tu_bind_tcs(struct tu_cmd_buffer * cmd,struct tu_shader * tcs)3374 tu_bind_tcs(struct tu_cmd_buffer *cmd, struct tu_shader *tcs)
3375 {
3376 cmd->state.shaders[MESA_SHADER_TESS_CTRL] = tcs;
3377 }
3378
3379 static void
tu_bind_tes(struct tu_cmd_buffer * cmd,struct tu_shader * tes)3380 tu_bind_tes(struct tu_cmd_buffer *cmd, struct tu_shader *tes)
3381 {
3382 if (cmd->state.shaders[MESA_SHADER_TESS_EVAL] != tes) {
3383 cmd->state.shaders[MESA_SHADER_TESS_EVAL] = tes;
3384 cmd->state.dirty |= TU_CMD_DIRTY_TES;
3385
3386 if (!cmd->state.tess_params.valid ||
3387 cmd->state.tess_params.output_upper_left !=
3388 tes->tes.tess_output_upper_left ||
3389 cmd->state.tess_params.output_lower_left !=
3390 tes->tes.tess_output_lower_left ||
3391 cmd->state.tess_params.spacing != tes->tes.tess_spacing) {
3392 cmd->state.tess_params.output_upper_left =
3393 tes->tes.tess_output_upper_left;
3394 cmd->state.tess_params.output_lower_left =
3395 tes->tes.tess_output_lower_left;
3396 cmd->state.tess_params.spacing = tes->tes.tess_spacing;
3397 cmd->state.tess_params.valid = true;
3398 cmd->state.dirty |= TU_CMD_DIRTY_TESS_PARAMS;
3399 }
3400 }
3401 }
3402
3403 static void
tu_bind_gs(struct tu_cmd_buffer * cmd,struct tu_shader * gs)3404 tu_bind_gs(struct tu_cmd_buffer *cmd, struct tu_shader *gs)
3405 {
3406 cmd->state.shaders[MESA_SHADER_GEOMETRY] = gs;
3407 }
3408
3409 static void
tu_bind_fs(struct tu_cmd_buffer * cmd,struct tu_shader * fs)3410 tu_bind_fs(struct tu_cmd_buffer *cmd, struct tu_shader *fs)
3411 {
3412 if (cmd->state.shaders[MESA_SHADER_FRAGMENT] != fs) {
3413 cmd->state.shaders[MESA_SHADER_FRAGMENT] = fs;
3414 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
3415 }
3416 }
3417
3418 /* We cannot do this only at pipeline bind time since pipeline
3419 * could have been bound at any time before current renderpass,
3420 * e.g. in the previous renderpass.
3421 */
3422 static void
tu_pipeline_update_rp_state(struct tu_cmd_state * cmd_state)3423 tu_pipeline_update_rp_state(struct tu_cmd_state *cmd_state)
3424 {
3425 if (cmd_state->pipeline_disable_gmem &&
3426 !cmd_state->rp.disable_gmem) {
3427 /* VK_EXT_attachment_feedback_loop_layout allows feedback loop to involve
3428 * not only input attachments but also sampled images or image resources.
3429 * But we cannot just patch gmem for image in the descriptors.
3430 *
3431 * At the moment, in context of DXVK, it is expected that only a few
3432 * drawcalls in a frame would use feedback loop and they would be wrapped
3433 * in their own renderpasses, so it should be ok to force sysmem.
3434 *
3435 * However, there are two further possible optimizations if need would
3436 * arise for other translation layer:
3437 * - Tiling could be enabled if we ensure that there is no barrier in
3438 * the renderpass;
3439 * - Check that both pipeline and attachments agree that feedback loop
3440 * is needed.
3441 */
3442 perf_debug(
3443 cmd->device,
3444 "Disabling gmem due to VK_EXT_attachment_feedback_loop_layout");
3445 cmd_state->rp.disable_gmem = true;
3446 }
3447
3448 if (cmd_state->pipeline_sysmem_single_prim_mode &&
3449 !cmd_state->rp.sysmem_single_prim_mode) {
3450 perf_debug(cmd->device, "single_prim_mode due to pipeline settings");
3451 cmd_state->rp.sysmem_single_prim_mode = true;
3452 }
3453
3454 if (cmd_state->pipeline_has_tess) {
3455 cmd_state->rp.has_tess = true;
3456 }
3457 }
3458
3459 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindPipeline(VkCommandBuffer commandBuffer,VkPipelineBindPoint pipelineBindPoint,VkPipeline _pipeline)3460 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
3461 VkPipelineBindPoint pipelineBindPoint,
3462 VkPipeline _pipeline)
3463 {
3464 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3465 VK_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
3466
3467 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE) {
3468 cmd->state.shaders[MESA_SHADER_COMPUTE] =
3469 pipeline->shaders[MESA_SHADER_COMPUTE];
3470 tu_cs_emit_state_ib(&cmd->cs,
3471 pipeline->shaders[MESA_SHADER_COMPUTE]->state);
3472 cmd->state.compute_load_state = pipeline->load_state;
3473 return;
3474 }
3475
3476 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS);
3477
3478 struct tu_graphics_pipeline *gfx_pipeline = tu_pipeline_to_graphics(pipeline);
3479 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS | TU_CMD_DIRTY_SHADER_CONSTS |
3480 TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_PROGRAM;
3481
3482 tu_bind_vs(cmd, pipeline->shaders[MESA_SHADER_VERTEX]);
3483 tu_bind_tcs(cmd, pipeline->shaders[MESA_SHADER_TESS_CTRL]);
3484 tu_bind_tes(cmd, pipeline->shaders[MESA_SHADER_TESS_EVAL]);
3485 tu_bind_gs(cmd, pipeline->shaders[MESA_SHADER_GEOMETRY]);
3486 tu_bind_fs(cmd, pipeline->shaders[MESA_SHADER_FRAGMENT]);
3487
3488 /* We precompile static state and count it as dynamic, so we have to
3489 * manually clear bitset that tells which dynamic state is set, in order to
3490 * make sure that future dynamic state will be emitted. The issue is that
3491 * framework remembers only a past REAL dynamic state and compares a new
3492 * dynamic state against it, and not against our static state masquaraded
3493 * as dynamic.
3494 */
3495 BITSET_ANDNOT(cmd->vk.dynamic_graphics_state.set,
3496 cmd->vk.dynamic_graphics_state.set,
3497 pipeline->static_state_mask);
3498
3499 vk_cmd_set_dynamic_graphics_state(&cmd->vk,
3500 &gfx_pipeline->dynamic_state);
3501 cmd->state.program = pipeline->program;
3502
3503 cmd->state.load_state = pipeline->load_state;
3504 cmd->state.prim_order_gmem = pipeline->prim_order.state_gmem;
3505 cmd->state.pipeline_sysmem_single_prim_mode = pipeline->prim_order.sysmem_single_prim_mode;
3506 cmd->state.pipeline_has_tess = pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
3507 cmd->state.pipeline_disable_gmem = gfx_pipeline->feedback_loop_may_involve_textures;
3508
3509 tu_pipeline_update_rp_state(&cmd->state);
3510
3511 if (pipeline->lrz_blend.valid) {
3512 if (cmd->state.blend_reads_dest != pipeline->lrz_blend.reads_dest) {
3513 cmd->state.blend_reads_dest = pipeline->lrz_blend.reads_dest;
3514 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
3515 }
3516 }
3517 cmd->state.pipeline_blend_lrz = pipeline->lrz_blend.valid;
3518
3519 if (pipeline->bandwidth.valid)
3520 cmd->state.bandwidth = pipeline->bandwidth;
3521 cmd->state.pipeline_bandwidth = pipeline->bandwidth.valid;
3522
3523 struct tu_cs *cs = &cmd->draw_cs;
3524
3525 /* note: this also avoids emitting draw states before renderpass clears,
3526 * which may use the 3D clear path (for MSAA cases)
3527 */
3528 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
3529 uint32_t mask = pipeline->set_state_mask;
3530
3531 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (10 + util_bitcount(mask)));
3532 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
3533 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS, pipeline->program.vs_state);
3534 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_BINNING, pipeline->program.vs_binning_state);
3535 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_HS, pipeline->program.hs_state);
3536 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS, pipeline->program.ds_state);
3537 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS, pipeline->program.gs_state);
3538 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS_BINNING, pipeline->program.gs_binning_state);
3539 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS, pipeline->program.fs_state);
3540 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VPC, pipeline->program.vpc_state);
3541 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, pipeline->prim_order.state_gmem);
3542
3543 u_foreach_bit(i, mask)
3544 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]);
3545 }
3546
3547 cmd->state.pipeline_draw_states = pipeline->set_state_mask;
3548 u_foreach_bit(i, pipeline->set_state_mask)
3549 cmd->state.dynamic_state[i] = pipeline->dynamic_state[i];
3550
3551 if (pipeline->program.per_view_viewport != cmd->state.per_view_viewport) {
3552 cmd->state.per_view_viewport = pipeline->program.per_view_viewport;
3553 cmd->state.dirty |= TU_CMD_DIRTY_PER_VIEW_VIEWPORT;
3554 }
3555
3556 if (gfx_pipeline->feedback_loops != cmd->state.pipeline_feedback_loops) {
3557 cmd->state.pipeline_feedback_loops = gfx_pipeline->feedback_loops;
3558 cmd->state.dirty |= TU_CMD_DIRTY_FEEDBACK_LOOPS | TU_CMD_DIRTY_LRZ;
3559 }
3560
3561 bool raster_order_attachment_access =
3562 pipeline->output.raster_order_attachment_access ||
3563 pipeline->ds.raster_order_attachment_access;
3564 if (!cmd->state.raster_order_attachment_access_valid ||
3565 raster_order_attachment_access !=
3566 cmd->state.raster_order_attachment_access) {
3567 cmd->state.raster_order_attachment_access =
3568 raster_order_attachment_access;
3569 cmd->state.dirty |= TU_CMD_DIRTY_RAST_ORDER;
3570 cmd->state.raster_order_attachment_access_valid = true;
3571 }
3572 }
3573
3574 void
tu_flush_for_access(struct tu_cache_state * cache,enum tu_cmd_access_mask src_mask,enum tu_cmd_access_mask dst_mask)3575 tu_flush_for_access(struct tu_cache_state *cache,
3576 enum tu_cmd_access_mask src_mask,
3577 enum tu_cmd_access_mask dst_mask)
3578 {
3579 BITMASK_ENUM(tu_cmd_flush_bits) flush_bits = 0;
3580
3581 if (src_mask & TU_ACCESS_SYSMEM_WRITE) {
3582 cache->pending_flush_bits |= TU_CMD_FLAG_ALL_INVALIDATE;
3583 }
3584
3585 if (src_mask & TU_ACCESS_CP_WRITE) {
3586 /* Flush the CP write queue.
3587 */
3588 cache->pending_flush_bits |=
3589 TU_CMD_FLAG_WAIT_MEM_WRITES |
3590 TU_CMD_FLAG_ALL_INVALIDATE;
3591 }
3592
3593 #define SRC_FLUSH(domain, clean, invalidate) \
3594 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
3595 cache->pending_flush_bits |= TU_CMD_FLAG_##clean | \
3596 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
3597 }
3598
3599 SRC_FLUSH(UCHE, CACHE_CLEAN, CACHE_INVALIDATE)
3600 SRC_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3601 SRC_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3602
3603 #undef SRC_FLUSH
3604
3605 #define SRC_INCOHERENT_FLUSH(domain, clean, invalidate) \
3606 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
3607 flush_bits |= TU_CMD_FLAG_##clean; \
3608 cache->pending_flush_bits |= \
3609 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
3610 }
3611
3612 SRC_INCOHERENT_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3613 SRC_INCOHERENT_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3614
3615 #undef SRC_INCOHERENT_FLUSH
3616
3617 /* Treat host & sysmem write accesses the same, since the kernel implicitly
3618 * drains the queue before signalling completion to the host.
3619 */
3620 if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE)) {
3621 flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_CLEAN;
3622 }
3623
3624 #define DST_FLUSH(domain, clean, invalidate) \
3625 if (dst_mask & (TU_ACCESS_##domain##_READ | \
3626 TU_ACCESS_##domain##_WRITE)) { \
3627 flush_bits |= cache->pending_flush_bits & \
3628 (TU_CMD_FLAG_##invalidate | \
3629 (TU_CMD_FLAG_ALL_CLEAN & ~TU_CMD_FLAG_##clean)); \
3630 }
3631
3632 DST_FLUSH(UCHE, CACHE_CLEAN, CACHE_INVALIDATE)
3633 DST_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3634 DST_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3635
3636 #undef DST_FLUSH
3637
3638 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
3639 if (dst_mask & (TU_ACCESS_##domain##_INCOHERENT_READ | \
3640 TU_ACCESS_##domain##_INCOHERENT_WRITE)) { \
3641 flush_bits |= TU_CMD_FLAG_##invalidate | \
3642 (cache->pending_flush_bits & \
3643 (TU_CMD_FLAG_ALL_CLEAN & ~TU_CMD_FLAG_##flush)); \
3644 }
3645
3646 DST_INCOHERENT_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3647 DST_INCOHERENT_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3648
3649 if (dst_mask & TU_ACCESS_BINDLESS_DESCRIPTOR_READ) {
3650 flush_bits |= TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE;
3651 }
3652
3653 /* There are multiple incoherent copies of CCHE, so any read through it may
3654 * require invalidating it and we cannot optimize away invalidates.
3655 */
3656 if (dst_mask & TU_ACCESS_CCHE_READ) {
3657 flush_bits |= TU_CMD_FLAG_CCHE_INVALIDATE;
3658 }
3659
3660 /* The blit cache is a special case dependency between CP_EVENT_WRITE::BLIT
3661 * (from GMEM loads/clears) to any GMEM attachment reads done via the UCHE
3662 * (Eg: Input attachments/CP_BLIT) which needs an explicit BLIT_CACHE_CLEAN
3663 * for the event blit writes to land, it has the following properties:
3664 * - Set on reads rather than on writes, like flushes.
3665 * - Not executed automatically if pending, like invalidates.
3666 * - Pending bits passed through to secondary command buffers, if they're
3667 * continuing the render pass.
3668 */
3669 if (src_mask & TU_ACCESS_BLIT_WRITE_GMEM) {
3670 cache->pending_flush_bits |= TU_CMD_FLAG_BLIT_CACHE_CLEAN;
3671 }
3672
3673 if ((dst_mask & TU_ACCESS_UCHE_READ_GMEM) &&
3674 (cache->pending_flush_bits & TU_CMD_FLAG_BLIT_CACHE_CLEAN)) {
3675 flush_bits |= TU_CMD_FLAG_BLIT_CACHE_CLEAN;
3676 }
3677
3678 #undef DST_INCOHERENT_FLUSH
3679
3680 cache->flush_bits |= flush_bits;
3681 cache->pending_flush_bits &= ~flush_bits;
3682 }
3683
3684 /* When translating Vulkan access flags to which cache is accessed
3685 * (CCU/UCHE/sysmem), we should take into account both the access flags and
3686 * the stage so that accesses with MEMORY_READ_BIT/MEMORY_WRITE_BIT + a
3687 * specific stage return something sensible. The specification for
3688 * VK_KHR_synchronization2 says that we should do this:
3689 *
3690 * Additionally, scoping the pipeline stages into the barrier structs
3691 * allows the use of the MEMORY_READ and MEMORY_WRITE flags without
3692 * sacrificing precision. The per-stage access flags should be used to
3693 * disambiguate specific accesses in a given stage or set of stages - for
3694 * instance, between uniform reads and sampling operations.
3695 *
3696 * Note that while in all known cases the stage is actually enough, we should
3697 * still narrow things down based on the access flags to handle "old-style"
3698 * barriers that may specify a wider range of stages but more precise access
3699 * flags. These helpers allow us to do both.
3700 */
3701
3702 static bool
filter_read_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3703 filter_read_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3704 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3705 {
3706 return (flags & (tu_flags | VK_ACCESS_2_MEMORY_READ_BIT)) &&
3707 (stages & (tu_stages | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT));
3708 }
3709
3710 static bool
filter_write_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3711 filter_write_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3712 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3713 {
3714 return (flags & (tu_flags | VK_ACCESS_2_MEMORY_WRITE_BIT)) &&
3715 (stages & (tu_stages | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT));
3716 }
3717
3718 static bool
gfx_read_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3719 gfx_read_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3720 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3721 {
3722 return filter_read_access(flags, stages, tu_flags,
3723 tu_stages | VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT);
3724 }
3725
3726 static bool
gfx_write_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3727 gfx_write_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3728 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3729 {
3730 return filter_write_access(flags, stages, tu_flags,
3731 tu_stages | VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT);
3732 }
3733
3734 static enum tu_cmd_access_mask
vk2tu_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,bool image_only,bool gmem)3735 vk2tu_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages, bool image_only, bool gmem)
3736 {
3737 BITMASK_ENUM(tu_cmd_access_mask) mask = 0;
3738
3739 if (gfx_read_access(flags, stages,
3740 VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT |
3741 VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT |
3742 VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT |
3743 VK_ACCESS_2_HOST_READ_BIT,
3744 VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT |
3745 VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT |
3746 VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT |
3747 VK_PIPELINE_STAGE_2_HOST_BIT))
3748 mask |= TU_ACCESS_SYSMEM_READ;
3749
3750 if (gfx_write_access(flags, stages,
3751 VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT,
3752 VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT))
3753 mask |= TU_ACCESS_CP_WRITE;
3754
3755 if (gfx_write_access(flags, stages,
3756 VK_ACCESS_2_HOST_WRITE_BIT,
3757 VK_PIPELINE_STAGE_2_HOST_BIT))
3758 mask |= TU_ACCESS_SYSMEM_WRITE;
3759
3760 #define SHADER_STAGES \
3761 (VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT | \
3762 VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT | \
3763 VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT | \
3764 VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT | \
3765 VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT | \
3766 VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT | \
3767 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT)
3768
3769
3770 if (gfx_read_access(flags, stages,
3771 VK_ACCESS_2_INDEX_READ_BIT |
3772 VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT |
3773 VK_ACCESS_2_UNIFORM_READ_BIT |
3774 VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT |
3775 VK_ACCESS_2_SHADER_READ_BIT |
3776 VK_ACCESS_2_SHADER_SAMPLED_READ_BIT |
3777 VK_ACCESS_2_SHADER_STORAGE_READ_BIT |
3778 VK_ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR,
3779 VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT |
3780 VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT |
3781 VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT |
3782 SHADER_STAGES))
3783 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ;
3784
3785 if (gfx_read_access(flags, stages,
3786 VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT,
3787 SHADER_STAGES))
3788 mask |= TU_ACCESS_UCHE_READ_GMEM;
3789
3790 if (gfx_read_access(flags, stages,
3791 VK_ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT,
3792 SHADER_STAGES)) {
3793 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_BINDLESS_DESCRIPTOR_READ |
3794 TU_ACCESS_CCHE_READ;
3795 }
3796
3797 if (gfx_write_access(flags, stages,
3798 VK_ACCESS_2_SHADER_WRITE_BIT |
3799 VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT |
3800 VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT,
3801 VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT |
3802 SHADER_STAGES))
3803 mask |= TU_ACCESS_UCHE_WRITE;
3804
3805 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
3806 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
3807 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
3808 * can ignore CCU and pretend that color attachments and transfers use
3809 * sysmem directly.
3810 */
3811
3812 if (gfx_read_access(flags, stages,
3813 VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT |
3814 VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT,
3815 VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT)) {
3816 if (gmem)
3817 mask |= TU_ACCESS_SYSMEM_READ;
3818 else
3819 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_READ;
3820 }
3821
3822 if (gfx_read_access(flags, stages,
3823 VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT,
3824 VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT |
3825 VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT)) {
3826 if (gmem)
3827 mask |= TU_ACCESS_SYSMEM_READ;
3828 else
3829 mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ;
3830 }
3831
3832 if (gfx_write_access(flags, stages,
3833 VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT,
3834 VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT)) {
3835 if (gmem) {
3836 mask |= TU_ACCESS_SYSMEM_WRITE;
3837 } else {
3838 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
3839 }
3840 }
3841
3842 if (gfx_write_access(flags, stages,
3843 VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
3844 VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT |
3845 VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT)) {
3846 if (gmem) {
3847 mask |= TU_ACCESS_SYSMEM_WRITE;
3848 } else {
3849 mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
3850 }
3851 }
3852
3853 if (filter_write_access(flags, stages,
3854 VK_ACCESS_2_TRANSFER_WRITE_BIT,
3855 VK_PIPELINE_STAGE_2_COPY_BIT |
3856 VK_PIPELINE_STAGE_2_BLIT_BIT |
3857 VK_PIPELINE_STAGE_2_CLEAR_BIT |
3858 VK_PIPELINE_STAGE_2_RESOLVE_BIT |
3859 VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT)) {
3860 if (gmem) {
3861 mask |= TU_ACCESS_SYSMEM_WRITE;
3862 } else if (image_only) {
3863 /* Because we always split up blits/copies of images involving
3864 * multiple layers, we always access each layer in the same way, with
3865 * the same base address, same format, etc. This means we can avoid
3866 * flushing between multiple writes to the same image. This elides
3867 * flushes between e.g. multiple blits to the same image.
3868 */
3869 mask |= TU_ACCESS_CCU_COLOR_WRITE;
3870 } else {
3871 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
3872 }
3873 }
3874
3875 if (filter_read_access(flags, stages,
3876 VK_ACCESS_2_TRANSFER_READ_BIT,
3877 VK_PIPELINE_STAGE_2_COPY_BIT |
3878 VK_PIPELINE_STAGE_2_BLIT_BIT |
3879 VK_PIPELINE_STAGE_2_RESOLVE_BIT |
3880 VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT)) {
3881 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ;
3882 }
3883
3884 return mask;
3885 }
3886
3887 /* These helpers deal with legacy BOTTOM_OF_PIPE/TOP_OF_PIPE stages.
3888 */
3889
3890 static VkPipelineStageFlags2
sanitize_src_stage(VkPipelineStageFlags2 stage_mask)3891 sanitize_src_stage(VkPipelineStageFlags2 stage_mask)
3892 {
3893 /* From the Vulkan spec:
3894 *
3895 * VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT is ... equivalent to
3896 * VK_PIPELINE_STAGE_2_NONE in the first scope.
3897 *
3898 * VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT is equivalent to
3899 * VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT with VkAccessFlags2 set to 0
3900 * when specified in the first synchronization scope, ...
3901 */
3902 if (stage_mask & VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT)
3903 return VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT;
3904
3905 return stage_mask & ~VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT;
3906 }
3907
3908 static VkPipelineStageFlags2
sanitize_dst_stage(VkPipelineStageFlags2 stage_mask)3909 sanitize_dst_stage(VkPipelineStageFlags2 stage_mask)
3910 {
3911 /* From the Vulkan spec:
3912 *
3913 * VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT is equivalent to
3914 * VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT with VkAccessFlags2 set to 0
3915 * when specified in the second synchronization scope, ...
3916 *
3917 * VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT is ... equivalent to
3918 * VK_PIPELINE_STAGE_2_NONE in the second scope.
3919 *
3920 */
3921 if (stage_mask & VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT)
3922 return VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT;
3923
3924 return stage_mask & ~VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
3925 }
3926
3927 static enum tu_stage
vk2tu_single_stage(VkPipelineStageFlags2 vk_stage,bool dst)3928 vk2tu_single_stage(VkPipelineStageFlags2 vk_stage, bool dst)
3929 {
3930 /* If the destination stage is executed on the CP, then the CP also has to
3931 * wait for any WFI's to finish. This is already done for draw calls,
3932 * including before indirect param reads, for the most part, so we just
3933 * need to WFI and can use TU_STAGE_GPU.
3934 *
3935 * However, some indirect draw opcodes, depending on firmware, don't have
3936 * implicit CP_WAIT_FOR_ME so we have to handle it manually.
3937 *
3938 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
3939 * does CP_WAIT_FOR_ME, so we don't include them here.
3940 *
3941 * Currently we read the draw predicate using CP_MEM_TO_MEM, which
3942 * also implicitly does CP_WAIT_FOR_ME. However CP_DRAW_PRED_SET does *not*
3943 * implicitly do CP_WAIT_FOR_ME, it seems to only wait for counters to
3944 * complete since it's written for DX11 where you can only predicate on the
3945 * result of a query object. So if we implement 64-bit comparisons in the
3946 * future, or if CP_DRAW_PRED_SET grows the capability to do 32-bit
3947 * comparisons, then this will have to be dealt with.
3948 */
3949 if (vk_stage == VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT ||
3950 vk_stage == VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT ||
3951 vk_stage == VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT)
3952 return TU_STAGE_CP;
3953
3954 if (vk_stage == VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT ||
3955 vk_stage == VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)
3956 return dst ? TU_STAGE_CP : TU_STAGE_GPU;
3957
3958 if (vk_stage == VK_PIPELINE_STAGE_2_HOST_BIT)
3959 return dst ? TU_STAGE_BOTTOM : TU_STAGE_CP;
3960
3961 return TU_STAGE_GPU;
3962 }
3963
3964 static enum tu_stage
vk2tu_src_stage(VkPipelineStageFlags2 vk_stages)3965 vk2tu_src_stage(VkPipelineStageFlags2 vk_stages)
3966 {
3967 enum tu_stage stage = TU_STAGE_CP;
3968 u_foreach_bit64 (bit, vk_stages) {
3969 enum tu_stage new_stage = vk2tu_single_stage(1ull << bit, false);
3970 stage = MAX2(stage, new_stage);
3971 }
3972
3973 return stage;
3974 }
3975
3976 static enum tu_stage
vk2tu_dst_stage(VkPipelineStageFlags2 vk_stages)3977 vk2tu_dst_stage(VkPipelineStageFlags2 vk_stages)
3978 {
3979 enum tu_stage stage = TU_STAGE_BOTTOM;
3980 u_foreach_bit64 (bit, vk_stages) {
3981 enum tu_stage new_stage = vk2tu_single_stage(1ull << bit, true);
3982 stage = MIN2(stage, new_stage);
3983 }
3984
3985 return stage;
3986 }
3987
3988 static void
tu_flush_for_stage(struct tu_cache_state * cache,enum tu_stage src_stage,enum tu_stage dst_stage)3989 tu_flush_for_stage(struct tu_cache_state *cache,
3990 enum tu_stage src_stage, enum tu_stage dst_stage)
3991 {
3992 /* Even if the source is the host or CP, the destination access could
3993 * generate invalidates that we have to wait to complete.
3994 */
3995 if (src_stage == TU_STAGE_CP &&
3996 (cache->flush_bits & TU_CMD_FLAG_ALL_INVALIDATE))
3997 src_stage = TU_STAGE_GPU;
3998
3999 if (src_stage >= dst_stage) {
4000 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
4001 if (dst_stage == TU_STAGE_CP)
4002 cache->pending_flush_bits |= TU_CMD_FLAG_WAIT_FOR_ME;
4003 }
4004 }
4005
4006 void
tu_render_pass_state_merge(struct tu_render_pass_state * dst,const struct tu_render_pass_state * src)4007 tu_render_pass_state_merge(struct tu_render_pass_state *dst,
4008 const struct tu_render_pass_state *src)
4009 {
4010 dst->xfb_used |= src->xfb_used;
4011 dst->has_tess |= src->has_tess;
4012 dst->has_prim_generated_query_in_rp |= src->has_prim_generated_query_in_rp;
4013 dst->has_zpass_done_sample_count_write_in_rp |= src->has_zpass_done_sample_count_write_in_rp;
4014 dst->disable_gmem |= src->disable_gmem;
4015 dst->sysmem_single_prim_mode |= src->sysmem_single_prim_mode;
4016 dst->draw_cs_writes_to_cond_pred |= src->draw_cs_writes_to_cond_pred;
4017 dst->shared_viewport |= src->shared_viewport;
4018
4019 dst->drawcall_count += src->drawcall_count;
4020 dst->drawcall_bandwidth_per_sample_sum +=
4021 src->drawcall_bandwidth_per_sample_sum;
4022 if (!dst->lrz_disable_reason)
4023 dst->lrz_disable_reason = src->lrz_disable_reason;
4024 }
4025
4026 void
tu_restore_suspended_pass(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * suspended)4027 tu_restore_suspended_pass(struct tu_cmd_buffer *cmd,
4028 struct tu_cmd_buffer *suspended)
4029 {
4030 cmd->state.pass = suspended->state.suspended_pass.pass;
4031 cmd->state.subpass = suspended->state.suspended_pass.subpass;
4032 cmd->state.framebuffer = suspended->state.suspended_pass.framebuffer;
4033 cmd->state.attachments = suspended->state.suspended_pass.attachments;
4034 cmd->state.clear_values = suspended->state.suspended_pass.clear_values;
4035 cmd->state.render_area = suspended->state.suspended_pass.render_area;
4036 cmd->state.gmem_layout = suspended->state.suspended_pass.gmem_layout;
4037 cmd->state.tiling = &cmd->state.framebuffer->tiling[cmd->state.gmem_layout];
4038 cmd->state.lrz = suspended->state.suspended_pass.lrz;
4039 }
4040
4041 /* Take the saved pre-chain in "secondary" and copy its commands to "cmd",
4042 * appending it after any saved-up commands in "cmd".
4043 */
4044 void
tu_append_pre_chain(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * secondary)4045 tu_append_pre_chain(struct tu_cmd_buffer *cmd,
4046 struct tu_cmd_buffer *secondary)
4047 {
4048 tu_cs_add_entries(&cmd->draw_cs, &secondary->pre_chain.draw_cs);
4049 tu_cs_add_entries(&cmd->draw_epilogue_cs,
4050 &secondary->pre_chain.draw_epilogue_cs);
4051
4052 tu_render_pass_state_merge(&cmd->state.rp,
4053 &secondary->pre_chain.state);
4054 tu_clone_trace_range(cmd, &cmd->draw_cs, secondary->pre_chain.trace_renderpass_start,
4055 secondary->pre_chain.trace_renderpass_end);
4056 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4057 &secondary->pre_chain.fdm_bin_patchpoints);
4058 }
4059
4060 /* Take the saved post-chain in "secondary" and copy it to "cmd".
4061 */
4062 void
tu_append_post_chain(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * secondary)4063 tu_append_post_chain(struct tu_cmd_buffer *cmd,
4064 struct tu_cmd_buffer *secondary)
4065 {
4066 tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
4067 tu_cs_add_entries(&cmd->draw_epilogue_cs, &secondary->draw_epilogue_cs);
4068
4069 tu_clone_trace_range(cmd, &cmd->draw_cs, secondary->trace_renderpass_start,
4070 secondary->trace_renderpass_end);
4071 cmd->state.rp = secondary->state.rp;
4072 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4073 &secondary->fdm_bin_patchpoints);
4074 }
4075
4076 /* Assuming "secondary" is just a sequence of suspended and resuming passes,
4077 * copy its state to "cmd". This also works instead of tu_append_post_chain(),
4078 * but it's a bit slower because we don't assume that the chain begins in
4079 * "secondary" and therefore have to care about the command buffer's
4080 * renderpass state.
4081 */
4082 void
tu_append_pre_post_chain(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * secondary)4083 tu_append_pre_post_chain(struct tu_cmd_buffer *cmd,
4084 struct tu_cmd_buffer *secondary)
4085 {
4086 tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
4087 tu_cs_add_entries(&cmd->draw_epilogue_cs, &secondary->draw_epilogue_cs);
4088
4089 tu_clone_trace_range(cmd, &cmd->draw_cs, secondary->trace_renderpass_start,
4090 secondary->trace_renderpass_end);
4091 tu_render_pass_state_merge(&cmd->state.rp,
4092 &secondary->state.rp);
4093 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4094 &secondary->fdm_bin_patchpoints);
4095 }
4096
4097 /* Take the current render pass state and save it to "pre_chain" to be
4098 * combined later.
4099 */
4100 static void
tu_save_pre_chain(struct tu_cmd_buffer * cmd)4101 tu_save_pre_chain(struct tu_cmd_buffer *cmd)
4102 {
4103 tu_cs_add_entries(&cmd->pre_chain.draw_cs,
4104 &cmd->draw_cs);
4105 tu_cs_add_entries(&cmd->pre_chain.draw_epilogue_cs,
4106 &cmd->draw_epilogue_cs);
4107 cmd->pre_chain.trace_renderpass_start =
4108 cmd->trace_renderpass_start;
4109 cmd->pre_chain.trace_renderpass_end =
4110 cmd->trace_renderpass_end;
4111 cmd->pre_chain.state = cmd->state.rp;
4112 util_dynarray_append_dynarray(&cmd->pre_chain.fdm_bin_patchpoints,
4113 &cmd->fdm_bin_patchpoints);
4114 cmd->pre_chain.patchpoints_ctx = cmd->patchpoints_ctx;
4115 cmd->patchpoints_ctx = NULL;
4116 }
4117
4118 VKAPI_ATTR void VKAPI_CALL
tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,uint32_t commandBufferCount,const VkCommandBuffer * pCmdBuffers)4119 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
4120 uint32_t commandBufferCount,
4121 const VkCommandBuffer *pCmdBuffers)
4122 {
4123 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4124 VkResult result;
4125
4126 assert(commandBufferCount > 0);
4127
4128 /* Emit any pending flushes. */
4129 if (cmd->state.pass) {
4130 tu_clean_all_pending(&cmd->state.renderpass_cache);
4131 TU_CALLX(cmd->device, tu_emit_cache_flush_renderpass)(cmd);
4132 } else {
4133 tu_clean_all_pending(&cmd->state.cache);
4134 TU_CALLX(cmd->device, tu_emit_cache_flush)(cmd);
4135 }
4136
4137 for (uint32_t i = 0; i < commandBufferCount; i++) {
4138 VK_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
4139
4140 if (secondary->usage_flags &
4141 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
4142 assert(tu_cs_is_empty(&secondary->cs));
4143
4144 result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
4145 if (result != VK_SUCCESS) {
4146 vk_command_buffer_set_error(&cmd->vk, result);
4147 break;
4148 }
4149
4150 result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
4151 &secondary->draw_epilogue_cs);
4152 if (result != VK_SUCCESS) {
4153 vk_command_buffer_set_error(&cmd->vk, result);
4154 break;
4155 }
4156
4157 /* If LRZ was made invalid in secondary - we should disable
4158 * LRZ retroactively for the whole renderpass.
4159 */
4160 if (!secondary->state.lrz.valid)
4161 cmd->state.lrz.valid = false;
4162
4163 tu_clone_trace(cmd, &cmd->draw_cs, &secondary->trace);
4164 tu_render_pass_state_merge(&cmd->state.rp, &secondary->state.rp);
4165 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4166 &secondary->fdm_bin_patchpoints);
4167 } else {
4168 switch (secondary->state.suspend_resume) {
4169 case SR_NONE:
4170 assert(tu_cs_is_empty(&secondary->draw_cs));
4171 assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
4172 tu_cs_add_entries(&cmd->cs, &secondary->cs);
4173 tu_clone_trace(cmd, &cmd->cs, &secondary->trace);
4174 break;
4175
4176 case SR_IN_PRE_CHAIN:
4177 /* cmd may be empty, which means that the chain begins before cmd
4178 * in which case we have to update its state.
4179 */
4180 if (cmd->state.suspend_resume == SR_NONE) {
4181 cmd->state.suspend_resume = SR_IN_PRE_CHAIN;
4182 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4183 }
4184
4185 /* The secondary is just a continuous suspend/resume chain so we
4186 * just have to append it to the the command buffer.
4187 */
4188 assert(tu_cs_is_empty(&secondary->cs));
4189 tu_append_pre_post_chain(cmd, secondary);
4190 break;
4191
4192 case SR_AFTER_PRE_CHAIN:
4193 case SR_IN_CHAIN:
4194 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
4195 if (secondary->state.suspend_resume == SR_AFTER_PRE_CHAIN ||
4196 secondary->state.suspend_resume == SR_IN_CHAIN_AFTER_PRE_CHAIN) {
4197 /* In thse cases there is a `pre_chain` in the secondary which
4198 * ends that we need to append to the primary.
4199 */
4200
4201 if (cmd->state.suspend_resume == SR_NONE)
4202 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4203
4204 tu_append_pre_chain(cmd, secondary);
4205
4206 /* We're about to render, so we need to end the command stream
4207 * in case there were any extra commands generated by copying
4208 * the trace.
4209 */
4210 tu_cs_end(&cmd->draw_cs);
4211 tu_cs_end(&cmd->draw_epilogue_cs);
4212
4213 switch (cmd->state.suspend_resume) {
4214 case SR_NONE:
4215 case SR_IN_PRE_CHAIN:
4216 /* The renderpass chain ends in the secondary but isn't
4217 * started in the primary, so we have to move the state to
4218 * `pre_chain`.
4219 */
4220 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
4221 tu_save_pre_chain(cmd);
4222 cmd->state.suspend_resume = SR_AFTER_PRE_CHAIN;
4223 break;
4224 case SR_IN_CHAIN:
4225 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
4226 /* The renderpass ends in the secondary and starts somewhere
4227 * earlier in this primary. Since the last render pass in
4228 * the chain is in the secondary, we are technically outside
4229 * of a render pass. Fix that here by reusing the dynamic
4230 * render pass that was setup for the last suspended render
4231 * pass before the secondary.
4232 */
4233 tu_restore_suspended_pass(cmd, cmd);
4234
4235 TU_CALLX(cmd->device, tu_cmd_render)(cmd);
4236 if (cmd->state.suspend_resume == SR_IN_CHAIN)
4237 cmd->state.suspend_resume = SR_NONE;
4238 else
4239 cmd->state.suspend_resume = SR_AFTER_PRE_CHAIN;
4240 break;
4241 case SR_AFTER_PRE_CHAIN:
4242 unreachable("resuming render pass is not preceded by suspending one");
4243 }
4244
4245 tu_reset_render_pass(cmd);
4246 }
4247
4248 tu_cs_add_entries(&cmd->cs, &secondary->cs);
4249
4250 if (secondary->state.suspend_resume == SR_IN_CHAIN_AFTER_PRE_CHAIN ||
4251 secondary->state.suspend_resume == SR_IN_CHAIN) {
4252 /* The secondary ends in a "post-chain" (the opposite of a
4253 * pre-chain) that we need to copy into the current command
4254 * buffer.
4255 */
4256 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4257 tu_append_post_chain(cmd, secondary);
4258 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
4259 cmd->state.suspended_pass = secondary->state.suspended_pass;
4260
4261 switch (cmd->state.suspend_resume) {
4262 case SR_NONE:
4263 cmd->state.suspend_resume = SR_IN_CHAIN;
4264 break;
4265 case SR_AFTER_PRE_CHAIN:
4266 cmd->state.suspend_resume = SR_IN_CHAIN_AFTER_PRE_CHAIN;
4267 break;
4268 default:
4269 unreachable("suspending render pass is followed by a not resuming one");
4270 }
4271 }
4272 }
4273 }
4274
4275 cmd->state.index_size = secondary->state.index_size; /* for restart index update */
4276 }
4277 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
4278
4279 if (!cmd->state.lrz.gpu_dir_tracking && cmd->state.pass) {
4280 /* After a secondary command buffer is executed, LRZ is not valid
4281 * until it is cleared again.
4282 */
4283 cmd->state.lrz.valid = false;
4284 }
4285
4286 /* After executing secondary command buffers, there may have been arbitrary
4287 * flushes executed, so when we encounter a pipeline barrier with a
4288 * srcMask, we have to assume that we need to invalidate. Therefore we need
4289 * to re-initialize the cache with all pending invalidate bits set.
4290 */
4291 if (cmd->state.pass) {
4292 struct tu_cache_state *cache = &cmd->state.renderpass_cache;
4293 BITMASK_ENUM(tu_cmd_flush_bits) retained_pending_flush_bits =
4294 cache->pending_flush_bits & TU_CMD_FLAG_BLIT_CACHE_CLEAN;
4295 tu_cache_init(cache);
4296 cache->pending_flush_bits |= retained_pending_flush_bits;
4297 } else {
4298 tu_cache_init(&cmd->state.cache);
4299 }
4300 }
4301
4302 static void
tu_subpass_barrier(struct tu_cmd_buffer * cmd_buffer,const struct tu_subpass_barrier * barrier,bool external)4303 tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
4304 const struct tu_subpass_barrier *barrier,
4305 bool external)
4306 {
4307 /* Note: we don't know until the end of the subpass whether we'll use
4308 * sysmem, so assume sysmem here to be safe.
4309 */
4310 struct tu_cache_state *cache =
4311 external ? &cmd_buffer->state.cache : &cmd_buffer->state.renderpass_cache;
4312 VkPipelineStageFlags2 src_stage_vk =
4313 sanitize_src_stage(barrier->src_stage_mask);
4314 VkPipelineStageFlags2 dst_stage_vk =
4315 sanitize_dst_stage(barrier->dst_stage_mask);
4316 BITMASK_ENUM(tu_cmd_access_mask) src_flags =
4317 vk2tu_access(barrier->src_access_mask, src_stage_vk, false, false);
4318 BITMASK_ENUM(tu_cmd_access_mask) dst_flags =
4319 vk2tu_access(barrier->dst_access_mask, dst_stage_vk, false, false);
4320
4321 if (barrier->incoherent_ccu_color)
4322 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
4323 if (barrier->incoherent_ccu_depth)
4324 src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
4325
4326 tu_flush_for_access(cache, src_flags, dst_flags);
4327
4328 enum tu_stage src_stage = vk2tu_src_stage(src_stage_vk);
4329 enum tu_stage dst_stage = vk2tu_dst_stage(dst_stage_vk);
4330 tu_flush_for_stage(cache, src_stage, dst_stage);
4331 }
4332
4333 template <chip CHIP>
4334 static void
tu_emit_subpass_begin_gmem(struct tu_cmd_buffer * cmd)4335 tu_emit_subpass_begin_gmem(struct tu_cmd_buffer *cmd)
4336 {
4337 struct tu_cs *cs = &cmd->draw_cs;
4338 uint32_t subpass_idx = cmd->state.subpass - cmd->state.pass->subpasses;
4339
4340 /* If we might choose to bin, then put the loads under a check for geometry
4341 * having been binned to this tile. If we don't choose to bin in the end,
4342 * then we will have manually set those registers to say geometry is present.
4343 *
4344 * However, if the draw CS has a write to the condition for some other reason
4345 * (perf queries), then we can't do this optimization since the
4346 * start-of-the-CS geometry condition will have been overwritten.
4347 */
4348 bool cond_load_allowed = cmd->state.tiling->binning &&
4349 cmd->state.pass->has_cond_load_store &&
4350 !cmd->state.rp.draw_cs_writes_to_cond_pred;
4351
4352 if (cmd->state.pass->has_fdm)
4353 tu_cs_set_writeable(cs, true);
4354
4355 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
4356
4357 /* Emit gmem loads that are first used in this subpass. */
4358 bool emitted_scissor = false;
4359 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4360 struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[i];
4361 if ((att->load || att->load_stencil) && att->first_subpass_idx == subpass_idx) {
4362 if (!emitted_scissor) {
4363 tu6_emit_blit_scissor(cmd, cs, true);
4364 emitted_scissor = true;
4365 }
4366 tu_load_gmem_attachment<CHIP>(cmd, cs, i, cond_load_allowed, false);
4367 }
4368 }
4369
4370 if (!cmd->device->physical_device->info->a7xx.has_generic_clear) {
4371 /* Emit gmem clears that are first used in this subpass. */
4372 emitted_scissor = false;
4373 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4374 struct tu_render_pass_attachment *att =
4375 &cmd->state.pass->attachments[i];
4376 if (att->clear_mask && att->first_subpass_idx == subpass_idx) {
4377 if (!emitted_scissor) {
4378 tu6_emit_blit_scissor(cmd, cs, false);
4379 emitted_scissor = true;
4380 }
4381 tu_clear_gmem_attachment<CHIP>(cmd, cs, i);
4382 }
4383 }
4384 }
4385
4386 tu_cond_exec_end(cs); /* CP_COND_EXEC_0_RENDER_MODE_GMEM */
4387
4388 if (cmd->state.pass->has_fdm)
4389 tu_cs_set_writeable(cs, false);
4390
4391 }
4392
4393 /* Emits sysmem clears that are first used in this subpass. */
4394 template <chip CHIP>
4395 static void
tu_emit_subpass_begin_sysmem(struct tu_cmd_buffer * cmd)4396 tu_emit_subpass_begin_sysmem(struct tu_cmd_buffer *cmd)
4397 {
4398 if (cmd->device->physical_device->info->a7xx.has_generic_clear)
4399 return;
4400
4401 struct tu_cs *cs = &cmd->draw_cs;
4402 uint32_t subpass_idx = cmd->state.subpass - cmd->state.pass->subpasses;
4403
4404 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
4405 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4406 struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[i];
4407 if (att->clear_mask && att->first_subpass_idx == subpass_idx)
4408 tu_clear_sysmem_attachment<CHIP>(cmd, cs, i);
4409 }
4410 tu_cond_exec_end(cs); /* sysmem */
4411 }
4412
4413 static void
tu7_emit_subpass_clear(struct tu_cmd_buffer * cmd)4414 tu7_emit_subpass_clear(struct tu_cmd_buffer *cmd)
4415 {
4416 if (cmd->state.render_area.extent.width == 0 ||
4417 cmd->state.render_area.extent.height == 0)
4418 return;
4419
4420 struct tu_cs *cs = &cmd->draw_cs;
4421 uint32_t subpass_idx = cmd->state.subpass - cmd->state.pass->subpasses;
4422
4423 bool emitted_scissor = false;
4424 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4425 struct tu_render_pass_attachment *att =
4426 &cmd->state.pass->attachments[i];
4427 if (att->clear_mask && att->first_subpass_idx == subpass_idx) {
4428 if (!emitted_scissor) {
4429 tu6_emit_blit_scissor(cmd, cs, false);
4430 emitted_scissor = true;
4431 }
4432 tu7_generic_clear_attachment(cmd, cs, i);
4433 }
4434 }
4435 }
4436
4437 /* emit loads, clears, and mrt/zs/msaa/ubwc state for the subpass that is
4438 * starting (either at vkCmdBeginRenderPass2() or vkCmdNextSubpass2())
4439 *
4440 * Clears and loads have to happen at this point, because with
4441 * VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT the loads may depend on the output of
4442 * a previous aliased attachment's store.
4443 */
4444 template <chip CHIP>
4445 static void
tu_emit_subpass_begin(struct tu_cmd_buffer * cmd)4446 tu_emit_subpass_begin(struct tu_cmd_buffer *cmd)
4447 {
4448 tu_fill_render_pass_state(&cmd->state.vk_rp, cmd->state.pass, cmd->state.subpass);
4449
4450 tu_emit_subpass_begin_gmem<CHIP>(cmd);
4451 tu_emit_subpass_begin_sysmem<CHIP>(cmd);
4452 if (cmd->device->physical_device->info->a7xx.has_generic_clear) {
4453 tu7_emit_subpass_clear(cmd);
4454 }
4455
4456 tu6_emit_zs<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs);
4457 tu6_emit_mrt<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs);
4458 tu6_emit_render_cntl<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs, false);
4459
4460 tu_set_input_attachments(cmd, cmd->state.subpass);
4461
4462 vk_cmd_set_cb_attachment_count(&cmd->vk, cmd->state.subpass->color_count);
4463
4464 cmd->state.dirty |= TU_CMD_DIRTY_SUBPASS;
4465 }
4466
4467 template <chip CHIP>
4468 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,const VkRenderPassBeginInfo * pRenderPassBegin,const VkSubpassBeginInfo * pSubpassBeginInfo)4469 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
4470 const VkRenderPassBeginInfo *pRenderPassBegin,
4471 const VkSubpassBeginInfo *pSubpassBeginInfo)
4472 {
4473 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4474
4475 if (TU_DEBUG(DYNAMIC)) {
4476 vk_common_CmdBeginRenderPass2(commandBuffer, pRenderPassBegin,
4477 pSubpassBeginInfo);
4478 return;
4479 }
4480
4481 VK_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
4482 VK_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
4483
4484 const struct VkRenderPassAttachmentBeginInfo *pAttachmentInfo =
4485 vk_find_struct_const(pRenderPassBegin->pNext,
4486 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
4487
4488 cmd->state.pass = pass;
4489 cmd->state.subpass = pass->subpasses;
4490 cmd->state.framebuffer = fb;
4491 cmd->state.render_area = pRenderPassBegin->renderArea;
4492
4493 VK_MULTIALLOC(ma);
4494 vk_multialloc_add(&ma, &cmd->state.attachments,
4495 const struct tu_image_view *, pass->attachment_count);
4496 vk_multialloc_add(&ma, &cmd->state.clear_values, VkClearValue,
4497 pRenderPassBegin->clearValueCount);
4498 if (!vk_multialloc_alloc(&ma, &cmd->vk.pool->alloc,
4499 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT)) {
4500 vk_command_buffer_set_error(&cmd->vk, VK_ERROR_OUT_OF_HOST_MEMORY);
4501 return;
4502 }
4503
4504 if (cmd->device->dbg_renderpass_stomp_cs) {
4505 tu_cs_emit_call(&cmd->cs, cmd->device->dbg_renderpass_stomp_cs);
4506 }
4507
4508 for (unsigned i = 0; i < pass->attachment_count; i++) {
4509 cmd->state.attachments[i] = pAttachmentInfo ?
4510 tu_image_view_from_handle(pAttachmentInfo->pAttachments[i]) :
4511 cmd->state.framebuffer->attachments[i].attachment;
4512 }
4513 for (unsigned i = 0; i < pRenderPassBegin->clearValueCount; i++)
4514 cmd->state.clear_values[i] = pRenderPassBegin->pClearValues[i];
4515
4516 tu_choose_gmem_layout(cmd);
4517
4518 tu_trace_start_render_pass(cmd);
4519
4520 /* Note: because this is external, any flushes will happen before draw_cs
4521 * gets called. However deferred flushes could have to happen later as part
4522 * of the subpass.
4523 */
4524 tu_subpass_barrier(cmd, &pass->subpasses[0].start_barrier, true);
4525 cmd->state.renderpass_cache.pending_flush_bits =
4526 cmd->state.cache.pending_flush_bits;
4527 cmd->state.renderpass_cache.flush_bits = 0;
4528
4529 if (pass->subpasses[0].feedback_invalidate)
4530 cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
4531
4532 tu_lrz_begin_renderpass<CHIP>(cmd);
4533
4534 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4535
4536 tu_emit_renderpass_begin(cmd);
4537 tu_emit_subpass_begin<CHIP>(cmd);
4538
4539 if (pass->has_fdm)
4540 cmd->patchpoints_ctx = ralloc_parent(NULL);
4541 }
4542 TU_GENX(tu_CmdBeginRenderPass2);
4543
4544 template <chip CHIP>
4545 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginRendering(VkCommandBuffer commandBuffer,const VkRenderingInfo * pRenderingInfo)4546 tu_CmdBeginRendering(VkCommandBuffer commandBuffer,
4547 const VkRenderingInfo *pRenderingInfo)
4548 {
4549 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4550
4551 tu_setup_dynamic_render_pass(cmd, pRenderingInfo);
4552 tu_setup_dynamic_framebuffer(cmd, pRenderingInfo);
4553
4554 cmd->state.pass = &cmd->dynamic_pass;
4555 cmd->state.subpass = &cmd->dynamic_subpass;
4556 cmd->state.framebuffer = &cmd->dynamic_framebuffer;
4557 cmd->state.render_area = pRenderingInfo->renderArea;
4558
4559 cmd->state.attachments = cmd->dynamic_attachments;
4560 cmd->state.clear_values = cmd->dynamic_clear_values;
4561
4562 for (unsigned i = 0; i < pRenderingInfo->colorAttachmentCount; i++) {
4563 uint32_t a = cmd->dynamic_subpass.color_attachments[i].attachment;
4564 if (!pRenderingInfo->pColorAttachments[i].imageView)
4565 continue;
4566
4567 cmd->state.clear_values[a] =
4568 pRenderingInfo->pColorAttachments[i].clearValue;
4569
4570 VK_FROM_HANDLE(tu_image_view, view,
4571 pRenderingInfo->pColorAttachments[i].imageView);
4572 cmd->state.attachments[a] = view;
4573
4574 a = cmd->dynamic_subpass.resolve_attachments[i].attachment;
4575 if (a != VK_ATTACHMENT_UNUSED) {
4576 VK_FROM_HANDLE(tu_image_view, resolve_view,
4577 pRenderingInfo->pColorAttachments[i].resolveImageView);
4578 cmd->state.attachments[a] = resolve_view;
4579 }
4580 }
4581
4582 uint32_t a = cmd->dynamic_subpass.depth_stencil_attachment.attachment;
4583 if (pRenderingInfo->pDepthAttachment || pRenderingInfo->pStencilAttachment) {
4584 const struct VkRenderingAttachmentInfo *common_info =
4585 (pRenderingInfo->pDepthAttachment &&
4586 pRenderingInfo->pDepthAttachment->imageView != VK_NULL_HANDLE) ?
4587 pRenderingInfo->pDepthAttachment :
4588 pRenderingInfo->pStencilAttachment;
4589 if (common_info && common_info->imageView != VK_NULL_HANDLE) {
4590 VK_FROM_HANDLE(tu_image_view, view, common_info->imageView);
4591 cmd->state.attachments[a] = view;
4592 if (pRenderingInfo->pDepthAttachment) {
4593 cmd->state.clear_values[a].depthStencil.depth =
4594 pRenderingInfo->pDepthAttachment->clearValue.depthStencil.depth;
4595 }
4596
4597 if (pRenderingInfo->pStencilAttachment) {
4598 cmd->state.clear_values[a].depthStencil.stencil =
4599 pRenderingInfo->pStencilAttachment->clearValue.depthStencil.stencil;
4600 }
4601
4602 if (cmd->dynamic_subpass.resolve_count >
4603 cmd->dynamic_subpass.color_count) {
4604 VK_FROM_HANDLE(tu_image_view, resolve_view,
4605 common_info->resolveImageView);
4606 a = cmd->dynamic_subpass.resolve_attachments[cmd->dynamic_subpass.color_count].attachment;
4607 cmd->state.attachments[a] = resolve_view;
4608 }
4609 }
4610 }
4611
4612 a = cmd->dynamic_pass.fragment_density_map.attachment;
4613 if (a != VK_ATTACHMENT_UNUSED) {
4614 const VkRenderingFragmentDensityMapAttachmentInfoEXT *fdm_info =
4615 vk_find_struct_const(pRenderingInfo->pNext,
4616 RENDERING_FRAGMENT_DENSITY_MAP_ATTACHMENT_INFO_EXT);
4617 VK_FROM_HANDLE(tu_image_view, view, fdm_info->imageView);
4618 cmd->state.attachments[a] = view;
4619 }
4620
4621 if (cmd->dynamic_pass.has_fdm)
4622 cmd->patchpoints_ctx = ralloc_context(NULL);
4623
4624 tu_choose_gmem_layout(cmd);
4625
4626 cmd->state.renderpass_cache.pending_flush_bits =
4627 cmd->state.cache.pending_flush_bits;
4628 cmd->state.renderpass_cache.flush_bits = 0;
4629
4630 bool resuming = pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT;
4631 bool suspending = pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT;
4632 cmd->state.suspending = suspending;
4633 cmd->state.resuming = resuming;
4634
4635 if (!resuming && cmd->device->dbg_renderpass_stomp_cs) {
4636 tu_cs_emit_call(&cmd->cs, cmd->device->dbg_renderpass_stomp_cs);
4637 }
4638
4639 /* We can't track LRZ across command buffer boundaries, so we have to
4640 * disable LRZ when resuming/suspending unless we can track on the GPU.
4641 */
4642 if ((resuming || suspending) &&
4643 !cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) {
4644 cmd->state.lrz.valid = false;
4645 } else {
4646 if (resuming)
4647 tu_lrz_begin_resumed_renderpass<CHIP>(cmd);
4648 else
4649 tu_lrz_begin_renderpass<CHIP>(cmd);
4650 }
4651
4652
4653 if (suspending) {
4654 cmd->state.suspended_pass.pass = cmd->state.pass;
4655 cmd->state.suspended_pass.subpass = cmd->state.subpass;
4656 cmd->state.suspended_pass.framebuffer = cmd->state.framebuffer;
4657 cmd->state.suspended_pass.render_area = cmd->state.render_area;
4658 cmd->state.suspended_pass.attachments = cmd->state.attachments;
4659 cmd->state.suspended_pass.clear_values = cmd->state.clear_values;
4660 cmd->state.suspended_pass.gmem_layout = cmd->state.gmem_layout;
4661 }
4662
4663 if (!resuming)
4664 tu_trace_start_render_pass(cmd);
4665
4666 if (!resuming || cmd->state.suspend_resume == SR_NONE) {
4667 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4668 }
4669
4670 if (!resuming) {
4671 tu_emit_renderpass_begin(cmd);
4672 tu_emit_subpass_begin<CHIP>(cmd);
4673 }
4674
4675 if (suspending && !resuming) {
4676 /* entering a chain */
4677 switch (cmd->state.suspend_resume) {
4678 case SR_NONE:
4679 cmd->state.suspend_resume = SR_IN_CHAIN;
4680 break;
4681 case SR_AFTER_PRE_CHAIN:
4682 cmd->state.suspend_resume = SR_IN_CHAIN_AFTER_PRE_CHAIN;
4683 break;
4684 case SR_IN_PRE_CHAIN:
4685 case SR_IN_CHAIN:
4686 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
4687 unreachable("suspending render pass not followed by resuming pass");
4688 break;
4689 }
4690 }
4691
4692 if (resuming && cmd->state.suspend_resume == SR_NONE)
4693 cmd->state.suspend_resume = SR_IN_PRE_CHAIN;
4694 }
4695 TU_GENX(tu_CmdBeginRendering);
4696
4697 template <chip CHIP>
4698 VKAPI_ATTR void VKAPI_CALL
tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,const VkSubpassBeginInfo * pSubpassBeginInfo,const VkSubpassEndInfo * pSubpassEndInfo)4699 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
4700 const VkSubpassBeginInfo *pSubpassBeginInfo,
4701 const VkSubpassEndInfo *pSubpassEndInfo)
4702 {
4703 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4704
4705 if (TU_DEBUG(DYNAMIC)) {
4706 vk_common_CmdNextSubpass2(commandBuffer, pSubpassBeginInfo,
4707 pSubpassEndInfo);
4708 return;
4709 }
4710
4711 const struct tu_render_pass *pass = cmd->state.pass;
4712 const struct tu_framebuffer *fb = cmd->state.framebuffer;
4713 struct tu_cs *cs = &cmd->draw_cs;
4714 const struct tu_subpass *last_subpass = cmd->state.subpass;
4715
4716 const struct tu_subpass *subpass = cmd->state.subpass++;
4717
4718 /* Track LRZ valid state
4719 *
4720 * TODO: Improve this tracking for keeping the state of the past depth/stencil images,
4721 * so if they become active again, we reuse its old state.
4722 */
4723 if (last_subpass->depth_stencil_attachment.attachment != subpass->depth_stencil_attachment.attachment) {
4724 cmd->state.lrz.valid = false;
4725 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
4726 }
4727
4728 if (cmd->state.tiling->possible) {
4729 if (cmd->state.pass->has_fdm)
4730 tu_cs_set_writeable(cs, true);
4731
4732 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
4733
4734 if (subpass->resolve_attachments) {
4735 tu6_emit_blit_scissor(cmd, cs, true);
4736
4737 for (unsigned i = 0; i < subpass->resolve_count; i++) {
4738 uint32_t a = subpass->resolve_attachments[i].attachment;
4739 if (a == VK_ATTACHMENT_UNUSED)
4740 continue;
4741
4742 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
4743
4744 tu_store_gmem_attachment<CHIP>(cmd, cs, a, gmem_a, fb->layers,
4745 subpass->multiview_mask, false);
4746
4747 if (!pass->attachments[a].gmem)
4748 continue;
4749
4750 /* check if the resolved attachment is needed by later subpasses,
4751 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
4752 */
4753 perf_debug(cmd->device, "TODO: missing GMEM->GMEM resolve path\n");
4754 tu_load_gmem_attachment<CHIP>(cmd, cs, a, false, true);
4755 }
4756 }
4757
4758 tu_cond_exec_end(cs);
4759
4760 if (cmd->state.pass->has_fdm)
4761 tu_cs_set_writeable(cs, false);
4762
4763 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
4764 }
4765
4766 tu6_emit_sysmem_resolves<CHIP>(cmd, cs, subpass);
4767
4768 if (cmd->state.tiling->possible)
4769 tu_cond_exec_end(cs);
4770
4771 /* Handle dependencies for the next subpass */
4772 tu_subpass_barrier(cmd, &cmd->state.subpass->start_barrier, false);
4773
4774 if (cmd->state.subpass->feedback_invalidate)
4775 cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
4776
4777 tu_emit_subpass_begin<CHIP>(cmd);
4778 }
4779 TU_GENX(tu_CmdNextSubpass2);
4780
4781 static uint32_t
tu6_user_consts_size(const struct tu_const_state * const_state,bool ldgk,gl_shader_stage type)4782 tu6_user_consts_size(const struct tu_const_state *const_state,
4783 bool ldgk,
4784 gl_shader_stage type)
4785 {
4786 uint32_t dwords = 0;
4787
4788 if (const_state->push_consts.type == IR3_PUSH_CONSTS_PER_STAGE) {
4789 unsigned num_units = const_state->push_consts.dwords;
4790 dwords += 4 + num_units;
4791 assert(num_units > 0);
4792 }
4793
4794 if (ldgk) {
4795 dwords += 6 + (2 * const_state->num_inline_ubos + 4);
4796 } else {
4797 dwords += 8 * const_state->num_inline_ubos;
4798 }
4799
4800 return dwords;
4801 }
4802
4803 static void
tu6_emit_per_stage_push_consts(struct tu_cs * cs,const struct tu_const_state * const_state,gl_shader_stage type,uint32_t * push_constants)4804 tu6_emit_per_stage_push_consts(struct tu_cs *cs,
4805 const struct tu_const_state *const_state,
4806 gl_shader_stage type,
4807 uint32_t *push_constants)
4808 {
4809 if (const_state->push_consts.type == IR3_PUSH_CONSTS_PER_STAGE) {
4810 unsigned num_units = const_state->push_consts.dwords;
4811 unsigned offset = const_state->push_consts.lo;
4812 assert(num_units > 0);
4813
4814 /* DST_OFF and NUM_UNIT requires vec4 units */
4815 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units);
4816 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset / 4) |
4817 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4818 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
4819 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4820 CP_LOAD_STATE6_0_NUM_UNIT(num_units / 4));
4821 tu_cs_emit(cs, 0);
4822 tu_cs_emit(cs, 0);
4823 for (unsigned i = 0; i < num_units; i++)
4824 tu_cs_emit(cs, push_constants[i + offset]);
4825 }
4826 }
4827
4828 static void
tu6_emit_inline_ubo(struct tu_cs * cs,const struct tu_const_state * const_state,unsigned constlen,gl_shader_stage type,struct tu_descriptor_state * descriptors)4829 tu6_emit_inline_ubo(struct tu_cs *cs,
4830 const struct tu_const_state *const_state,
4831 unsigned constlen,
4832 gl_shader_stage type,
4833 struct tu_descriptor_state *descriptors)
4834 {
4835 assert(const_state->num_inline_ubos == 0 || !cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble);
4836
4837 /* Emit loads of inline uniforms. These load directly from the uniform's
4838 * storage space inside the descriptor set.
4839 */
4840 for (unsigned i = 0; i < const_state->num_inline_ubos; i++) {
4841 const struct tu_inline_ubo *ubo = &const_state->ubos[i];
4842
4843 if (constlen <= ubo->const_offset_vec4)
4844 continue;
4845
4846 uint64_t va = descriptors->set_iova[ubo->base] & ~0x3f;
4847
4848 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), ubo->push_address ? 7 : 3);
4849 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(ubo->const_offset_vec4) |
4850 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4851 CP_LOAD_STATE6_0_STATE_SRC(ubo->push_address ? SS6_DIRECT : SS6_INDIRECT) |
4852 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4853 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(ubo->size_vec4, constlen - ubo->const_offset_vec4)));
4854 if (ubo->push_address) {
4855 tu_cs_emit(cs, 0);
4856 tu_cs_emit(cs, 0);
4857 tu_cs_emit_qw(cs, va + ubo->offset);
4858 tu_cs_emit(cs, 0);
4859 tu_cs_emit(cs, 0);
4860 } else {
4861 tu_cs_emit_qw(cs, va + ubo->offset);
4862 }
4863 }
4864 }
4865
4866 static void
tu7_emit_inline_ubo(struct tu_cs * cs,const struct tu_const_state * const_state,const struct ir3_const_state * ir_const_state,unsigned constlen,gl_shader_stage type,struct tu_descriptor_state * descriptors)4867 tu7_emit_inline_ubo(struct tu_cs *cs,
4868 const struct tu_const_state *const_state,
4869 const struct ir3_const_state *ir_const_state,
4870 unsigned constlen,
4871 gl_shader_stage type,
4872 struct tu_descriptor_state *descriptors)
4873 {
4874 uint64_t addresses[7] = {0};
4875 unsigned offset = const_state->inline_uniforms_ubo.idx;
4876
4877 if (offset == -1)
4878 return;
4879
4880 for (unsigned i = 0; i < const_state->num_inline_ubos; i++) {
4881 const struct tu_inline_ubo *ubo = &const_state->ubos[i];
4882
4883 uint64_t va = descriptors->set_iova[ubo->base] & ~0x3f;
4884 addresses[i] = va + ubo->offset;
4885 }
4886
4887 /* A7XX TODO: Emit data via sub_cs instead of NOP */
4888 uint64_t iova = tu_cs_emit_data_nop(cs, (uint32_t *)addresses, const_state->num_inline_ubos * 2, 4);
4889
4890 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 5);
4891 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4892 CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO) |
4893 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
4894 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4895 CP_LOAD_STATE6_0_NUM_UNIT(1));
4896 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
4897 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
4898 int size_vec4s = DIV_ROUND_UP(const_state->num_inline_ubos * 2, 4);
4899 tu_cs_emit_qw(cs, iova | ((uint64_t)A6XX_UBO_1_SIZE(size_vec4s) << 32));
4900 }
4901
4902 static void
tu_emit_inline_ubo(struct tu_cs * cs,const struct tu_const_state * const_state,const struct ir3_const_state * ir_const_state,unsigned constlen,gl_shader_stage type,struct tu_descriptor_state * descriptors)4903 tu_emit_inline_ubo(struct tu_cs *cs,
4904 const struct tu_const_state *const_state,
4905 const struct ir3_const_state *ir_const_state,
4906 unsigned constlen,
4907 gl_shader_stage type,
4908 struct tu_descriptor_state *descriptors)
4909 {
4910 if (!const_state->num_inline_ubos)
4911 return;
4912
4913 if (cs->device->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk) {
4914 tu7_emit_inline_ubo(cs, const_state, ir_const_state, constlen, type, descriptors);
4915 } else {
4916 tu6_emit_inline_ubo(cs, const_state, constlen, type, descriptors);
4917 }
4918 }
4919
4920 static void
tu6_emit_shared_consts(struct tu_cs * cs,const struct tu_push_constant_range * shared_consts,uint32_t * push_constants,bool compute)4921 tu6_emit_shared_consts(struct tu_cs *cs,
4922 const struct tu_push_constant_range *shared_consts,
4923 uint32_t *push_constants,
4924 bool compute)
4925 {
4926 if (shared_consts->dwords > 0) {
4927 /* Offset and num_units for shared consts are in units of dwords. */
4928 unsigned num_units = shared_consts->dwords;
4929 unsigned offset = shared_consts->lo;
4930
4931 enum a6xx_state_type st = compute ? ST6_UBO : ST6_CONSTANTS;
4932 uint32_t cp_load_state = compute ? CP_LOAD_STATE6_FRAG : CP_LOAD_STATE6;
4933
4934 tu_cs_emit_pkt7(cs, cp_load_state, 3 + num_units);
4935 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4936 CP_LOAD_STATE6_0_STATE_TYPE(st) |
4937 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
4938 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
4939 CP_LOAD_STATE6_0_NUM_UNIT(num_units));
4940 tu_cs_emit(cs, 0);
4941 tu_cs_emit(cs, 0);
4942
4943 for (unsigned i = 0; i < num_units; i++)
4944 tu_cs_emit(cs, push_constants[i + offset]);
4945 }
4946 }
4947
4948 static void
tu7_emit_shared_preamble_consts(struct tu_cs * cs,const struct tu_push_constant_range * shared_consts,uint32_t * push_constants)4949 tu7_emit_shared_preamble_consts(
4950 struct tu_cs *cs,
4951 const struct tu_push_constant_range *shared_consts,
4952 uint32_t *push_constants)
4953 {
4954 tu_cs_emit_pkt4(cs, REG_A7XX_HLSQ_SHARED_CONSTS_IMM(shared_consts->lo),
4955 shared_consts->dwords);
4956 tu_cs_emit_array(cs, push_constants + shared_consts->lo,
4957 shared_consts->dwords);
4958 }
4959
4960 static uint32_t
tu6_const_size(struct tu_cmd_buffer * cmd,const struct tu_push_constant_range * shared_consts,bool compute)4961 tu6_const_size(struct tu_cmd_buffer *cmd,
4962 const struct tu_push_constant_range *shared_consts,
4963 bool compute)
4964 {
4965 uint32_t dwords = 0;
4966
4967 if (shared_consts->type == IR3_PUSH_CONSTS_SHARED) {
4968 dwords += shared_consts->dwords + 4;
4969 } else if (shared_consts->type == IR3_PUSH_CONSTS_SHARED_PREAMBLE) {
4970 dwords += shared_consts->dwords + 1;
4971 }
4972
4973 bool ldgk = cmd->device->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk;
4974 if (compute) {
4975 dwords +=
4976 tu6_user_consts_size(&cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state, ldgk, MESA_SHADER_COMPUTE);
4977 } else {
4978 for (uint32_t type = MESA_SHADER_VERTEX; type <= MESA_SHADER_FRAGMENT; type++)
4979 dwords += tu6_user_consts_size(&cmd->state.shaders[type]->const_state, ldgk, (gl_shader_stage) type);
4980 }
4981
4982 return dwords;
4983 }
4984
4985 static struct tu_draw_state
tu_emit_consts(struct tu_cmd_buffer * cmd,bool compute)4986 tu_emit_consts(struct tu_cmd_buffer *cmd, bool compute)
4987 {
4988 uint32_t dwords = 0;
4989 const struct tu_push_constant_range *shared_consts =
4990 compute ? &cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state.push_consts :
4991 &cmd->state.program.shared_consts;
4992
4993 dwords = tu6_const_size(cmd, shared_consts, compute);
4994
4995 if (dwords == 0)
4996 return (struct tu_draw_state) {};
4997
4998 struct tu_cs cs;
4999 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs);
5000
5001 if (shared_consts->type == IR3_PUSH_CONSTS_SHARED) {
5002 tu6_emit_shared_consts(&cs, shared_consts, cmd->push_constants, compute);
5003 } else if (shared_consts->type == IR3_PUSH_CONSTS_SHARED_PREAMBLE) {
5004 tu7_emit_shared_preamble_consts(&cs, shared_consts, cmd->push_constants);
5005 }
5006
5007 if (compute) {
5008 tu6_emit_per_stage_push_consts(
5009 &cs, &cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state,
5010 MESA_SHADER_COMPUTE, cmd->push_constants);
5011 tu_emit_inline_ubo(
5012 &cs, &cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state,
5013 cmd->state.shaders[MESA_SHADER_COMPUTE]->variant->const_state,
5014 cmd->state.shaders[MESA_SHADER_COMPUTE]->variant->constlen,
5015 MESA_SHADER_COMPUTE,
5016 tu_get_descriptors_state(cmd, VK_PIPELINE_BIND_POINT_COMPUTE));
5017 } else {
5018 struct tu_descriptor_state *descriptors =
5019 tu_get_descriptors_state(cmd, VK_PIPELINE_BIND_POINT_GRAPHICS);
5020 for (uint32_t type = MESA_SHADER_VERTEX; type <= MESA_SHADER_FRAGMENT; type++) {
5021 const struct tu_program_descriptor_linkage *link =
5022 &cmd->state.program.link[type];
5023 tu6_emit_per_stage_push_consts(&cs, &link->tu_const_state,
5024 (gl_shader_stage) type,
5025 cmd->push_constants);
5026 tu_emit_inline_ubo(&cs, &link->tu_const_state,
5027 &link->const_state, link->constlen,
5028 (gl_shader_stage) type, descriptors);
5029 }
5030 }
5031
5032 return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5033 }
5034
5035 /* Various frontends (ANGLE, zink at least) will enable stencil testing with
5036 * what works out to be no-op writes. Simplify what they give us into flags
5037 * that LRZ can use.
5038 */
5039 static void
tu6_update_simplified_stencil_state(struct tu_cmd_buffer * cmd)5040 tu6_update_simplified_stencil_state(struct tu_cmd_buffer *cmd)
5041 {
5042 const struct vk_depth_stencil_state *ds =
5043 &cmd->vk.dynamic_graphics_state.ds;
5044 bool stencil_test_enable = ds->stencil.test_enable;
5045
5046 if (!stencil_test_enable) {
5047 cmd->state.stencil_front_write = false;
5048 cmd->state.stencil_back_write = false;
5049 return;
5050 }
5051
5052 bool stencil_front_writemask = ds->stencil.front.write_mask;
5053 bool stencil_back_writemask = ds->stencil.back.write_mask;
5054
5055 VkStencilOp front_fail_op = (VkStencilOp)ds->stencil.front.op.fail;
5056 VkStencilOp front_pass_op = (VkStencilOp)ds->stencil.front.op.pass;
5057 VkStencilOp front_depth_fail_op = (VkStencilOp)ds->stencil.front.op.depth_fail;
5058 VkStencilOp back_fail_op = (VkStencilOp)ds->stencil.back.op.fail;
5059 VkStencilOp back_pass_op = (VkStencilOp)ds->stencil.back.op.pass;
5060 VkStencilOp back_depth_fail_op = (VkStencilOp)ds->stencil.back.op.depth_fail;
5061
5062 bool stencil_front_op_writes =
5063 front_pass_op != VK_STENCIL_OP_KEEP ||
5064 front_fail_op != VK_STENCIL_OP_KEEP ||
5065 front_depth_fail_op != VK_STENCIL_OP_KEEP;
5066
5067 bool stencil_back_op_writes =
5068 back_pass_op != VK_STENCIL_OP_KEEP ||
5069 back_fail_op != VK_STENCIL_OP_KEEP ||
5070 back_depth_fail_op != VK_STENCIL_OP_KEEP;
5071
5072 cmd->state.stencil_front_write =
5073 stencil_front_op_writes && stencil_front_writemask;
5074 cmd->state.stencil_back_write =
5075 stencil_back_op_writes && stencil_back_writemask;
5076 }
5077
5078 static bool
tu6_writes_depth(struct tu_cmd_buffer * cmd,bool depth_test_enable)5079 tu6_writes_depth(struct tu_cmd_buffer *cmd, bool depth_test_enable)
5080 {
5081 bool depth_write_enable =
5082 cmd->vk.dynamic_graphics_state.ds.depth.write_enable;
5083
5084 VkCompareOp depth_compare_op = (VkCompareOp)
5085 cmd->vk.dynamic_graphics_state.ds.depth.compare_op;
5086
5087 bool depth_compare_op_writes = depth_compare_op != VK_COMPARE_OP_NEVER;
5088
5089 return depth_test_enable && depth_write_enable && depth_compare_op_writes;
5090 }
5091
5092 static bool
tu6_writes_stencil(struct tu_cmd_buffer * cmd)5093 tu6_writes_stencil(struct tu_cmd_buffer *cmd)
5094 {
5095 return cmd->state.stencil_front_write || cmd->state.stencil_back_write;
5096 }
5097
5098 static void
tu6_build_depth_plane_z_mode(struct tu_cmd_buffer * cmd,struct tu_cs * cs)5099 tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
5100 {
5101 enum a6xx_ztest_mode zmode = A6XX_EARLY_Z;
5102 bool depth_test_enable = cmd->vk.dynamic_graphics_state.ds.depth.test_enable;
5103 bool depth_write = tu6_writes_depth(cmd, depth_test_enable);
5104 bool stencil_write = tu6_writes_stencil(cmd);
5105 const struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5106 const struct tu_render_pass *pass = cmd->state.pass;
5107 const struct tu_subpass *subpass = cmd->state.subpass;
5108
5109 if ((fs->variant->has_kill ||
5110 (cmd->state.pipeline_feedback_loops & VK_IMAGE_ASPECT_DEPTH_BIT) ||
5111 (cmd->vk.dynamic_graphics_state.feedback_loops &
5112 VK_IMAGE_ASPECT_DEPTH_BIT)) &&
5113 (depth_write || stencil_write)) {
5114 zmode = (cmd->state.lrz.valid && cmd->state.lrz.enabled)
5115 ? A6XX_EARLY_LRZ_LATE_Z
5116 : A6XX_LATE_Z;
5117 }
5118
5119 bool force_late_z =
5120 (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED &&
5121 pass->attachments[subpass->depth_stencil_attachment.attachment].format
5122 == VK_FORMAT_S8_UINT) ||
5123 fs->fs.lrz.force_late_z ||
5124 /* alpha-to-coverage can behave like a discard. */
5125 cmd->vk.dynamic_graphics_state.ms.alpha_to_coverage_enable;
5126 if ((force_late_z && !fs->variant->fs.early_fragment_tests) ||
5127 !depth_test_enable)
5128 zmode = A6XX_LATE_Z;
5129
5130 /* User defined early tests take precedence above all else */
5131 if (fs->variant->fs.early_fragment_tests)
5132 zmode = A6XX_EARLY_Z;
5133
5134 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
5135 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
5136
5137 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
5138 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
5139 }
5140
5141 static uint32_t
fs_params_offset(struct tu_cmd_buffer * cmd)5142 fs_params_offset(struct tu_cmd_buffer *cmd)
5143 {
5144 const struct tu_program_descriptor_linkage *link =
5145 &cmd->state.program.link[MESA_SHADER_FRAGMENT];
5146 const struct ir3_const_state *const_state = &link->const_state;
5147
5148 if (const_state->num_driver_params <= IR3_DP_FS_DYNAMIC)
5149 return 0;
5150
5151 if (const_state->offsets.driver_param + IR3_DP_FS_DYNAMIC / 4 >= link->constlen)
5152 return 0;
5153
5154 return const_state->offsets.driver_param + IR3_DP_FS_DYNAMIC / 4;
5155 }
5156
5157 static uint32_t
fs_params_size(struct tu_cmd_buffer * cmd)5158 fs_params_size(struct tu_cmd_buffer *cmd)
5159 {
5160 const struct tu_program_descriptor_linkage *link =
5161 &cmd->state.program.link[MESA_SHADER_FRAGMENT];
5162 const struct ir3_const_state *const_state = &link->const_state;
5163
5164 return DIV_ROUND_UP(const_state->num_driver_params - IR3_DP_FS_DYNAMIC, 4);
5165 }
5166
5167 struct apply_fs_params_state {
5168 unsigned num_consts;
5169 };
5170
5171 static void
fdm_apply_fs_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,void * data,VkRect2D bin,unsigned views,VkExtent2D * frag_areas)5172 fdm_apply_fs_params(struct tu_cmd_buffer *cmd,
5173 struct tu_cs *cs,
5174 void *data,
5175 VkRect2D bin,
5176 unsigned views,
5177 VkExtent2D *frag_areas)
5178 {
5179 const struct apply_fs_params_state *state =
5180 (const struct apply_fs_params_state *)data;
5181 unsigned num_consts = state->num_consts;
5182
5183 for (unsigned i = 0; i < num_consts; i++) {
5184 assert(i < views);
5185 VkExtent2D area = frag_areas[i];
5186 VkOffset2D offset = tu_fdm_per_bin_offset(area, bin);
5187
5188 tu_cs_emit(cs, area.width);
5189 tu_cs_emit(cs, area.height);
5190 tu_cs_emit(cs, fui(offset.x));
5191 tu_cs_emit(cs, fui(offset.y));
5192 }
5193 }
5194
5195 static void
tu_emit_fdm_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_shader * fs,unsigned num_units)5196 tu_emit_fdm_params(struct tu_cmd_buffer *cmd,
5197 struct tu_cs *cs, struct tu_shader *fs,
5198 unsigned num_units)
5199 {
5200 STATIC_ASSERT(IR3_DP_FS_FRAG_INVOCATION_COUNT == IR3_DP_FS_DYNAMIC);
5201 tu_cs_emit(cs, fs->fs.per_samp ?
5202 cmd->vk.dynamic_graphics_state.ms.rasterization_samples : 1);
5203 tu_cs_emit(cs, 0);
5204 tu_cs_emit(cs, 0);
5205 tu_cs_emit(cs, 0);
5206
5207 STATIC_ASSERT(IR3_DP_FS_FRAG_SIZE == IR3_DP_FS_DYNAMIC + 4);
5208 STATIC_ASSERT(IR3_DP_FS_FRAG_OFFSET == IR3_DP_FS_DYNAMIC + 6);
5209 if (num_units > 1) {
5210 if (fs->fs.has_fdm) {
5211 struct apply_fs_params_state state = {
5212 .num_consts = num_units - 1,
5213 };
5214 tu_create_fdm_bin_patchpoint(cmd, cs, 4 * (num_units - 1),
5215 fdm_apply_fs_params, state);
5216 } else {
5217 for (unsigned i = 1; i < num_units; i++) {
5218 tu_cs_emit(cs, 1);
5219 tu_cs_emit(cs, 1);
5220 tu_cs_emit(cs, fui(0.0f));
5221 tu_cs_emit(cs, fui(0.0f));
5222 }
5223 }
5224 }
5225 }
5226
5227 static void
tu6_emit_fs_params(struct tu_cmd_buffer * cmd)5228 tu6_emit_fs_params(struct tu_cmd_buffer *cmd)
5229 {
5230 uint32_t offset = fs_params_offset(cmd);
5231
5232 if (offset == 0) {
5233 cmd->state.fs_params = (struct tu_draw_state) {};
5234 return;
5235 }
5236
5237 struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5238
5239 unsigned num_units = fs_params_size(cmd);
5240
5241 if (fs->fs.has_fdm)
5242 tu_cs_set_writeable(&cmd->sub_cs, true);
5243
5244 struct tu_cs cs;
5245 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 4 + 4 * num_units, &cs);
5246 if (result != VK_SUCCESS) {
5247 tu_cs_set_writeable(&cmd->sub_cs, false);
5248 vk_command_buffer_set_error(&cmd->vk, result);
5249 return;
5250 }
5251
5252 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3 + 4 * num_units);
5253 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
5254 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
5255 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5256 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
5257 CP_LOAD_STATE6_0_NUM_UNIT(num_units));
5258 tu_cs_emit(&cs, 0);
5259 tu_cs_emit(&cs, 0);
5260
5261 tu_emit_fdm_params(cmd, &cs, fs, num_units);
5262
5263 cmd->state.fs_params = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5264
5265 if (fs->fs.has_fdm)
5266 tu_cs_set_writeable(&cmd->sub_cs, false);
5267 }
5268
5269 static void
tu7_emit_fs_params(struct tu_cmd_buffer * cmd)5270 tu7_emit_fs_params(struct tu_cmd_buffer *cmd)
5271 {
5272 struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5273
5274 int ubo_offset = fs->const_state.fdm_ubo.idx;
5275 if (ubo_offset < 0) {
5276 cmd->state.fs_params = (struct tu_draw_state) {};
5277 return;
5278 }
5279
5280 unsigned num_units = DIV_ROUND_UP(fs->const_state.fdm_ubo.size, 4);
5281
5282 if (fs->fs.has_fdm)
5283 tu_cs_set_writeable(&cmd->sub_cs, true);
5284
5285 struct tu_cs cs;
5286 VkResult result =
5287 tu_cs_begin_sub_stream_aligned(&cmd->sub_cs, num_units, 4, &cs);
5288 if (result != VK_SUCCESS) {
5289 tu_cs_set_writeable(&cmd->sub_cs, false);
5290 vk_command_buffer_set_error(&cmd->vk, result);
5291 return;
5292 }
5293
5294 tu_emit_fdm_params(cmd, &cs, fs, num_units);
5295
5296 struct tu_draw_state fdm_ubo = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5297
5298 if (fs->fs.has_fdm)
5299 tu_cs_set_writeable(&cmd->sub_cs, false);
5300
5301 result = tu_cs_begin_sub_stream(&cmd->sub_cs, 6, &cs);
5302 if (result != VK_SUCCESS) {
5303 vk_command_buffer_set_error(&cmd->vk, result);
5304 return;
5305 }
5306
5307 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 5);
5308 tu_cs_emit(&cs,
5309 CP_LOAD_STATE6_0_DST_OFF(ubo_offset) |
5310 CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO)|
5311 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5312 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
5313 CP_LOAD_STATE6_0_NUM_UNIT(1));
5314 tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
5315 tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
5316 tu_cs_emit_qw(&cs,
5317 fdm_ubo.iova |
5318 (uint64_t)A6XX_UBO_1_SIZE(num_units) << 32);
5319
5320 cmd->state.fs_params = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5321 }
5322
5323 static void
tu_emit_fs_params(struct tu_cmd_buffer * cmd)5324 tu_emit_fs_params(struct tu_cmd_buffer *cmd)
5325 {
5326 if (cmd->device->compiler->load_shader_consts_via_preamble)
5327 tu7_emit_fs_params(cmd);
5328 else
5329 tu6_emit_fs_params(cmd);
5330 }
5331
5332 template <chip CHIP>
5333 static VkResult
tu6_draw_common(struct tu_cmd_buffer * cmd,struct tu_cs * cs,bool indexed,uint32_t draw_count)5334 tu6_draw_common(struct tu_cmd_buffer *cmd,
5335 struct tu_cs *cs,
5336 bool indexed,
5337 /* note: draw_count is 0 for indirect */
5338 uint32_t draw_count)
5339 {
5340 const struct tu_program_state *program = &cmd->state.program;
5341 struct tu_render_pass_state *rp = &cmd->state.rp;
5342
5343 /* Emit state first, because it's needed for bandwidth calculations */
5344 uint32_t dynamic_draw_state_dirty = 0;
5345 if (!BITSET_IS_EMPTY(cmd->vk.dynamic_graphics_state.dirty) ||
5346 (cmd->state.dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS)) {
5347 dynamic_draw_state_dirty = tu_emit_draw_state<CHIP>(cmd);
5348 }
5349
5350 /* Primitive restart value works in non-indexed draws, we have to disable
5351 * prim restart for such draws since we may read stale restart index.
5352 */
5353 if (cmd->state.last_draw_indexed != indexed) {
5354 cmd->state.last_draw_indexed = indexed;
5355 BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
5356 MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE);
5357 }
5358
5359 /* Fill draw stats for autotuner */
5360 rp->drawcall_count++;
5361
5362 rp->drawcall_bandwidth_per_sample_sum +=
5363 cmd->state.bandwidth.color_bandwidth_per_sample;
5364
5365 /* add depth memory bandwidth cost */
5366 const uint32_t depth_bandwidth = cmd->state.bandwidth.depth_cpp_per_sample;
5367 if (cmd->vk.dynamic_graphics_state.ds.depth.write_enable)
5368 rp->drawcall_bandwidth_per_sample_sum += depth_bandwidth;
5369 if (cmd->vk.dynamic_graphics_state.ds.depth.test_enable)
5370 rp->drawcall_bandwidth_per_sample_sum += depth_bandwidth;
5371
5372 /* add stencil memory bandwidth cost */
5373 const uint32_t stencil_bandwidth =
5374 cmd->state.bandwidth.stencil_cpp_per_sample;
5375 if (cmd->vk.dynamic_graphics_state.ds.stencil.test_enable)
5376 rp->drawcall_bandwidth_per_sample_sum += stencil_bandwidth * 2;
5377
5378 tu_emit_cache_flush_renderpass<CHIP>(cmd);
5379
5380 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5381 MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE) ||
5382 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5383 MESA_VK_DYNAMIC_RS_PROVOKING_VERTEX) ||
5384 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5385 bool primitive_restart_enabled =
5386 cmd->vk.dynamic_graphics_state.ia.primitive_restart_enable;
5387
5388 bool primitive_restart = primitive_restart_enabled && indexed;
5389 bool provoking_vtx_last =
5390 cmd->vk.dynamic_graphics_state.rs.provoking_vertex ==
5391 VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT;
5392
5393 uint32_t primitive_cntl_0 =
5394 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart = primitive_restart,
5395 .provoking_vtx_last = provoking_vtx_last).value;
5396 tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(.dword = primitive_cntl_0));
5397 if (CHIP == A7XX) {
5398 tu_cs_emit_regs(cs, A7XX_VPC_PRIMITIVE_CNTL_0(.dword = primitive_cntl_0));
5399 }
5400 }
5401
5402 struct tu_tess_params *tess_params = &cmd->state.tess_params;
5403 if ((cmd->state.dirty & TU_CMD_DIRTY_TESS_PARAMS) ||
5404 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5405 MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN) ||
5406 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5407 bool tess_upper_left_domain_origin =
5408 (VkTessellationDomainOrigin)cmd->vk.dynamic_graphics_state.ts.domain_origin ==
5409 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
5410 tu_cs_emit_regs(cs, A6XX_PC_TESS_CNTL(
5411 .spacing = tess_params->spacing,
5412 .output = tess_upper_left_domain_origin ?
5413 tess_params->output_upper_left :
5414 tess_params->output_lower_left));
5415 }
5416
5417 /* Early exit if there is nothing to emit, saves CPU cycles */
5418 uint32_t dirty = cmd->state.dirty;
5419 if (!dynamic_draw_state_dirty && !(dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS))
5420 return VK_SUCCESS;
5421
5422 bool dirty_lrz =
5423 (dirty & TU_CMD_DIRTY_LRZ) ||
5424 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5425 MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE) ||
5426 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5427 MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE) ||
5428 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5429 MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE) ||
5430 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5431 MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP) ||
5432 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5433 MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
5434 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5435 MESA_VK_DYNAMIC_DS_STENCIL_OP) ||
5436 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5437 MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK) ||
5438 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5439 MESA_VK_DYNAMIC_MS_ALPHA_TO_COVERAGE_ENABLE) ||
5440 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5441 MESA_VK_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE);
5442
5443 if (dirty_lrz) {
5444 struct tu_cs cs;
5445 uint32_t size = 8 +
5446 (cmd->device->physical_device->info->a6xx.lrz_track_quirk ? 2 : 0) +
5447 (CHIP >= A7XX ? 2 : 0); // A7XX has extra packets from LRZ_CNTL2.
5448
5449 cmd->state.lrz_and_depth_plane_state =
5450 tu_cs_draw_state(&cmd->sub_cs, &cs, size);
5451 tu6_update_simplified_stencil_state(cmd);
5452 tu6_emit_lrz<CHIP>(cmd, &cs);
5453 tu6_build_depth_plane_z_mode(cmd, &cs);
5454 }
5455
5456 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5457 MESA_VK_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE)) {
5458 if (cmd->vk.dynamic_graphics_state.feedback_loops &&
5459 !cmd->state.rp.disable_gmem) {
5460 perf_debug(
5461 cmd->device,
5462 "Disabling gmem due to VK_EXT_attachment_feedback_loop_layout");
5463 cmd->state.rp.disable_gmem = true;
5464 }
5465 }
5466
5467 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5468 MESA_VK_DYNAMIC_VI_BINDINGS_VALID)) {
5469 cmd->state.vertex_buffers.size =
5470 util_last_bit(cmd->vk.dynamic_graphics_state.vi_bindings_valid) * 4;
5471 dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
5472 }
5473
5474 if (dirty & TU_CMD_DIRTY_SHADER_CONSTS)
5475 cmd->state.shader_const = tu_emit_consts(cmd, false);
5476
5477 if (dirty & TU_CMD_DIRTY_DESC_SETS)
5478 tu6_emit_descriptor_sets<CHIP>(cmd, VK_PIPELINE_BIND_POINT_GRAPHICS);
5479
5480 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5481 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
5482 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5483 MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
5484 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5485 MESA_VK_DYNAMIC_RS_LINE_MODE) ||
5486 (cmd->state.dirty & TU_CMD_DIRTY_TES) ||
5487 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5488 tu6_update_msaa_disable(cmd);
5489 }
5490
5491 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5492 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
5493 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5494 tu6_update_msaa(cmd);
5495 }
5496
5497 bool dirty_fs_params = false;
5498 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5499 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
5500 (cmd->state.dirty & (TU_CMD_DIRTY_PROGRAM | TU_CMD_DIRTY_FDM))) {
5501 tu_emit_fs_params(cmd);
5502 dirty_fs_params = true;
5503 }
5504
5505 /* for the first draw in a renderpass, re-emit all the draw states
5506 *
5507 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
5508 * used, then draw states must be re-emitted. note however this only happens
5509 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
5510 *
5511 * the two input attachment states are excluded because secondary command
5512 * buffer doesn't have a state ib to restore it, and not re-emitting them
5513 * is OK since CmdClearAttachments won't disable/overwrite them
5514 */
5515 if (dirty & TU_CMD_DIRTY_DRAW_STATE) {
5516 tu_pipeline_update_rp_state(&cmd->state);
5517
5518 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (TU_DRAW_STATE_COUNT - 2));
5519
5520 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, program->config_state);
5521 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS, program->vs_state);
5522 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_BINNING, program->vs_binning_state);
5523 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_HS, program->hs_state);
5524 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS, program->ds_state);
5525 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS, program->gs_state);
5526 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS_BINNING, program->gs_binning_state);
5527 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS, program->fs_state);
5528 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VPC, program->vpc_state);
5529 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, cmd->state.prim_order_gmem);
5530 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
5531 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
5532 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, cmd->state.load_state);
5533 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
5534 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
5535 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_PARAMS, cmd->state.fs_params);
5536 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
5537
5538 for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
5539 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
5540 cmd->state.dynamic_state[i]);
5541 }
5542 } else {
5543 /* emit draw states that were just updated */
5544 uint32_t draw_state_count =
5545 util_bitcount(dynamic_draw_state_dirty) +
5546 ((dirty & TU_CMD_DIRTY_SHADER_CONSTS) ? 1 : 0) +
5547 ((dirty & TU_CMD_DIRTY_DESC_SETS) ? 1 : 0) +
5548 ((dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) ? 1 : 0) +
5549 ((dirty & TU_CMD_DIRTY_VS_PARAMS) ? 1 : 0) +
5550 (dirty_fs_params ? 1 : 0) +
5551 (dirty_lrz ? 1 : 0);
5552
5553 if (draw_state_count > 0)
5554 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count);
5555
5556 if (dirty & TU_CMD_DIRTY_SHADER_CONSTS)
5557 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
5558 if (dirty & TU_CMD_DIRTY_DESC_SETS) {
5559 /* tu6_emit_descriptor_sets emitted the cmd->state.desc_sets draw state. */
5560 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, cmd->state.load_state);
5561 }
5562 if (dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
5563 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
5564 u_foreach_bit (i, dynamic_draw_state_dirty) {
5565 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
5566 cmd->state.dynamic_state[i]);
5567 }
5568 if (dirty & TU_CMD_DIRTY_VS_PARAMS)
5569 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
5570 if (dirty_fs_params)
5571 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_PARAMS, cmd->state.fs_params);
5572 if (dirty_lrz) {
5573 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
5574 }
5575 }
5576
5577 tu_cs_sanity_check(cs);
5578
5579 /* There are too many graphics dirty bits to list here, so just list the
5580 * bits to preserve instead. The only things not emitted here are
5581 * compute-related state.
5582 */
5583 cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESC_SETS;
5584 BITSET_ZERO(cmd->vk.dynamic_graphics_state.dirty);
5585 return VK_SUCCESS;
5586 }
5587
5588 static uint32_t
tu_draw_initiator(struct tu_cmd_buffer * cmd,enum pc_di_src_sel src_sel)5589 tu_draw_initiator(struct tu_cmd_buffer *cmd, enum pc_di_src_sel src_sel)
5590 {
5591 enum pc_di_primtype primtype =
5592 tu6_primtype((VkPrimitiveTopology)cmd->vk.dynamic_graphics_state.ia.primitive_topology);
5593
5594 if (primtype == DI_PT_PATCHES0)
5595 primtype = (enum pc_di_primtype) (primtype +
5596 cmd->vk.dynamic_graphics_state.ts.patch_control_points);
5597
5598 uint32_t initiator =
5599 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
5600 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel) |
5601 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE((enum a4xx_index_size) cmd->state.index_size) |
5602 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY);
5603
5604 if (cmd->state.shaders[MESA_SHADER_GEOMETRY]->variant)
5605 initiator |= CP_DRAW_INDX_OFFSET_0_GS_ENABLE;
5606
5607 const struct tu_shader *tes = cmd->state.shaders[MESA_SHADER_TESS_EVAL];
5608 if (tes->variant) {
5609 switch (tes->variant->key.tessellation) {
5610 case IR3_TESS_TRIANGLES:
5611 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES) |
5612 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
5613 break;
5614 case IR3_TESS_ISOLINES:
5615 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES) |
5616 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
5617 break;
5618 case IR3_TESS_QUADS:
5619 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS) |
5620 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
5621 break;
5622 }
5623 }
5624 return initiator;
5625 }
5626
5627
5628 static uint32_t
vs_params_offset(struct tu_cmd_buffer * cmd)5629 vs_params_offset(struct tu_cmd_buffer *cmd)
5630 {
5631 const struct tu_program_descriptor_linkage *link =
5632 &cmd->state.program.link[MESA_SHADER_VERTEX];
5633 const struct ir3_const_state *const_state = &link->const_state;
5634
5635 if (const_state->offsets.driver_param >= link->constlen)
5636 return 0;
5637
5638 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
5639 STATIC_ASSERT(IR3_DP_DRAWID == 0);
5640 STATIC_ASSERT(IR3_DP_VTXID_BASE == 1);
5641 STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
5642
5643 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
5644 assert(const_state->offsets.driver_param != 0);
5645
5646 return const_state->offsets.driver_param;
5647 }
5648
5649 static void
tu6_emit_empty_vs_params(struct tu_cmd_buffer * cmd)5650 tu6_emit_empty_vs_params(struct tu_cmd_buffer *cmd)
5651 {
5652 if (cmd->state.vs_params.iova) {
5653 cmd->state.vs_params = (struct tu_draw_state) {};
5654 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
5655 }
5656 }
5657
5658 static void
tu6_emit_vs_params(struct tu_cmd_buffer * cmd,uint32_t draw_id,uint32_t vertex_offset,uint32_t first_instance)5659 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
5660 uint32_t draw_id,
5661 uint32_t vertex_offset,
5662 uint32_t first_instance)
5663 {
5664 uint32_t offset = vs_params_offset(cmd);
5665
5666 /* Beside re-emitting params when they are changed, we should re-emit
5667 * them after constants are invalidated via HLSQ_INVALIDATE_CMD or after we
5668 * emit an empty vs params.
5669 */
5670 if (!(cmd->state.dirty & (TU_CMD_DIRTY_DRAW_STATE | TU_CMD_DIRTY_VS_PARAMS |
5671 TU_CMD_DIRTY_PROGRAM)) &&
5672 cmd->state.vs_params.iova &&
5673 (offset == 0 || draw_id == cmd->state.last_vs_params.draw_id) &&
5674 vertex_offset == cmd->state.last_vs_params.vertex_offset &&
5675 first_instance == cmd->state.last_vs_params.first_instance) {
5676 return;
5677 }
5678
5679 uint64_t consts_iova = 0;
5680 if (offset) {
5681 struct tu_cs_memory consts;
5682 VkResult result = tu_cs_alloc(&cmd->sub_cs, 1, 4, &consts);
5683 if (result != VK_SUCCESS) {
5684 vk_command_buffer_set_error(&cmd->vk, result);
5685 return;
5686 }
5687 consts.map[0] = draw_id;
5688 consts.map[1] = vertex_offset;
5689 consts.map[2] = first_instance;
5690 consts.map[3] = 0;
5691
5692 consts_iova = consts.iova;
5693 }
5694
5695 struct tu_cs cs;
5696 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 4 : 0), &cs);
5697 if (result != VK_SUCCESS) {
5698 vk_command_buffer_set_error(&cmd->vk, result);
5699 return;
5700 }
5701
5702 tu_cs_emit_regs(&cs,
5703 A6XX_VFD_INDEX_OFFSET(vertex_offset),
5704 A6XX_VFD_INSTANCE_START_OFFSET(first_instance));
5705
5706 /* It is implemented as INDIRECT load even on a750+ because with UBO
5707 * lowering it would be tricky to get const offset for to use in multidraw,
5708 * also we would need to ensure the offset is not 0.
5709 * TODO/A7XX: Rework vs params to use UBO lowering.
5710 */
5711 if (offset) {
5712 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3);
5713 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
5714 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
5715 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
5716 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
5717 CP_LOAD_STATE6_0_NUM_UNIT(1));
5718 tu_cs_emit_qw(&cs, consts_iova);
5719 }
5720
5721 cmd->state.last_vs_params.vertex_offset = vertex_offset;
5722 cmd->state.last_vs_params.first_instance = first_instance;
5723 cmd->state.last_vs_params.draw_id = draw_id;
5724
5725 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
5726 cmd->state.vs_params = (struct tu_draw_state) {entry.bo->iova + entry.offset, entry.size / 4};
5727
5728 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
5729 }
5730
5731 template <chip CHIP>
5732 VKAPI_ATTR void VKAPI_CALL
tu_CmdDraw(VkCommandBuffer commandBuffer,uint32_t vertexCount,uint32_t instanceCount,uint32_t firstVertex,uint32_t firstInstance)5733 tu_CmdDraw(VkCommandBuffer commandBuffer,
5734 uint32_t vertexCount,
5735 uint32_t instanceCount,
5736 uint32_t firstVertex,
5737 uint32_t firstInstance)
5738 {
5739 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5740 struct tu_cs *cs = &cmd->draw_cs;
5741
5742 tu6_emit_vs_params(cmd, 0, firstVertex, firstInstance);
5743
5744 tu6_draw_common<CHIP>(cmd, cs, false, vertexCount);
5745
5746 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
5747 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
5748 tu_cs_emit(cs, instanceCount);
5749 tu_cs_emit(cs, vertexCount);
5750 }
5751 TU_GENX(tu_CmdDraw);
5752
5753 template <chip CHIP>
5754 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawMultiEXT(VkCommandBuffer commandBuffer,uint32_t drawCount,const VkMultiDrawInfoEXT * pVertexInfo,uint32_t instanceCount,uint32_t firstInstance,uint32_t stride)5755 tu_CmdDrawMultiEXT(VkCommandBuffer commandBuffer,
5756 uint32_t drawCount,
5757 const VkMultiDrawInfoEXT *pVertexInfo,
5758 uint32_t instanceCount,
5759 uint32_t firstInstance,
5760 uint32_t stride)
5761 {
5762 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5763 struct tu_cs *cs = &cmd->draw_cs;
5764
5765 if (!drawCount)
5766 return;
5767
5768 bool has_tess = cmd->state.shaders[MESA_SHADER_TESS_CTRL]->variant;
5769
5770 uint32_t max_vertex_count = 0;
5771 if (has_tess) {
5772 uint32_t i = 0;
5773 vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
5774 max_vertex_count = MAX2(max_vertex_count, draw->vertexCount);
5775 }
5776 }
5777
5778 uint32_t i = 0;
5779 vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
5780 tu6_emit_vs_params(cmd, i, draw->firstVertex, firstInstance);
5781
5782 if (i == 0)
5783 tu6_draw_common<CHIP>(cmd, cs, false, max_vertex_count);
5784
5785 if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS) {
5786 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
5787 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
5788 cmd->state.dirty &= ~TU_CMD_DIRTY_VS_PARAMS;
5789 }
5790
5791 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
5792 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
5793 tu_cs_emit(cs, instanceCount);
5794 tu_cs_emit(cs, draw->vertexCount);
5795 }
5796 }
5797 TU_GENX(tu_CmdDrawMultiEXT);
5798
5799 template <chip CHIP>
5800 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,uint32_t indexCount,uint32_t instanceCount,uint32_t firstIndex,int32_t vertexOffset,uint32_t firstInstance)5801 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
5802 uint32_t indexCount,
5803 uint32_t instanceCount,
5804 uint32_t firstIndex,
5805 int32_t vertexOffset,
5806 uint32_t firstInstance)
5807 {
5808 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5809 struct tu_cs *cs = &cmd->draw_cs;
5810
5811 tu6_emit_vs_params(cmd, 0, vertexOffset, firstInstance);
5812
5813 tu6_draw_common<CHIP>(cmd, cs, true, indexCount);
5814
5815 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
5816 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
5817 tu_cs_emit(cs, instanceCount);
5818 tu_cs_emit(cs, indexCount);
5819 tu_cs_emit(cs, firstIndex);
5820 tu_cs_emit_qw(cs, cmd->state.index_va);
5821 tu_cs_emit(cs, cmd->state.max_index_count);
5822 }
5823 TU_GENX(tu_CmdDrawIndexed);
5824
5825 template <chip CHIP>
5826 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawMultiIndexedEXT(VkCommandBuffer commandBuffer,uint32_t drawCount,const VkMultiDrawIndexedInfoEXT * pIndexInfo,uint32_t instanceCount,uint32_t firstInstance,uint32_t stride,const int32_t * pVertexOffset)5827 tu_CmdDrawMultiIndexedEXT(VkCommandBuffer commandBuffer,
5828 uint32_t drawCount,
5829 const VkMultiDrawIndexedInfoEXT *pIndexInfo,
5830 uint32_t instanceCount,
5831 uint32_t firstInstance,
5832 uint32_t stride,
5833 const int32_t *pVertexOffset)
5834 {
5835 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5836 struct tu_cs *cs = &cmd->draw_cs;
5837
5838 if (!drawCount)
5839 return;
5840
5841 bool has_tess = cmd->state.shaders[MESA_SHADER_TESS_CTRL]->variant;
5842
5843 uint32_t max_index_count = 0;
5844 if (has_tess) {
5845 uint32_t i = 0;
5846 vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
5847 max_index_count = MAX2(max_index_count, draw->indexCount);
5848 }
5849 }
5850
5851 uint32_t i = 0;
5852 vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
5853 int32_t vertexOffset = pVertexOffset ? *pVertexOffset : draw->vertexOffset;
5854 tu6_emit_vs_params(cmd, i, vertexOffset, firstInstance);
5855
5856 if (i == 0)
5857 tu6_draw_common<CHIP>(cmd, cs, true, max_index_count);
5858
5859 if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS) {
5860 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
5861 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
5862 cmd->state.dirty &= ~TU_CMD_DIRTY_VS_PARAMS;
5863 }
5864
5865 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
5866 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
5867 tu_cs_emit(cs, instanceCount);
5868 tu_cs_emit(cs, draw->indexCount);
5869 tu_cs_emit(cs, draw->firstIndex);
5870 tu_cs_emit_qw(cs, cmd->state.index_va);
5871 tu_cs_emit(cs, cmd->state.max_index_count);
5872 }
5873 }
5874 TU_GENX(tu_CmdDrawMultiIndexedEXT);
5875
5876 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
5877 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
5878 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
5879 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
5880 * before draw opcodes that don't need it.
5881 */
5882 static void
draw_wfm(struct tu_cmd_buffer * cmd)5883 draw_wfm(struct tu_cmd_buffer *cmd)
5884 {
5885 cmd->state.renderpass_cache.flush_bits |=
5886 cmd->state.renderpass_cache.pending_flush_bits & TU_CMD_FLAG_WAIT_FOR_ME;
5887 cmd->state.renderpass_cache.pending_flush_bits &= ~TU_CMD_FLAG_WAIT_FOR_ME;
5888 }
5889
5890 template <chip CHIP>
5891 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,uint32_t drawCount,uint32_t stride)5892 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
5893 VkBuffer _buffer,
5894 VkDeviceSize offset,
5895 uint32_t drawCount,
5896 uint32_t stride)
5897 {
5898 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5899 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
5900 struct tu_cs *cs = &cmd->draw_cs;
5901
5902 tu6_emit_empty_vs_params(cmd);
5903
5904 if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
5905 draw_wfm(cmd);
5906
5907 tu6_draw_common<CHIP>(cmd, cs, false, 0);
5908
5909 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6);
5910 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
5911 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) |
5912 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
5913 tu_cs_emit(cs, drawCount);
5914 tu_cs_emit_qw(cs, buf->iova + offset);
5915 tu_cs_emit(cs, stride);
5916 }
5917 TU_GENX(tu_CmdDrawIndirect);
5918
5919 template <chip CHIP>
5920 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,uint32_t drawCount,uint32_t stride)5921 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
5922 VkBuffer _buffer,
5923 VkDeviceSize offset,
5924 uint32_t drawCount,
5925 uint32_t stride)
5926 {
5927 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5928 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
5929 struct tu_cs *cs = &cmd->draw_cs;
5930
5931 tu6_emit_empty_vs_params(cmd);
5932
5933 if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
5934 draw_wfm(cmd);
5935
5936 tu6_draw_common<CHIP>(cmd, cs, true, 0);
5937
5938 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9);
5939 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
5940 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) |
5941 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
5942 tu_cs_emit(cs, drawCount);
5943 tu_cs_emit_qw(cs, cmd->state.index_va);
5944 tu_cs_emit(cs, cmd->state.max_index_count);
5945 tu_cs_emit_qw(cs, buf->iova + offset);
5946 tu_cs_emit(cs, stride);
5947 }
5948 TU_GENX(tu_CmdDrawIndexedIndirect);
5949
5950 template <chip CHIP>
5951 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,VkBuffer countBuffer,VkDeviceSize countBufferOffset,uint32_t drawCount,uint32_t stride)5952 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,
5953 VkBuffer _buffer,
5954 VkDeviceSize offset,
5955 VkBuffer countBuffer,
5956 VkDeviceSize countBufferOffset,
5957 uint32_t drawCount,
5958 uint32_t stride)
5959 {
5960 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5961 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
5962 VK_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
5963 struct tu_cs *cs = &cmd->draw_cs;
5964
5965 tu6_emit_empty_vs_params(cmd);
5966
5967 /* It turns out that the firmware we have for a650 only partially fixed the
5968 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
5969 * before reading indirect parameters. It waits for WFI's before reading
5970 * the draw parameters, but after reading the indirect count :(.
5971 */
5972 draw_wfm(cmd);
5973
5974 tu6_draw_common<CHIP>(cmd, cs, false, 0);
5975
5976 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 8);
5977 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
5978 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT) |
5979 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
5980 tu_cs_emit(cs, drawCount);
5981 tu_cs_emit_qw(cs, buf->iova + offset);
5982 tu_cs_emit_qw(cs, count_buf->iova + countBufferOffset);
5983 tu_cs_emit(cs, stride);
5984 }
5985 TU_GENX(tu_CmdDrawIndirectCount);
5986
5987 template <chip CHIP>
5988 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,VkBuffer countBuffer,VkDeviceSize countBufferOffset,uint32_t drawCount,uint32_t stride)5989 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,
5990 VkBuffer _buffer,
5991 VkDeviceSize offset,
5992 VkBuffer countBuffer,
5993 VkDeviceSize countBufferOffset,
5994 uint32_t drawCount,
5995 uint32_t stride)
5996 {
5997 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5998 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
5999 VK_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
6000 struct tu_cs *cs = &cmd->draw_cs;
6001
6002 tu6_emit_empty_vs_params(cmd);
6003
6004 draw_wfm(cmd);
6005
6006 tu6_draw_common<CHIP>(cmd, cs, true, 0);
6007
6008 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 11);
6009 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
6010 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED) |
6011 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
6012 tu_cs_emit(cs, drawCount);
6013 tu_cs_emit_qw(cs, cmd->state.index_va);
6014 tu_cs_emit(cs, cmd->state.max_index_count);
6015 tu_cs_emit_qw(cs, buf->iova + offset);
6016 tu_cs_emit_qw(cs, count_buf->iova + countBufferOffset);
6017 tu_cs_emit(cs, stride);
6018 }
6019 TU_GENX(tu_CmdDrawIndexedIndirectCount);
6020
6021 template <chip CHIP>
6022 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,uint32_t instanceCount,uint32_t firstInstance,VkBuffer _counterBuffer,VkDeviceSize counterBufferOffset,uint32_t counterOffset,uint32_t vertexStride)6023 tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
6024 uint32_t instanceCount,
6025 uint32_t firstInstance,
6026 VkBuffer _counterBuffer,
6027 VkDeviceSize counterBufferOffset,
6028 uint32_t counterOffset,
6029 uint32_t vertexStride)
6030 {
6031 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6032 VK_FROM_HANDLE(tu_buffer, buf, _counterBuffer);
6033 struct tu_cs *cs = &cmd->draw_cs;
6034
6035 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
6036 * Plus, for the common case where the counter buffer is written by
6037 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
6038 * complete which means we need a WAIT_FOR_ME anyway.
6039 */
6040 draw_wfm(cmd);
6041
6042 tu6_emit_vs_params(cmd, 0, 0, firstInstance);
6043
6044 tu6_draw_common<CHIP>(cmd, cs, false, 0);
6045
6046 tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6);
6047 if (CHIP == A6XX) {
6048 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB));
6049 } else {
6050 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
6051 /* On a7xx the counter value and offset are shifted right by 2, so
6052 * the vertexStride should also be in units of dwords.
6053 */
6054 vertexStride = vertexStride >> 2;
6055 }
6056 tu_cs_emit(cs, instanceCount);
6057 tu_cs_emit_qw(cs, buf->iova + counterBufferOffset);
6058 tu_cs_emit(cs, counterOffset);
6059 tu_cs_emit(cs, vertexStride);
6060 }
6061 TU_GENX(tu_CmdDrawIndirectByteCountEXT);
6062
6063 struct tu_dispatch_info
6064 {
6065 /**
6066 * Determine the layout of the grid (in block units) to be used.
6067 */
6068 uint32_t blocks[3];
6069
6070 /**
6071 * A starting offset for the grid. If unaligned is set, the offset
6072 * must still be aligned.
6073 */
6074 uint32_t offsets[3];
6075 /**
6076 * Whether it's an unaligned compute dispatch.
6077 */
6078 bool unaligned;
6079
6080 /**
6081 * Indirect compute parameters resource.
6082 */
6083 struct tu_buffer *indirect;
6084 uint64_t indirect_offset;
6085 };
6086
6087 template <chip CHIP>
6088 static void
tu_emit_compute_driver_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,const struct tu_dispatch_info * info)6089 tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd,
6090 struct tu_cs *cs,
6091 const struct tu_dispatch_info *info)
6092 {
6093 gl_shader_stage type = MESA_SHADER_COMPUTE;
6094 const struct tu_shader *shader = cmd->state.shaders[MESA_SHADER_COMPUTE];
6095 const struct ir3_shader_variant *variant = shader->variant;
6096 const struct ir3_const_state *const_state = variant->const_state;
6097 unsigned subgroup_size = variant->info.subgroup_size;
6098 unsigned subgroup_shift = util_logbase2(subgroup_size);
6099
6100 if (cmd->device->physical_device->info->a7xx.load_shader_consts_via_preamble) {
6101 uint32_t num_consts = const_state->driver_params_ubo.size;
6102 if (num_consts == 0)
6103 return;
6104
6105 bool direct_indirect_load =
6106 !(info->indirect_offset & 0xf) &&
6107 !(info->indirect && num_consts > IR3_DP_BASE_GROUP_X);
6108
6109 uint64_t iova = 0;
6110
6111 if (!info->indirect) {
6112 uint32_t driver_params[12] = {
6113 [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
6114 [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
6115 [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
6116 [IR3_DP_WORK_DIM] = 0,
6117 [IR3_DP_BASE_GROUP_X] = info->offsets[0],
6118 [IR3_DP_BASE_GROUP_Y] = info->offsets[1],
6119 [IR3_DP_BASE_GROUP_Z] = info->offsets[2],
6120 [IR3_DP_CS_SUBGROUP_SIZE] = subgroup_size,
6121 [IR3_DP_LOCAL_GROUP_SIZE_X] = 0,
6122 [IR3_DP_LOCAL_GROUP_SIZE_Y] = 0,
6123 [IR3_DP_LOCAL_GROUP_SIZE_Z] = 0,
6124 [IR3_DP_SUBGROUP_ID_SHIFT] = subgroup_shift,
6125 };
6126
6127 assert(num_consts <= ARRAY_SIZE(driver_params));
6128
6129 struct tu_cs_memory consts;
6130 uint32_t consts_vec4 = DIV_ROUND_UP(num_consts, 4);
6131 VkResult result = tu_cs_alloc(&cmd->sub_cs, consts_vec4, 4, &consts);
6132 if (result != VK_SUCCESS) {
6133 vk_command_buffer_set_error(&cmd->vk, result);
6134 return;
6135 }
6136 memcpy(consts.map, driver_params, num_consts * sizeof(uint32_t));
6137 iova = consts.iova;
6138 } else if (direct_indirect_load) {
6139 iova = info->indirect->iova + info->indirect_offset;
6140 } else {
6141 /* Vulkan guarantees only 4 byte alignment for indirect_offset.
6142 * However, CP_LOAD_STATE.EXT_SRC_ADDR needs 16 byte alignment.
6143 */
6144
6145 uint64_t indirect_iova = info->indirect->iova + info->indirect_offset;
6146
6147 /* Wait for any previous uses to finish. */
6148 tu_cs_emit_wfi(cs);
6149
6150 for (uint32_t i = 0; i < 3; i++) {
6151 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
6152 tu_cs_emit(cs, 0);
6153 tu_cs_emit_qw(cs, global_iova_arr(cmd, cs_indirect_xyz, i));
6154 tu_cs_emit_qw(cs, indirect_iova + i * sizeof(uint32_t));
6155 }
6156
6157 /* Fill out IR3_DP_CS_SUBGROUP_SIZE and IR3_DP_SUBGROUP_ID_SHIFT for
6158 * indirect dispatch.
6159 */
6160 if (info->indirect && num_consts > IR3_DP_BASE_GROUP_X) {
6161 uint32_t indirect_driver_params[8] = {
6162 0, 0, 0, subgroup_size,
6163 0, 0, 0, subgroup_shift,
6164 };
6165 bool emit_local = num_consts > IR3_DP_LOCAL_GROUP_SIZE_X;
6166 uint32_t emit_size = emit_local ? 8 : 4;
6167
6168 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + emit_size);
6169 tu_cs_emit_qw(cs, global_iova_arr(cmd, cs_indirect_xyz, 0) + 4 * sizeof(uint32_t));
6170 for (uint32_t i = 0; i < emit_size; i++) {
6171 tu_cs_emit(cs, indirect_driver_params[i]);
6172 }
6173 }
6174
6175 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
6176 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
6177 tu_cs_emit_wfi(cs);
6178
6179 iova = global_iova(cmd, cs_indirect_xyz[0]);
6180 }
6181
6182 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 5);
6183 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(const_state->driver_params_ubo.idx) |
6184 CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO) |
6185 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
6186 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6187 CP_LOAD_STATE6_0_NUM_UNIT(1));
6188 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
6189 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
6190 int size_vec4s = DIV_ROUND_UP(num_consts, 4);
6191 tu_cs_emit_qw(cs, iova | ((uint64_t)A6XX_UBO_1_SIZE(size_vec4s) << 32));
6192
6193 } else {
6194 uint32_t offset = const_state->offsets.driver_param;
6195 if (variant->constlen <= offset)
6196 return;
6197
6198 uint32_t num_consts = MIN2(const_state->num_driver_params,
6199 (variant->constlen - offset) * 4);
6200
6201 if (!info->indirect) {
6202 uint32_t driver_params[12] = {
6203 [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
6204 [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
6205 [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
6206 [IR3_DP_WORK_DIM] = 0,
6207 [IR3_DP_BASE_GROUP_X] = info->offsets[0],
6208 [IR3_DP_BASE_GROUP_Y] = info->offsets[1],
6209 [IR3_DP_BASE_GROUP_Z] = info->offsets[2],
6210 [IR3_DP_CS_SUBGROUP_SIZE] = subgroup_size,
6211 [IR3_DP_LOCAL_GROUP_SIZE_X] = 0,
6212 [IR3_DP_LOCAL_GROUP_SIZE_Y] = 0,
6213 [IR3_DP_LOCAL_GROUP_SIZE_Z] = 0,
6214 [IR3_DP_SUBGROUP_ID_SHIFT] = subgroup_shift,
6215 };
6216
6217 assert(num_consts <= ARRAY_SIZE(driver_params));
6218
6219 /* push constants */
6220 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
6221 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6222 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6223 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
6224 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6225 CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
6226 tu_cs_emit(cs, 0);
6227 tu_cs_emit(cs, 0);
6228 uint32_t i;
6229 for (i = 0; i < num_consts; i++)
6230 tu_cs_emit(cs, driver_params[i]);
6231 } else if (!(info->indirect_offset & 0xf)) {
6232 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
6233 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6234 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6235 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
6236 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6237 CP_LOAD_STATE6_0_NUM_UNIT(1));
6238 tu_cs_emit_qw(cs, info->indirect->iova + info->indirect_offset);
6239 } else {
6240 /* Vulkan guarantees only 4 byte alignment for indirect_offset.
6241 * However, CP_LOAD_STATE.EXT_SRC_ADDR needs 16 byte alignment.
6242 */
6243
6244 uint64_t indirect_iova = info->indirect->iova + info->indirect_offset;
6245
6246 /* Wait for any previous uses to finish. */
6247 tu_cs_emit_wfi(cs);
6248
6249 for (uint32_t i = 0; i < 3; i++) {
6250 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
6251 tu_cs_emit(cs, 0);
6252 tu_cs_emit_qw(cs, global_iova_arr(cmd, cs_indirect_xyz, i));
6253 tu_cs_emit_qw(cs, indirect_iova + i * 4);
6254 }
6255
6256 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
6257 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
6258 tu_cs_emit_wfi(cs);
6259
6260 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
6261 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6262 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6263 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
6264 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6265 CP_LOAD_STATE6_0_NUM_UNIT(1));
6266 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[0]));
6267 }
6268
6269 /* Fill out IR3_DP_CS_SUBGROUP_SIZE and IR3_DP_SUBGROUP_ID_SHIFT for
6270 * indirect dispatch.
6271 */
6272 if (info->indirect && num_consts > IR3_DP_BASE_GROUP_X) {
6273 bool emit_local = num_consts > IR3_DP_LOCAL_GROUP_SIZE_X;
6274 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 7 + (emit_local ? 4 : 0));
6275 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset + (IR3_DP_BASE_GROUP_X / 4)) |
6276 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6277 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
6278 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6279 CP_LOAD_STATE6_0_NUM_UNIT((num_consts - IR3_DP_BASE_GROUP_X) / 4));
6280 tu_cs_emit_qw(cs, 0);
6281 tu_cs_emit(cs, 0); /* BASE_GROUP_X */
6282 tu_cs_emit(cs, 0); /* BASE_GROUP_Y */
6283 tu_cs_emit(cs, 0); /* BASE_GROUP_Z */
6284 tu_cs_emit(cs, subgroup_size);
6285 if (emit_local) {
6286 assert(num_consts == align(IR3_DP_SUBGROUP_ID_SHIFT, 4));
6287 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_X */
6288 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Y */
6289 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Z */
6290 tu_cs_emit(cs, subgroup_shift);
6291 }
6292 }
6293 }
6294 }
6295
6296 template <chip CHIP>
6297 static void
tu_dispatch(struct tu_cmd_buffer * cmd,const struct tu_dispatch_info * info)6298 tu_dispatch(struct tu_cmd_buffer *cmd,
6299 const struct tu_dispatch_info *info)
6300 {
6301 if (!info->indirect &&
6302 (info->blocks[0] == 0 || info->blocks[1] == 0 || info->blocks[2] == 0))
6303 return;
6304
6305 struct tu_cs *cs = &cmd->cs;
6306 struct tu_shader *shader = cmd->state.shaders[MESA_SHADER_COMPUTE];
6307
6308 bool emit_instrlen_workaround =
6309 shader->variant->instrlen >
6310 cmd->device->physical_device->info->a6xx.instr_cache_size;
6311
6312 /* We don't use draw states for dispatches, so the bound pipeline
6313 * could be overwritten by reg stomping in a renderpass or blit.
6314 */
6315 if (cmd->device->dbg_renderpass_stomp_cs) {
6316 tu_cs_emit_state_ib(&cmd->cs, shader->state);
6317 }
6318
6319 /* There appears to be a HW bug where in some rare circumstances it appears
6320 * to accidentally use the FS instrlen instead of the CS instrlen, which
6321 * affects all known gens. Based on various experiments it appears that the
6322 * issue is that when prefetching a branch destination and there is a cache
6323 * miss, when fetching from memory the HW bounds-checks the fetch against
6324 * SP_CS_INSTRLEN, except when one of the two register contexts is active
6325 * it accidentally fetches SP_FS_INSTRLEN from the other (inactive)
6326 * context. To workaround it we set the FS instrlen here and do a dummy
6327 * event to roll the context (because it fetches SP_FS_INSTRLEN from the
6328 * "wrong" context). Because the bug seems to involve cache misses, we
6329 * don't emit this if the entire CS program fits in cache, which will
6330 * hopefully be the majority of cases.
6331 *
6332 * See https://gitlab.freedesktop.org/mesa/mesa/-/issues/5892
6333 */
6334 if (emit_instrlen_workaround) {
6335 tu_cs_emit_regs(cs, A6XX_SP_FS_INSTRLEN(shader->variant->instrlen));
6336 tu_emit_event_write<CHIP>(cmd, cs, FD_LABEL);
6337 }
6338
6339 /* TODO: We could probably flush less if we add a compute_flush_bits
6340 * bitfield.
6341 */
6342 tu_emit_cache_flush<CHIP>(cmd);
6343
6344 /* note: no reason to have this in a separate IB */
6345 tu_cs_emit_state_ib(cs, tu_emit_consts(cmd, true));
6346
6347 tu_emit_compute_driver_params<CHIP>(cmd, cs, info);
6348
6349 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESC_SETS) {
6350 tu6_emit_descriptor_sets<CHIP>(cmd, VK_PIPELINE_BIND_POINT_COMPUTE);
6351 tu_cs_emit_state_ib(cs, cmd->state.compute_load_state);
6352 }
6353
6354 cmd->state.dirty &= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS;
6355
6356 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
6357 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
6358
6359 const uint16_t *local_size = shader->variant->local_size;
6360 const uint32_t *num_groups = info->blocks;
6361 tu_cs_emit_regs(cs,
6362 HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 3,
6363 .localsizex = local_size[0] - 1,
6364 .localsizey = local_size[1] - 1,
6365 .localsizez = local_size[2] - 1),
6366 HLSQ_CS_NDRANGE_1(CHIP, .globalsize_x = local_size[0] * num_groups[0]),
6367 HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
6368 HLSQ_CS_NDRANGE_3(CHIP, .globalsize_y = local_size[1] * num_groups[1]),
6369 HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
6370 HLSQ_CS_NDRANGE_5(CHIP, .globalsize_z = local_size[2] * num_groups[2]),
6371 HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
6372
6373 tu_cs_emit_regs(cs,
6374 HLSQ_CS_KERNEL_GROUP_X(CHIP, 1),
6375 HLSQ_CS_KERNEL_GROUP_Y(CHIP, 1),
6376 HLSQ_CS_KERNEL_GROUP_Z(CHIP, 1));
6377
6378 if (info->indirect) {
6379 uint64_t iova = info->indirect->iova + info->indirect_offset;
6380
6381 trace_start_compute_indirect(&cmd->trace, cs);
6382
6383 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
6384 tu_cs_emit(cs, 0x00000000);
6385 tu_cs_emit_qw(cs, iova);
6386 tu_cs_emit(cs,
6387 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
6388 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
6389 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
6390
6391 trace_end_compute_indirect(&cmd->trace, cs,
6392 (struct u_trace_address) {
6393 .bo = info->indirect->bo,
6394 .offset = info->indirect_offset,
6395 });
6396 } else {
6397 trace_start_compute(&cmd->trace, cs, info->indirect != NULL,
6398 local_size[0], local_size[1], local_size[2],
6399 info->blocks[0], info->blocks[1], info->blocks[2]);
6400
6401 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
6402 tu_cs_emit(cs, 0x00000000);
6403 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
6404 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
6405 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
6406
6407 trace_end_compute(&cmd->trace, cs);
6408 }
6409
6410 /* For the workaround above, because it's using the "wrong" context for
6411 * SP_FS_INSTRLEN we should emit another dummy event write to avoid a
6412 * potential race between writing the register and the CP_EXEC_CS we just
6413 * did. We don't need to reset the register because it will be re-emitted
6414 * anyway when the next renderpass starts.
6415 */
6416 if (emit_instrlen_workaround) {
6417 tu_emit_event_write<CHIP>(cmd, cs, FD_LABEL);
6418 }
6419 }
6420
6421 template <chip CHIP>
6422 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatchBase(VkCommandBuffer commandBuffer,uint32_t base_x,uint32_t base_y,uint32_t base_z,uint32_t x,uint32_t y,uint32_t z)6423 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
6424 uint32_t base_x,
6425 uint32_t base_y,
6426 uint32_t base_z,
6427 uint32_t x,
6428 uint32_t y,
6429 uint32_t z)
6430 {
6431 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
6432 struct tu_dispatch_info info = {};
6433
6434 info.blocks[0] = x;
6435 info.blocks[1] = y;
6436 info.blocks[2] = z;
6437
6438 info.offsets[0] = base_x;
6439 info.offsets[1] = base_y;
6440 info.offsets[2] = base_z;
6441 tu_dispatch<CHIP>(cmd_buffer, &info);
6442 }
6443 TU_GENX(tu_CmdDispatchBase);
6444
6445 template <chip CHIP>
6446 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset)6447 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
6448 VkBuffer _buffer,
6449 VkDeviceSize offset)
6450 {
6451 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
6452 VK_FROM_HANDLE(tu_buffer, buffer, _buffer);
6453 struct tu_dispatch_info info = {};
6454
6455 info.indirect = buffer;
6456 info.indirect_offset = offset;
6457
6458 tu_dispatch<CHIP>(cmd_buffer, &info);
6459 }
6460 TU_GENX(tu_CmdDispatchIndirect);
6461
6462 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,const VkSubpassEndInfo * pSubpassEndInfo)6463 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
6464 const VkSubpassEndInfo *pSubpassEndInfo)
6465 {
6466 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
6467
6468 if (TU_DEBUG(DYNAMIC)) {
6469 vk_common_CmdEndRenderPass2(commandBuffer, pSubpassEndInfo);
6470 return;
6471 }
6472
6473 tu_cs_end(&cmd_buffer->draw_cs);
6474 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
6475 TU_CALLX(cmd_buffer->device, tu_cmd_render)(cmd_buffer);
6476
6477 cmd_buffer->state.cache.pending_flush_bits |=
6478 cmd_buffer->state.renderpass_cache.pending_flush_bits;
6479 tu_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier, true);
6480
6481 vk_free(&cmd_buffer->vk.pool->alloc, cmd_buffer->state.attachments);
6482
6483 tu_reset_render_pass(cmd_buffer);
6484 }
6485
6486 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndRendering(VkCommandBuffer commandBuffer)6487 tu_CmdEndRendering(VkCommandBuffer commandBuffer)
6488 {
6489 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
6490
6491 if (cmd_buffer->state.suspending)
6492 cmd_buffer->state.suspended_pass.lrz = cmd_buffer->state.lrz;
6493
6494 if (!cmd_buffer->state.suspending) {
6495 tu_cs_end(&cmd_buffer->draw_cs);
6496 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
6497
6498 if (cmd_buffer->state.suspend_resume == SR_IN_PRE_CHAIN) {
6499 cmd_buffer->trace_renderpass_end = u_trace_end_iterator(&cmd_buffer->trace);
6500 tu_save_pre_chain(cmd_buffer);
6501
6502 /* Even we don't call tu_cmd_render here, renderpass is finished
6503 * and draw states should be disabled.
6504 */
6505 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs);
6506 } else {
6507 TU_CALLX(cmd_buffer->device, tu_cmd_render)(cmd_buffer);
6508 }
6509
6510 tu_reset_render_pass(cmd_buffer);
6511 }
6512
6513 if (cmd_buffer->state.resuming && !cmd_buffer->state.suspending) {
6514 /* exiting suspend/resume chain */
6515 switch (cmd_buffer->state.suspend_resume) {
6516 case SR_IN_CHAIN:
6517 cmd_buffer->state.suspend_resume = SR_NONE;
6518 break;
6519 case SR_IN_PRE_CHAIN:
6520 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
6521 cmd_buffer->state.suspend_resume = SR_AFTER_PRE_CHAIN;
6522 break;
6523 default:
6524 unreachable("suspending render pass not followed by resuming pass");
6525 }
6526 }
6527 }
6528
6529 void
tu_barrier(struct tu_cmd_buffer * cmd,uint32_t dep_count,const VkDependencyInfo * dep_infos)6530 tu_barrier(struct tu_cmd_buffer *cmd,
6531 uint32_t dep_count,
6532 const VkDependencyInfo *dep_infos)
6533 {
6534 VkPipelineStageFlags2 srcStage = 0;
6535 VkPipelineStageFlags2 dstStage = 0;
6536 BITMASK_ENUM(tu_cmd_access_mask) src_flags = 0;
6537 BITMASK_ENUM(tu_cmd_access_mask) dst_flags = 0;
6538
6539 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
6540 * so we have to use the sysmem flushes.
6541 */
6542 bool gmem = cmd->state.ccu_state == TU_CMD_CCU_GMEM &&
6543 !cmd->state.pass;
6544
6545 for (uint32_t dep_idx = 0; dep_idx < dep_count; dep_idx++) {
6546 const VkDependencyInfo *dep_info = &dep_infos[dep_idx];
6547
6548 for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
6549 VkPipelineStageFlags2 sanitized_src_stage =
6550 sanitize_src_stage(dep_info->pMemoryBarriers[i].srcStageMask);
6551 VkPipelineStageFlags2 sanitized_dst_stage =
6552 sanitize_dst_stage(dep_info->pMemoryBarriers[i].dstStageMask);
6553 src_flags |= vk2tu_access(dep_info->pMemoryBarriers[i].srcAccessMask,
6554 sanitized_src_stage, false, gmem);
6555 dst_flags |= vk2tu_access(dep_info->pMemoryBarriers[i].dstAccessMask,
6556 sanitized_dst_stage, false, gmem);
6557 srcStage |= sanitized_src_stage;
6558 dstStage |= sanitized_dst_stage;
6559 }
6560
6561 for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
6562 VkPipelineStageFlags2 sanitized_src_stage =
6563 sanitize_src_stage(dep_info->pBufferMemoryBarriers[i].srcStageMask);
6564 VkPipelineStageFlags2 sanitized_dst_stage =
6565 sanitize_dst_stage(dep_info->pBufferMemoryBarriers[i].dstStageMask);
6566 src_flags |= vk2tu_access(dep_info->pBufferMemoryBarriers[i].srcAccessMask,
6567 sanitized_src_stage, false, gmem);
6568 dst_flags |= vk2tu_access(dep_info->pBufferMemoryBarriers[i].dstAccessMask,
6569 sanitized_dst_stage, false, gmem);
6570 srcStage |= sanitized_src_stage;
6571 dstStage |= sanitized_dst_stage;
6572 }
6573
6574 for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
6575 VkImageLayout old_layout = dep_info->pImageMemoryBarriers[i].oldLayout;
6576 if (old_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
6577 /* The underlying memory for this image may have been used earlier
6578 * within the same queue submission for a different image, which
6579 * means that there may be old, stale cache entries which are in the
6580 * "wrong" location, which could cause problems later after writing
6581 * to the image. We don't want these entries being flushed later and
6582 * overwriting the actual image, so we need to flush the CCU.
6583 */
6584 VK_FROM_HANDLE(tu_image, image, dep_info->pImageMemoryBarriers[i].image);
6585
6586 if (vk_format_is_depth_or_stencil(image->vk.format)) {
6587 src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
6588 } else {
6589 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
6590 }
6591 }
6592 VkPipelineStageFlags2 sanitized_src_stage =
6593 sanitize_src_stage(dep_info->pImageMemoryBarriers[i].srcStageMask);
6594 VkPipelineStageFlags2 sanitized_dst_stage =
6595 sanitize_dst_stage(dep_info->pImageMemoryBarriers[i].dstStageMask);
6596 src_flags |= vk2tu_access(dep_info->pImageMemoryBarriers[i].srcAccessMask,
6597 sanitized_src_stage, true, gmem);
6598 dst_flags |= vk2tu_access(dep_info->pImageMemoryBarriers[i].dstAccessMask,
6599 sanitized_dst_stage, true, gmem);
6600 srcStage |= sanitized_src_stage;
6601 dstStage |= sanitized_dst_stage;
6602 }
6603 }
6604
6605 if (cmd->state.pass) {
6606 const VkPipelineStageFlags framebuffer_space_stages =
6607 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
6608 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
6609 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
6610 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
6611
6612 /* We cannot have non-by-region "fb-space to fb-space" barriers.
6613 *
6614 * From the Vulkan 1.2.185 spec, section 7.6.1 "Subpass Self-dependency":
6615 *
6616 * If the source and destination stage masks both include
6617 * framebuffer-space stages, then dependencyFlags must include
6618 * VK_DEPENDENCY_BY_REGION_BIT.
6619 * [...]
6620 * Each of the synchronization scopes and access scopes of a
6621 * vkCmdPipelineBarrier2 or vkCmdPipelineBarrier command inside
6622 * a render pass instance must be a subset of the scopes of one of
6623 * the self-dependencies for the current subpass.
6624 *
6625 * If the self-dependency has VK_DEPENDENCY_BY_REGION_BIT or
6626 * VK_DEPENDENCY_VIEW_LOCAL_BIT set, then so must the pipeline barrier.
6627 *
6628 * By-region barriers are ok for gmem. All other barriers would involve
6629 * vtx stages which are NOT ok for gmem rendering.
6630 * See dep_invalid_for_gmem().
6631 */
6632 if ((srcStage & ~framebuffer_space_stages) ||
6633 (dstStage & ~framebuffer_space_stages)) {
6634 cmd->state.rp.disable_gmem = true;
6635 }
6636 }
6637
6638 struct tu_cache_state *cache =
6639 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
6640
6641 /* a750 has a HW bug where writing a UBWC compressed image with a compute
6642 * shader followed by reading it as a texture (or readonly image) requires
6643 * a CACHE_CLEAN event. Some notes about this bug:
6644 * - It only happens after a blit happens.
6645 * - It's fast-clear related, it happens when the image is fast cleared
6646 * before the write and the value read is (incorrectly) the fast clear
6647 * color.
6648 * - CACHE_FLUSH is supposed to be the same as CACHE_CLEAN +
6649 * CACHE_INVALIDATE, but it doesn't work whereas CACHE_CLEAN +
6650 * CACHE_INVALIDATE does.
6651 *
6652 * The srcAccess can be replaced by a OpMemoryBarrier(MakeAvailable), so
6653 * we can't use that to insert the flush. Instead we use the shader source
6654 * stage.
6655 */
6656 if (cmd->device->physical_device->info->a7xx.ubwc_coherency_quirk &&
6657 (srcStage &
6658 (VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT |
6659 VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT |
6660 VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT |
6661 VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT |
6662 VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT |
6663 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT |
6664 VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT |
6665 VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT))) {
6666 cache->flush_bits |= TU_CMD_FLAG_CACHE_CLEAN;
6667 cache->pending_flush_bits &= ~TU_CMD_FLAG_CACHE_CLEAN;
6668 }
6669
6670 tu_flush_for_access(cache, src_flags, dst_flags);
6671
6672 enum tu_stage src_stage = vk2tu_src_stage(srcStage);
6673 enum tu_stage dst_stage = vk2tu_dst_stage(dstStage);
6674 tu_flush_for_stage(cache, src_stage, dst_stage);
6675 }
6676
6677 VKAPI_ATTR void VKAPI_CALL
tu_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,const VkDependencyInfo * pDependencyInfo)6678 tu_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,
6679 const VkDependencyInfo *pDependencyInfo)
6680 {
6681 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
6682
6683 tu_barrier(cmd_buffer, 1, pDependencyInfo);
6684 }
6685
6686 template <chip CHIP>
6687 void
tu_write_event(struct tu_cmd_buffer * cmd,struct tu_event * event,VkPipelineStageFlags2 stageMask,unsigned value)6688 tu_write_event(struct tu_cmd_buffer *cmd, struct tu_event *event,
6689 VkPipelineStageFlags2 stageMask, unsigned value)
6690 {
6691 struct tu_cs *cs = &cmd->cs;
6692
6693 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
6694 assert(!cmd->state.pass);
6695
6696 tu_emit_cache_flush<CHIP>(cmd);
6697
6698 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
6699 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
6700 */
6701 VkPipelineStageFlags2 top_of_pipe_flags =
6702 VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT |
6703 VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT;
6704
6705 if (!(stageMask & ~top_of_pipe_flags)) {
6706 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
6707 tu_cs_emit_qw(cs, event->bo->iova); /* ADDR_LO/HI */
6708 tu_cs_emit(cs, value);
6709 } else {
6710 /* Use a RB_DONE_TS event to wait for everything to complete. */
6711 if (CHIP == A6XX) {
6712 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
6713 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
6714 } else {
6715 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, 4);
6716 tu_cs_emit(cs, CP_EVENT_WRITE7_0(.event = RB_DONE_TS,
6717 .write_src = EV_WRITE_USER_32B,
6718 .write_dst = EV_DST_RAM,
6719 .write_enabled = true).value);
6720 }
6721
6722 tu_cs_emit_qw(cs, event->bo->iova);
6723 tu_cs_emit(cs, value);
6724 }
6725 }
6726 TU_GENX(tu_write_event);
6727
6728 template <chip CHIP>
6729 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,const VkConditionalRenderingBeginInfoEXT * pConditionalRenderingBegin)6730 tu_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,
6731 const VkConditionalRenderingBeginInfoEXT *pConditionalRenderingBegin)
6732 {
6733 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6734
6735 cmd->state.predication_active = true;
6736
6737 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
6738
6739 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
6740 tu_cs_emit(cs, 1);
6741
6742 /* Wait for any writes to the predicate to land */
6743 if (cmd->state.pass)
6744 tu_emit_cache_flush_renderpass<CHIP>(cmd);
6745 else
6746 tu_emit_cache_flush<CHIP>(cmd);
6747
6748 VK_FROM_HANDLE(tu_buffer, buf, pConditionalRenderingBegin->buffer);
6749 uint64_t iova = buf->iova + pConditionalRenderingBegin->offset;
6750
6751 /* qcom doesn't support 32-bit reference values, only 64-bit, but Vulkan
6752 * mandates 32-bit comparisons. Our workaround is to copy the the reference
6753 * value to the low 32-bits of a location where the high 32 bits are known
6754 * to be 0 and then compare that.
6755 */
6756 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
6757 tu_cs_emit(cs, 0);
6758 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
6759 tu_cs_emit_qw(cs, iova);
6760
6761 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
6762 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
6763
6764 bool inv = pConditionalRenderingBegin->flags & VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT;
6765 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_SET, 3);
6766 tu_cs_emit(cs, CP_DRAW_PRED_SET_0_SRC(PRED_SRC_MEM) |
6767 CP_DRAW_PRED_SET_0_TEST(inv ? EQ_0_PASS : NE_0_PASS));
6768 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
6769 }
6770 TU_GENX(tu_CmdBeginConditionalRenderingEXT);
6771
6772 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)6773 tu_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)
6774 {
6775 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6776
6777 cmd->state.predication_active = false;
6778
6779 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
6780
6781 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
6782 tu_cs_emit(cs, 0);
6783 }
6784
6785 template <chip CHIP>
6786 void
tu_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer,VkPipelineStageFlagBits2 pipelineStage,VkBuffer dstBuffer,VkDeviceSize dstOffset,uint32_t marker)6787 tu_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer,
6788 VkPipelineStageFlagBits2 pipelineStage,
6789 VkBuffer dstBuffer,
6790 VkDeviceSize dstOffset,
6791 uint32_t marker)
6792 {
6793 /* Almost the same as tu_write_event, but also allowed in renderpass */
6794 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6795 VK_FROM_HANDLE(tu_buffer, buffer, dstBuffer);
6796
6797 uint64_t va = buffer->iova + dstOffset;
6798
6799 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
6800 struct tu_cache_state *cache =
6801 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
6802
6803 /* From the Vulkan 1.2.203 spec:
6804 *
6805 * The access scope for buffer marker writes falls under
6806 * the VK_ACCESS_TRANSFER_WRITE_BIT, and the pipeline stages for
6807 * identifying the synchronization scope must include both pipelineStage
6808 * and VK_PIPELINE_STAGE_TRANSFER_BIT.
6809 *
6810 * Transfer operations use CCU however here we write via CP.
6811 * Flush CCU in order to make the results of previous transfer
6812 * operation visible to CP.
6813 */
6814 tu_flush_for_access(cache, TU_ACCESS_NONE, TU_ACCESS_SYSMEM_WRITE);
6815
6816 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
6817 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
6818 */
6819 VkPipelineStageFlags2 top_of_pipe_flags =
6820 VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT |
6821 VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT;
6822
6823 bool is_top_of_pipe = !(pipelineStage & ~top_of_pipe_flags);
6824
6825 /* We have to WFI only if we flushed CCU here and are using CP_MEM_WRITE.
6826 * Otherwise:
6827 * - We do CP_EVENT_WRITE(RB_DONE_TS) which should wait for flushes;
6828 * - There was a barrier to synchronize other writes with WriteBufferMarkerAMD
6829 * and they had to include our pipelineStage which forces the WFI.
6830 */
6831 if (cache->flush_bits && is_top_of_pipe) {
6832 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
6833 }
6834
6835 if (cmd->state.pass) {
6836 tu_emit_cache_flush_renderpass<CHIP>(cmd);
6837 } else {
6838 tu_emit_cache_flush<CHIP>(cmd);
6839 }
6840
6841 if (is_top_of_pipe) {
6842 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
6843 tu_cs_emit_qw(cs, va); /* ADDR_LO/HI */
6844 tu_cs_emit(cs, marker);
6845 } else {
6846 /* Use a RB_DONE_TS event to wait for everything to complete. */
6847 if (CHIP == A6XX) {
6848 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
6849 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
6850 } else {
6851 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, 4);
6852 tu_cs_emit(cs, CP_EVENT_WRITE7_0(.event = RB_DONE_TS,
6853 .write_src = EV_WRITE_USER_32B,
6854 .write_dst = EV_DST_RAM,
6855 .write_enabled = true).value);
6856 }
6857 tu_cs_emit_qw(cs, va);
6858 tu_cs_emit(cs, marker);
6859 }
6860
6861 /* Make sure the result of this write is visible to others. */
6862 tu_flush_for_access(cache, TU_ACCESS_CP_WRITE, TU_ACCESS_NONE);
6863 }
6864 TU_GENX(tu_CmdWriteBufferMarker2AMD);
6865