1 #ifndef __BDK_CSRS_UAA_H__
2 #define __BDK_CSRS_UAA_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium UAA.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration uaa_bar_e
57 *
58 * UART Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN9(a) (0x87e028000000ll + 0x1000000ll * (a))
62 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN9_SIZE 0x10000ull
63 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN81XX(a) (0x87e028000000ll + 0x1000000ll * (a))
64 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN81XX_SIZE 0x100000ull
65 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN88XX(a) (0x87e024000000ll + 0x1000000ll * (a))
66 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN88XX_SIZE 0x100000ull
67 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN83XX(a) (0x87e028000000ll + 0x1000000ll * (a))
68 #define BDK_UAA_BAR_E_UAAX_PF_BAR0_CN83XX_SIZE 0x100000ull
69 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN9(a) (0x87e028f00000ll + 0x1000000ll * (a))
70 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN9_SIZE 0x100000ull
71 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN81XX(a) (0x87e028f00000ll + 0x1000000ll * (a))
72 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN81XX_SIZE 0x100000ull
73 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN88XX(a) (0x87e024f00000ll + 0x1000000ll * (a))
74 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN88XX_SIZE 0x100000ull
75 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN83XX(a) (0x87e028f00000ll + 0x1000000ll * (a))
76 #define BDK_UAA_BAR_E_UAAX_PF_BAR4_CN83XX_SIZE 0x100000ull
77
78 /**
79 * Enumeration uaa_int_vec_e
80 *
81 * UART MSI-X Vector Enumeration
82 * Enumerates the MSI-X interrupt vectors.
83 */
84 #define BDK_UAA_INT_VEC_E_INTS (0)
85 #define BDK_UAA_INT_VEC_E_INTS_CLEAR (1)
86
87 /**
88 * Register (RSL32b) uaa#_cidr0
89 *
90 * UART Component Identification Register 0
91 */
92 union bdk_uaax_cidr0
93 {
94 uint32_t u;
95 struct bdk_uaax_cidr0_s
96 {
97 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
98 uint32_t reserved_8_31 : 24;
99 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
100 #else /* Word 0 - Little Endian */
101 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
102 uint32_t reserved_8_31 : 24;
103 #endif /* Word 0 - End */
104 } s;
105 /* struct bdk_uaax_cidr0_s cn; */
106 };
107 typedef union bdk_uaax_cidr0 bdk_uaax_cidr0_t;
108
109 static inline uint64_t BDK_UAAX_CIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_CIDR0(unsigned long a)110 static inline uint64_t BDK_UAAX_CIDR0(unsigned long a)
111 {
112 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
113 return 0x87e028000ff0ll + 0x1000000ll * ((a) & 0x3);
114 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
115 return 0x87e028000ff0ll + 0x1000000ll * ((a) & 0x3);
116 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
117 return 0x87e024000ff0ll + 0x1000000ll * ((a) & 0x1);
118 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
119 return 0x87e028000ff0ll + 0x1000000ll * ((a) & 0x7);
120 __bdk_csr_fatal("UAAX_CIDR0", 1, a, 0, 0, 0);
121 }
122
123 #define typedef_BDK_UAAX_CIDR0(a) bdk_uaax_cidr0_t
124 #define bustype_BDK_UAAX_CIDR0(a) BDK_CSR_TYPE_RSL32b
125 #define basename_BDK_UAAX_CIDR0(a) "UAAX_CIDR0"
126 #define device_bar_BDK_UAAX_CIDR0(a) 0x0 /* PF_BAR0 */
127 #define busnum_BDK_UAAX_CIDR0(a) (a)
128 #define arguments_BDK_UAAX_CIDR0(a) (a),-1,-1,-1
129
130 /**
131 * Register (RSL32b) uaa#_cidr1
132 *
133 * UART Component Identification Register 1
134 */
135 union bdk_uaax_cidr1
136 {
137 uint32_t u;
138 struct bdk_uaax_cidr1_s
139 {
140 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
141 uint32_t reserved_8_31 : 24;
142 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
143 #else /* Word 0 - Little Endian */
144 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
145 uint32_t reserved_8_31 : 24;
146 #endif /* Word 0 - End */
147 } s;
148 /* struct bdk_uaax_cidr1_s cn; */
149 };
150 typedef union bdk_uaax_cidr1 bdk_uaax_cidr1_t;
151
152 static inline uint64_t BDK_UAAX_CIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_CIDR1(unsigned long a)153 static inline uint64_t BDK_UAAX_CIDR1(unsigned long a)
154 {
155 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
156 return 0x87e028000ff4ll + 0x1000000ll * ((a) & 0x3);
157 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
158 return 0x87e028000ff4ll + 0x1000000ll * ((a) & 0x3);
159 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
160 return 0x87e024000ff4ll + 0x1000000ll * ((a) & 0x1);
161 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
162 return 0x87e028000ff4ll + 0x1000000ll * ((a) & 0x7);
163 __bdk_csr_fatal("UAAX_CIDR1", 1, a, 0, 0, 0);
164 }
165
166 #define typedef_BDK_UAAX_CIDR1(a) bdk_uaax_cidr1_t
167 #define bustype_BDK_UAAX_CIDR1(a) BDK_CSR_TYPE_RSL32b
168 #define basename_BDK_UAAX_CIDR1(a) "UAAX_CIDR1"
169 #define device_bar_BDK_UAAX_CIDR1(a) 0x0 /* PF_BAR0 */
170 #define busnum_BDK_UAAX_CIDR1(a) (a)
171 #define arguments_BDK_UAAX_CIDR1(a) (a),-1,-1,-1
172
173 /**
174 * Register (RSL32b) uaa#_cidr2
175 *
176 * UART Component Identification Register 2
177 */
178 union bdk_uaax_cidr2
179 {
180 uint32_t u;
181 struct bdk_uaax_cidr2_s
182 {
183 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
184 uint32_t reserved_8_31 : 24;
185 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
186 #else /* Word 0 - Little Endian */
187 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
188 uint32_t reserved_8_31 : 24;
189 #endif /* Word 0 - End */
190 } s;
191 /* struct bdk_uaax_cidr2_s cn; */
192 };
193 typedef union bdk_uaax_cidr2 bdk_uaax_cidr2_t;
194
195 static inline uint64_t BDK_UAAX_CIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_CIDR2(unsigned long a)196 static inline uint64_t BDK_UAAX_CIDR2(unsigned long a)
197 {
198 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
199 return 0x87e028000ff8ll + 0x1000000ll * ((a) & 0x3);
200 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
201 return 0x87e028000ff8ll + 0x1000000ll * ((a) & 0x3);
202 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
203 return 0x87e024000ff8ll + 0x1000000ll * ((a) & 0x1);
204 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
205 return 0x87e028000ff8ll + 0x1000000ll * ((a) & 0x7);
206 __bdk_csr_fatal("UAAX_CIDR2", 1, a, 0, 0, 0);
207 }
208
209 #define typedef_BDK_UAAX_CIDR2(a) bdk_uaax_cidr2_t
210 #define bustype_BDK_UAAX_CIDR2(a) BDK_CSR_TYPE_RSL32b
211 #define basename_BDK_UAAX_CIDR2(a) "UAAX_CIDR2"
212 #define device_bar_BDK_UAAX_CIDR2(a) 0x0 /* PF_BAR0 */
213 #define busnum_BDK_UAAX_CIDR2(a) (a)
214 #define arguments_BDK_UAAX_CIDR2(a) (a),-1,-1,-1
215
216 /**
217 * Register (RSL32b) uaa#_cidr3
218 *
219 * UART Component Identification Register 3
220 */
221 union bdk_uaax_cidr3
222 {
223 uint32_t u;
224 struct bdk_uaax_cidr3_s
225 {
226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
227 uint32_t reserved_8_31 : 24;
228 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
229 #else /* Word 0 - Little Endian */
230 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
231 uint32_t reserved_8_31 : 24;
232 #endif /* Word 0 - End */
233 } s;
234 /* struct bdk_uaax_cidr3_s cn; */
235 };
236 typedef union bdk_uaax_cidr3 bdk_uaax_cidr3_t;
237
238 static inline uint64_t BDK_UAAX_CIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_CIDR3(unsigned long a)239 static inline uint64_t BDK_UAAX_CIDR3(unsigned long a)
240 {
241 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
242 return 0x87e028000ffcll + 0x1000000ll * ((a) & 0x3);
243 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
244 return 0x87e028000ffcll + 0x1000000ll * ((a) & 0x3);
245 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
246 return 0x87e024000ffcll + 0x1000000ll * ((a) & 0x1);
247 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
248 return 0x87e028000ffcll + 0x1000000ll * ((a) & 0x7);
249 __bdk_csr_fatal("UAAX_CIDR3", 1, a, 0, 0, 0);
250 }
251
252 #define typedef_BDK_UAAX_CIDR3(a) bdk_uaax_cidr3_t
253 #define bustype_BDK_UAAX_CIDR3(a) BDK_CSR_TYPE_RSL32b
254 #define basename_BDK_UAAX_CIDR3(a) "UAAX_CIDR3"
255 #define device_bar_BDK_UAAX_CIDR3(a) 0x0 /* PF_BAR0 */
256 #define busnum_BDK_UAAX_CIDR3(a) (a)
257 #define arguments_BDK_UAAX_CIDR3(a) (a),-1,-1,-1
258
259 /**
260 * Register (RSL32b) uaa#_cr
261 *
262 * UART Control Register
263 */
264 union bdk_uaax_cr
265 {
266 uint32_t u;
267 struct bdk_uaax_cr_s
268 {
269 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
270 uint32_t reserved_16_31 : 16;
271 uint32_t ctsen : 1; /**< [ 15: 15](R/W) "CTS hardware flow control enable. If set, data is only transmitted when UART#_CTS_L is
272 asserted (low)." */
273 uint32_t rtsen : 1; /**< [ 14: 14](R/W) RTS hardware flow control enable. If set, data is only requested when space in the receive FIFO. */
274 uint32_t out2 : 1; /**< [ 13: 13](R/W) Unused. */
275 uint32_t out1 : 1; /**< [ 12: 12](R/W) Data carrier detect. If set, drive UART#_DCD_L asserted (low). */
276 uint32_t rts : 1; /**< [ 11: 11](R/W) Request to send. If set, assert UART#_RTS_L. */
277 uint32_t dtr : 1; /**< [ 10: 10](R/W) Data terminal ready. If set, assert UART#_DTR_N. */
278 uint32_t rxe : 1; /**< [ 9: 9](R/W) Receive enable. If set, receive section is enabled. */
279 uint32_t txe : 1; /**< [ 8: 8](R/W) Transmit enable. */
280 uint32_t lbe : 1; /**< [ 7: 7](R/W) "Loopback enable. If set, the serial output is looped into the serial input as if
281 UART#_SIN
282 was physically attached to UART#_SOUT." */
283 uint32_t reserved_1_6 : 6;
284 uint32_t uarten : 1; /**< [ 0: 0](R/W) UART enable.
285 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception,
286 it completes the current character.
287 1 = UART enabled. */
288 #else /* Word 0 - Little Endian */
289 uint32_t uarten : 1; /**< [ 0: 0](R/W) UART enable.
290 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception,
291 it completes the current character.
292 1 = UART enabled. */
293 uint32_t reserved_1_6 : 6;
294 uint32_t lbe : 1; /**< [ 7: 7](R/W) "Loopback enable. If set, the serial output is looped into the serial input as if
295 UART#_SIN
296 was physically attached to UART#_SOUT." */
297 uint32_t txe : 1; /**< [ 8: 8](R/W) Transmit enable. */
298 uint32_t rxe : 1; /**< [ 9: 9](R/W) Receive enable. If set, receive section is enabled. */
299 uint32_t dtr : 1; /**< [ 10: 10](R/W) Data terminal ready. If set, assert UART#_DTR_N. */
300 uint32_t rts : 1; /**< [ 11: 11](R/W) Request to send. If set, assert UART#_RTS_L. */
301 uint32_t out1 : 1; /**< [ 12: 12](R/W) Data carrier detect. If set, drive UART#_DCD_L asserted (low). */
302 uint32_t out2 : 1; /**< [ 13: 13](R/W) Unused. */
303 uint32_t rtsen : 1; /**< [ 14: 14](R/W) RTS hardware flow control enable. If set, data is only requested when space in the receive FIFO. */
304 uint32_t ctsen : 1; /**< [ 15: 15](R/W) "CTS hardware flow control enable. If set, data is only transmitted when UART#_CTS_L is
305 asserted (low)." */
306 uint32_t reserved_16_31 : 16;
307 #endif /* Word 0 - End */
308 } s;
309 struct bdk_uaax_cr_cn
310 {
311 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
312 uint32_t reserved_16_31 : 16;
313 uint32_t ctsen : 1; /**< [ 15: 15](R/W) "CTS hardware flow control enable. If set, data is only transmitted when UART#_CTS_L is
314 asserted (low)." */
315 uint32_t rtsen : 1; /**< [ 14: 14](R/W) RTS hardware flow control enable. If set, data is only requested when space in the receive FIFO. */
316 uint32_t out2 : 1; /**< [ 13: 13](R/W) Unused. */
317 uint32_t out1 : 1; /**< [ 12: 12](R/W) Data carrier detect. If set, drive UART#_DCD_L asserted (low). */
318 uint32_t rts : 1; /**< [ 11: 11](R/W) Request to send. If set, assert UART#_RTS_L. */
319 uint32_t dtr : 1; /**< [ 10: 10](R/W) Data terminal ready. If set, assert UART#_DTR_N. */
320 uint32_t rxe : 1; /**< [ 9: 9](R/W) Receive enable. If set, receive section is enabled. */
321 uint32_t txe : 1; /**< [ 8: 8](R/W) Transmit enable. */
322 uint32_t lbe : 1; /**< [ 7: 7](R/W) "Loopback enable. If set, the serial output is looped into the serial input as if
323 UART#_SIN
324 was physically attached to UART#_SOUT." */
325 uint32_t reserved_3_6 : 4;
326 uint32_t reserved_2 : 1;
327 uint32_t reserved_1 : 1;
328 uint32_t uarten : 1; /**< [ 0: 0](R/W) UART enable.
329 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception,
330 it completes the current character.
331 1 = UART enabled. */
332 #else /* Word 0 - Little Endian */
333 uint32_t uarten : 1; /**< [ 0: 0](R/W) UART enable.
334 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception,
335 it completes the current character.
336 1 = UART enabled. */
337 uint32_t reserved_1 : 1;
338 uint32_t reserved_2 : 1;
339 uint32_t reserved_3_6 : 4;
340 uint32_t lbe : 1; /**< [ 7: 7](R/W) "Loopback enable. If set, the serial output is looped into the serial input as if
341 UART#_SIN
342 was physically attached to UART#_SOUT." */
343 uint32_t txe : 1; /**< [ 8: 8](R/W) Transmit enable. */
344 uint32_t rxe : 1; /**< [ 9: 9](R/W) Receive enable. If set, receive section is enabled. */
345 uint32_t dtr : 1; /**< [ 10: 10](R/W) Data terminal ready. If set, assert UART#_DTR_N. */
346 uint32_t rts : 1; /**< [ 11: 11](R/W) Request to send. If set, assert UART#_RTS_L. */
347 uint32_t out1 : 1; /**< [ 12: 12](R/W) Data carrier detect. If set, drive UART#_DCD_L asserted (low). */
348 uint32_t out2 : 1; /**< [ 13: 13](R/W) Unused. */
349 uint32_t rtsen : 1; /**< [ 14: 14](R/W) RTS hardware flow control enable. If set, data is only requested when space in the receive FIFO. */
350 uint32_t ctsen : 1; /**< [ 15: 15](R/W) "CTS hardware flow control enable. If set, data is only transmitted when UART#_CTS_L is
351 asserted (low)." */
352 uint32_t reserved_16_31 : 16;
353 #endif /* Word 0 - End */
354 } cn;
355 };
356 typedef union bdk_uaax_cr bdk_uaax_cr_t;
357
358 static inline uint64_t BDK_UAAX_CR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_CR(unsigned long a)359 static inline uint64_t BDK_UAAX_CR(unsigned long a)
360 {
361 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
362 return 0x87e028000030ll + 0x1000000ll * ((a) & 0x3);
363 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
364 return 0x87e028000030ll + 0x1000000ll * ((a) & 0x3);
365 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
366 return 0x87e024000030ll + 0x1000000ll * ((a) & 0x1);
367 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
368 return 0x87e028000030ll + 0x1000000ll * ((a) & 0x7);
369 __bdk_csr_fatal("UAAX_CR", 1, a, 0, 0, 0);
370 }
371
372 #define typedef_BDK_UAAX_CR(a) bdk_uaax_cr_t
373 #define bustype_BDK_UAAX_CR(a) BDK_CSR_TYPE_RSL32b
374 #define basename_BDK_UAAX_CR(a) "UAAX_CR"
375 #define device_bar_BDK_UAAX_CR(a) 0x0 /* PF_BAR0 */
376 #define busnum_BDK_UAAX_CR(a) (a)
377 #define arguments_BDK_UAAX_CR(a) (a),-1,-1,-1
378
379 /**
380 * Register (RSL32b) uaa#_dr
381 *
382 * UART Data Register
383 * Writing to this register pushes data to the FIFO for transmission. Reading it retrieves
384 * received data from the receive FIFO.
385 */
386 union bdk_uaax_dr
387 {
388 uint32_t u;
389 struct bdk_uaax_dr_s
390 {
391 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
392 uint32_t reserved_12_31 : 20;
393 uint32_t oe : 1; /**< [ 11: 11](RO/H) Overrun error. Set if data is received and FIFO was full. Cleared once a new character is
394 written to the FIFO. */
395 uint32_t be : 1; /**< [ 10: 10](RO/H) Break error. Indicates received data input was held low for longer than a full-transmission time. */
396 uint32_t pe : 1; /**< [ 9: 9](RO/H) Parity error. Indicates the parity did not match that expected. */
397 uint32_t fe : 1; /**< [ 8: 8](RO/H) Framing error. Indicates that the received character did not have a stop bit. */
398 uint32_t data : 8; /**< [ 7: 0](R/W/H) On write operations, data to transmit. On read operations, received data. */
399 #else /* Word 0 - Little Endian */
400 uint32_t data : 8; /**< [ 7: 0](R/W/H) On write operations, data to transmit. On read operations, received data. */
401 uint32_t fe : 1; /**< [ 8: 8](RO/H) Framing error. Indicates that the received character did not have a stop bit. */
402 uint32_t pe : 1; /**< [ 9: 9](RO/H) Parity error. Indicates the parity did not match that expected. */
403 uint32_t be : 1; /**< [ 10: 10](RO/H) Break error. Indicates received data input was held low for longer than a full-transmission time. */
404 uint32_t oe : 1; /**< [ 11: 11](RO/H) Overrun error. Set if data is received and FIFO was full. Cleared once a new character is
405 written to the FIFO. */
406 uint32_t reserved_12_31 : 20;
407 #endif /* Word 0 - End */
408 } s;
409 /* struct bdk_uaax_dr_s cn; */
410 };
411 typedef union bdk_uaax_dr bdk_uaax_dr_t;
412
413 static inline uint64_t BDK_UAAX_DR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_DR(unsigned long a)414 static inline uint64_t BDK_UAAX_DR(unsigned long a)
415 {
416 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
417 return 0x87e028000000ll + 0x1000000ll * ((a) & 0x3);
418 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
419 return 0x87e028000000ll + 0x1000000ll * ((a) & 0x3);
420 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
421 return 0x87e024000000ll + 0x1000000ll * ((a) & 0x1);
422 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
423 return 0x87e028000000ll + 0x1000000ll * ((a) & 0x7);
424 __bdk_csr_fatal("UAAX_DR", 1, a, 0, 0, 0);
425 }
426
427 #define typedef_BDK_UAAX_DR(a) bdk_uaax_dr_t
428 #define bustype_BDK_UAAX_DR(a) BDK_CSR_TYPE_RSL32b
429 #define basename_BDK_UAAX_DR(a) "UAAX_DR"
430 #define device_bar_BDK_UAAX_DR(a) 0x0 /* PF_BAR0 */
431 #define busnum_BDK_UAAX_DR(a) (a)
432 #define arguments_BDK_UAAX_DR(a) (a),-1,-1,-1
433
434 /**
435 * Register (RSL32b) uaa#_fbrd
436 *
437 * UART Fractional Baud Rate Register
438 */
439 union bdk_uaax_fbrd
440 {
441 uint32_t u;
442 struct bdk_uaax_fbrd_s
443 {
444 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
445 uint32_t reserved_6_31 : 26;
446 uint32_t baud_divfrac : 6; /**< [ 5: 0](R/W) Fractional part of baud rate divisor. The output baud rate is equal to the HCLK frequency
447 divided by sixteen times the value of the baud-rate divisor, as follows:
448
449 _ baud rate = HCLK / (16 * divisor).
450
451 Where the HCLK frequency is controlled by UAA()_UCTL_CTL[H_CLKDIV_SEL].
452
453 Once both divisor-latch registers are set, at least eight HCLK
454 cycles should be allowed to pass before transmitting or receiving data. */
455 #else /* Word 0 - Little Endian */
456 uint32_t baud_divfrac : 6; /**< [ 5: 0](R/W) Fractional part of baud rate divisor. The output baud rate is equal to the HCLK frequency
457 divided by sixteen times the value of the baud-rate divisor, as follows:
458
459 _ baud rate = HCLK / (16 * divisor).
460
461 Where the HCLK frequency is controlled by UAA()_UCTL_CTL[H_CLKDIV_SEL].
462
463 Once both divisor-latch registers are set, at least eight HCLK
464 cycles should be allowed to pass before transmitting or receiving data. */
465 uint32_t reserved_6_31 : 26;
466 #endif /* Word 0 - End */
467 } s;
468 /* struct bdk_uaax_fbrd_s cn9; */
469 struct bdk_uaax_fbrd_cn81xx
470 {
471 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
472 uint32_t reserved_6_31 : 26;
473 uint32_t baud_divfrac : 6; /**< [ 5: 0](R/W) Fractional part of baud rate divisor. The output baud rate is equal to the coprocessor-
474 clock frequency divided by sixteen times the value of the baud-rate divisor, as follows:
475
476 _ baud rate = coprocessor-clock frequency / (16 * divisor).
477
478 Note that once both divisor-latch registers are set, at least eight coprocessor-clock
479 cycles should be allowed to pass before transmitting or receiving data. */
480 #else /* Word 0 - Little Endian */
481 uint32_t baud_divfrac : 6; /**< [ 5: 0](R/W) Fractional part of baud rate divisor. The output baud rate is equal to the coprocessor-
482 clock frequency divided by sixteen times the value of the baud-rate divisor, as follows:
483
484 _ baud rate = coprocessor-clock frequency / (16 * divisor).
485
486 Note that once both divisor-latch registers are set, at least eight coprocessor-clock
487 cycles should be allowed to pass before transmitting or receiving data. */
488 uint32_t reserved_6_31 : 26;
489 #endif /* Word 0 - End */
490 } cn81xx;
491 /* struct bdk_uaax_fbrd_s cn88xx; */
492 /* struct bdk_uaax_fbrd_cn81xx cn83xx; */
493 };
494 typedef union bdk_uaax_fbrd bdk_uaax_fbrd_t;
495
496 static inline uint64_t BDK_UAAX_FBRD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_FBRD(unsigned long a)497 static inline uint64_t BDK_UAAX_FBRD(unsigned long a)
498 {
499 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
500 return 0x87e028000028ll + 0x1000000ll * ((a) & 0x3);
501 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
502 return 0x87e028000028ll + 0x1000000ll * ((a) & 0x3);
503 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
504 return 0x87e024000028ll + 0x1000000ll * ((a) & 0x1);
505 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
506 return 0x87e028000028ll + 0x1000000ll * ((a) & 0x7);
507 __bdk_csr_fatal("UAAX_FBRD", 1, a, 0, 0, 0);
508 }
509
510 #define typedef_BDK_UAAX_FBRD(a) bdk_uaax_fbrd_t
511 #define bustype_BDK_UAAX_FBRD(a) BDK_CSR_TYPE_RSL32b
512 #define basename_BDK_UAAX_FBRD(a) "UAAX_FBRD"
513 #define device_bar_BDK_UAAX_FBRD(a) 0x0 /* PF_BAR0 */
514 #define busnum_BDK_UAAX_FBRD(a) (a)
515 #define arguments_BDK_UAAX_FBRD(a) (a),-1,-1,-1
516
517 /**
518 * Register (RSL32b) uaa#_fr
519 *
520 * UART Flag Register
521 */
522 union bdk_uaax_fr
523 {
524 uint32_t u;
525 struct bdk_uaax_fr_s
526 {
527 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
528 uint32_t reserved_9_31 : 23;
529 uint32_t ri : 1; /**< [ 8: 8](RO/H) Complement of ring indicator. not supported. */
530 uint32_t txfe : 1; /**< [ 7: 7](RO/H) Transmit FIFO empty. */
531 uint32_t rxff : 1; /**< [ 6: 6](RO/H) Receive FIFO full. */
532 uint32_t txff : 1; /**< [ 5: 5](RO/H) Transmit FIFO full. */
533 uint32_t rxfe : 1; /**< [ 4: 4](RO/H) Receive FIFO empty. */
534 uint32_t busy : 1; /**< [ 3: 3](RO/H) UART busy transmitting data. */
535 uint32_t dcd : 1; /**< [ 2: 2](RO/H) Data carrier detect. */
536 uint32_t dsr : 1; /**< [ 1: 1](RO/H) Data set ready. */
537 uint32_t cts : 1; /**< [ 0: 0](RO/H) Clear to send. Complement of the UART#_CTS_L modem status input pin. */
538 #else /* Word 0 - Little Endian */
539 uint32_t cts : 1; /**< [ 0: 0](RO/H) Clear to send. Complement of the UART#_CTS_L modem status input pin. */
540 uint32_t dsr : 1; /**< [ 1: 1](RO/H) Data set ready. */
541 uint32_t dcd : 1; /**< [ 2: 2](RO/H) Data carrier detect. */
542 uint32_t busy : 1; /**< [ 3: 3](RO/H) UART busy transmitting data. */
543 uint32_t rxfe : 1; /**< [ 4: 4](RO/H) Receive FIFO empty. */
544 uint32_t txff : 1; /**< [ 5: 5](RO/H) Transmit FIFO full. */
545 uint32_t rxff : 1; /**< [ 6: 6](RO/H) Receive FIFO full. */
546 uint32_t txfe : 1; /**< [ 7: 7](RO/H) Transmit FIFO empty. */
547 uint32_t ri : 1; /**< [ 8: 8](RO/H) Complement of ring indicator. not supported. */
548 uint32_t reserved_9_31 : 23;
549 #endif /* Word 0 - End */
550 } s;
551 /* struct bdk_uaax_fr_s cn; */
552 };
553 typedef union bdk_uaax_fr bdk_uaax_fr_t;
554
555 static inline uint64_t BDK_UAAX_FR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_FR(unsigned long a)556 static inline uint64_t BDK_UAAX_FR(unsigned long a)
557 {
558 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
559 return 0x87e028000018ll + 0x1000000ll * ((a) & 0x3);
560 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
561 return 0x87e028000018ll + 0x1000000ll * ((a) & 0x3);
562 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
563 return 0x87e024000018ll + 0x1000000ll * ((a) & 0x1);
564 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
565 return 0x87e028000018ll + 0x1000000ll * ((a) & 0x7);
566 __bdk_csr_fatal("UAAX_FR", 1, a, 0, 0, 0);
567 }
568
569 #define typedef_BDK_UAAX_FR(a) bdk_uaax_fr_t
570 #define bustype_BDK_UAAX_FR(a) BDK_CSR_TYPE_RSL32b
571 #define basename_BDK_UAAX_FR(a) "UAAX_FR"
572 #define device_bar_BDK_UAAX_FR(a) 0x0 /* PF_BAR0 */
573 #define busnum_BDK_UAAX_FR(a) (a)
574 #define arguments_BDK_UAAX_FR(a) (a),-1,-1,-1
575
576 /**
577 * Register (RSL32b) uaa#_ibrd
578 *
579 * UART Integer Baud Rate Register
580 */
581 union bdk_uaax_ibrd
582 {
583 uint32_t u;
584 struct bdk_uaax_ibrd_s
585 {
586 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
587 uint32_t reserved_16_31 : 16;
588 uint32_t baud_divint : 16; /**< [ 15: 0](R/W) Integer part of baud-rate divisor. See UAA()_FBRD. */
589 #else /* Word 0 - Little Endian */
590 uint32_t baud_divint : 16; /**< [ 15: 0](R/W) Integer part of baud-rate divisor. See UAA()_FBRD. */
591 uint32_t reserved_16_31 : 16;
592 #endif /* Word 0 - End */
593 } s;
594 /* struct bdk_uaax_ibrd_s cn; */
595 };
596 typedef union bdk_uaax_ibrd bdk_uaax_ibrd_t;
597
598 static inline uint64_t BDK_UAAX_IBRD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_IBRD(unsigned long a)599 static inline uint64_t BDK_UAAX_IBRD(unsigned long a)
600 {
601 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
602 return 0x87e028000024ll + 0x1000000ll * ((a) & 0x3);
603 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
604 return 0x87e028000024ll + 0x1000000ll * ((a) & 0x3);
605 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
606 return 0x87e024000024ll + 0x1000000ll * ((a) & 0x1);
607 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
608 return 0x87e028000024ll + 0x1000000ll * ((a) & 0x7);
609 __bdk_csr_fatal("UAAX_IBRD", 1, a, 0, 0, 0);
610 }
611
612 #define typedef_BDK_UAAX_IBRD(a) bdk_uaax_ibrd_t
613 #define bustype_BDK_UAAX_IBRD(a) BDK_CSR_TYPE_RSL32b
614 #define basename_BDK_UAAX_IBRD(a) "UAAX_IBRD"
615 #define device_bar_BDK_UAAX_IBRD(a) 0x0 /* PF_BAR0 */
616 #define busnum_BDK_UAAX_IBRD(a) (a)
617 #define arguments_BDK_UAAX_IBRD(a) (a),-1,-1,-1
618
619 /**
620 * Register (RSL32b) uaa#_icr
621 *
622 * UART Interrupt Clear Register
623 * Read value is zero for this register, not the interrupt state.
624 */
625 union bdk_uaax_icr
626 {
627 uint32_t u;
628 struct bdk_uaax_icr_s
629 {
630 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
631 uint32_t reserved_11_31 : 21;
632 uint32_t oeic : 1; /**< [ 10: 10](R/W1C) Overrun error interrupt clear. */
633 uint32_t beic : 1; /**< [ 9: 9](R/W1C) Break error interrupt clear. */
634 uint32_t peic : 1; /**< [ 8: 8](R/W1C) Parity error interrupt clear. */
635 uint32_t feic : 1; /**< [ 7: 7](R/W1C) Framing error interrupt clear. */
636 uint32_t rtic : 1; /**< [ 6: 6](R/W1C) Receive timeout interrupt clear. */
637 uint32_t txic : 1; /**< [ 5: 5](R/W1C) Transmit interrupt clear. */
638 uint32_t rxic : 1; /**< [ 4: 4](R/W1C) Receive interrupt clear. */
639 uint32_t dsrmic : 1; /**< [ 3: 3](R/W1C) DSR modem interrupt clear. */
640 uint32_t dcdmic : 1; /**< [ 2: 2](R/W1C) DCD modem interrupt clear. */
641 uint32_t ctsmic : 1; /**< [ 1: 1](R/W1C) CTS modem interrupt clear. */
642 uint32_t rimic : 1; /**< [ 0: 0](R/W1C) Ring indicator interrupt clear. Not implemented. */
643 #else /* Word 0 - Little Endian */
644 uint32_t rimic : 1; /**< [ 0: 0](R/W1C) Ring indicator interrupt clear. Not implemented. */
645 uint32_t ctsmic : 1; /**< [ 1: 1](R/W1C) CTS modem interrupt clear. */
646 uint32_t dcdmic : 1; /**< [ 2: 2](R/W1C) DCD modem interrupt clear. */
647 uint32_t dsrmic : 1; /**< [ 3: 3](R/W1C) DSR modem interrupt clear. */
648 uint32_t rxic : 1; /**< [ 4: 4](R/W1C) Receive interrupt clear. */
649 uint32_t txic : 1; /**< [ 5: 5](R/W1C) Transmit interrupt clear. */
650 uint32_t rtic : 1; /**< [ 6: 6](R/W1C) Receive timeout interrupt clear. */
651 uint32_t feic : 1; /**< [ 7: 7](R/W1C) Framing error interrupt clear. */
652 uint32_t peic : 1; /**< [ 8: 8](R/W1C) Parity error interrupt clear. */
653 uint32_t beic : 1; /**< [ 9: 9](R/W1C) Break error interrupt clear. */
654 uint32_t oeic : 1; /**< [ 10: 10](R/W1C) Overrun error interrupt clear. */
655 uint32_t reserved_11_31 : 21;
656 #endif /* Word 0 - End */
657 } s;
658 /* struct bdk_uaax_icr_s cn; */
659 };
660 typedef union bdk_uaax_icr bdk_uaax_icr_t;
661
662 static inline uint64_t BDK_UAAX_ICR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_ICR(unsigned long a)663 static inline uint64_t BDK_UAAX_ICR(unsigned long a)
664 {
665 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
666 return 0x87e028000044ll + 0x1000000ll * ((a) & 0x3);
667 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
668 return 0x87e028000044ll + 0x1000000ll * ((a) & 0x3);
669 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
670 return 0x87e024000044ll + 0x1000000ll * ((a) & 0x1);
671 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
672 return 0x87e028000044ll + 0x1000000ll * ((a) & 0x7);
673 __bdk_csr_fatal("UAAX_ICR", 1, a, 0, 0, 0);
674 }
675
676 #define typedef_BDK_UAAX_ICR(a) bdk_uaax_icr_t
677 #define bustype_BDK_UAAX_ICR(a) BDK_CSR_TYPE_RSL32b
678 #define basename_BDK_UAAX_ICR(a) "UAAX_ICR"
679 #define device_bar_BDK_UAAX_ICR(a) 0x0 /* PF_BAR0 */
680 #define busnum_BDK_UAAX_ICR(a) (a)
681 #define arguments_BDK_UAAX_ICR(a) (a),-1,-1,-1
682
683 /**
684 * Register (RSL32b) uaa#_ifls
685 *
686 * UART Interrupt FIFO Level Select Register
687 */
688 union bdk_uaax_ifls
689 {
690 uint32_t u;
691 struct bdk_uaax_ifls_s
692 {
693 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
694 uint32_t reserved_6_31 : 26;
695 uint32_t rxiflsel : 3; /**< [ 5: 3](R/W) Receive interrupt FIFO level select.
696 0x0 = Receive FIFO becomes \>= 1/8 full.
697 0x1 = Receive FIFO becomes \>= 1/4 full.
698 0x2 = Receive FIFO becomes \>= 1/2 full.
699 0x3 = Receive FIFO becomes \>= 3/4 full.
700 0x4 = Receive FIFO becomes \>= 7/8 full.
701 0x5-0x7 = Reserved. */
702 uint32_t txiflsel : 3; /**< [ 2: 0](R/W) Transmit interrupt FIFO level select.
703 0x0 = Transmit FIFO becomes \<= 1/8 full.
704 0x1 = Transmit FIFO becomes \<= 1/4 full.
705 0x2 = Transmit FIFO becomes \<= 1/2 full.
706 0x3 = Transmit FIFO becomes \<= 3/4 full.
707 0x4 = Transmit FIFO becomes \<= 7/8 full.
708 0x5-0x7 = Reserved. */
709 #else /* Word 0 - Little Endian */
710 uint32_t txiflsel : 3; /**< [ 2: 0](R/W) Transmit interrupt FIFO level select.
711 0x0 = Transmit FIFO becomes \<= 1/8 full.
712 0x1 = Transmit FIFO becomes \<= 1/4 full.
713 0x2 = Transmit FIFO becomes \<= 1/2 full.
714 0x3 = Transmit FIFO becomes \<= 3/4 full.
715 0x4 = Transmit FIFO becomes \<= 7/8 full.
716 0x5-0x7 = Reserved. */
717 uint32_t rxiflsel : 3; /**< [ 5: 3](R/W) Receive interrupt FIFO level select.
718 0x0 = Receive FIFO becomes \>= 1/8 full.
719 0x1 = Receive FIFO becomes \>= 1/4 full.
720 0x2 = Receive FIFO becomes \>= 1/2 full.
721 0x3 = Receive FIFO becomes \>= 3/4 full.
722 0x4 = Receive FIFO becomes \>= 7/8 full.
723 0x5-0x7 = Reserved. */
724 uint32_t reserved_6_31 : 26;
725 #endif /* Word 0 - End */
726 } s;
727 /* struct bdk_uaax_ifls_s cn; */
728 };
729 typedef union bdk_uaax_ifls bdk_uaax_ifls_t;
730
731 static inline uint64_t BDK_UAAX_IFLS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_IFLS(unsigned long a)732 static inline uint64_t BDK_UAAX_IFLS(unsigned long a)
733 {
734 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
735 return 0x87e028000034ll + 0x1000000ll * ((a) & 0x3);
736 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
737 return 0x87e028000034ll + 0x1000000ll * ((a) & 0x3);
738 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
739 return 0x87e024000034ll + 0x1000000ll * ((a) & 0x1);
740 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
741 return 0x87e028000034ll + 0x1000000ll * ((a) & 0x7);
742 __bdk_csr_fatal("UAAX_IFLS", 1, a, 0, 0, 0);
743 }
744
745 #define typedef_BDK_UAAX_IFLS(a) bdk_uaax_ifls_t
746 #define bustype_BDK_UAAX_IFLS(a) BDK_CSR_TYPE_RSL32b
747 #define basename_BDK_UAAX_IFLS(a) "UAAX_IFLS"
748 #define device_bar_BDK_UAAX_IFLS(a) 0x0 /* PF_BAR0 */
749 #define busnum_BDK_UAAX_IFLS(a) (a)
750 #define arguments_BDK_UAAX_IFLS(a) (a),-1,-1,-1
751
752 /**
753 * Register (RSL32b) uaa#_imsc
754 *
755 * UART Interrupt Mask Set/Clear Register
756 */
757 union bdk_uaax_imsc
758 {
759 uint32_t u;
760 struct bdk_uaax_imsc_s
761 {
762 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
763 uint32_t reserved_11_31 : 21;
764 uint32_t oeim : 1; /**< [ 10: 10](R/W) Overrun error interrupt mask. */
765 uint32_t beim : 1; /**< [ 9: 9](R/W) Break error interrupt mask. */
766 uint32_t peim : 1; /**< [ 8: 8](R/W) Parity error interrupt mask. */
767 uint32_t feim : 1; /**< [ 7: 7](R/W) Framing error interrupt mask. */
768 uint32_t rtim : 1; /**< [ 6: 6](R/W) Receive timeout interrupt mask. */
769 uint32_t txim : 1; /**< [ 5: 5](R/W) Transmit interrupt mask. */
770 uint32_t rxim : 1; /**< [ 4: 4](R/W) Receive interrupt mask. */
771 uint32_t dsrmim : 1; /**< [ 3: 3](R/W) DSR modem interrupt mask. */
772 uint32_t dcdmim : 1; /**< [ 2: 2](R/W) DCD modem interrupt mask. */
773 uint32_t ctsmim : 1; /**< [ 1: 1](R/W) CTS modem interrupt mask. */
774 uint32_t rimim : 1; /**< [ 0: 0](R/W) Ring indicator interrupt mask. Not implemented. */
775 #else /* Word 0 - Little Endian */
776 uint32_t rimim : 1; /**< [ 0: 0](R/W) Ring indicator interrupt mask. Not implemented. */
777 uint32_t ctsmim : 1; /**< [ 1: 1](R/W) CTS modem interrupt mask. */
778 uint32_t dcdmim : 1; /**< [ 2: 2](R/W) DCD modem interrupt mask. */
779 uint32_t dsrmim : 1; /**< [ 3: 3](R/W) DSR modem interrupt mask. */
780 uint32_t rxim : 1; /**< [ 4: 4](R/W) Receive interrupt mask. */
781 uint32_t txim : 1; /**< [ 5: 5](R/W) Transmit interrupt mask. */
782 uint32_t rtim : 1; /**< [ 6: 6](R/W) Receive timeout interrupt mask. */
783 uint32_t feim : 1; /**< [ 7: 7](R/W) Framing error interrupt mask. */
784 uint32_t peim : 1; /**< [ 8: 8](R/W) Parity error interrupt mask. */
785 uint32_t beim : 1; /**< [ 9: 9](R/W) Break error interrupt mask. */
786 uint32_t oeim : 1; /**< [ 10: 10](R/W) Overrun error interrupt mask. */
787 uint32_t reserved_11_31 : 21;
788 #endif /* Word 0 - End */
789 } s;
790 /* struct bdk_uaax_imsc_s cn; */
791 };
792 typedef union bdk_uaax_imsc bdk_uaax_imsc_t;
793
794 static inline uint64_t BDK_UAAX_IMSC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_IMSC(unsigned long a)795 static inline uint64_t BDK_UAAX_IMSC(unsigned long a)
796 {
797 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
798 return 0x87e028000038ll + 0x1000000ll * ((a) & 0x3);
799 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
800 return 0x87e028000038ll + 0x1000000ll * ((a) & 0x3);
801 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
802 return 0x87e024000038ll + 0x1000000ll * ((a) & 0x1);
803 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
804 return 0x87e028000038ll + 0x1000000ll * ((a) & 0x7);
805 __bdk_csr_fatal("UAAX_IMSC", 1, a, 0, 0, 0);
806 }
807
808 #define typedef_BDK_UAAX_IMSC(a) bdk_uaax_imsc_t
809 #define bustype_BDK_UAAX_IMSC(a) BDK_CSR_TYPE_RSL32b
810 #define basename_BDK_UAAX_IMSC(a) "UAAX_IMSC"
811 #define device_bar_BDK_UAAX_IMSC(a) 0x0 /* PF_BAR0 */
812 #define busnum_BDK_UAAX_IMSC(a) (a)
813 #define arguments_BDK_UAAX_IMSC(a) (a),-1,-1,-1
814
815 /**
816 * Register (RSL) uaa#_io_ctl
817 *
818 * UART IO Control Register
819 * This register controls the UAA[0..1] IO drive strength and slew rates. The additional
820 * UAA interfaces are controlled by GPIO_IO_CTL[DRIVEx] and GPIO_IO_CTL[SLEWx] based
821 * on the selected pins.
822 */
823 union bdk_uaax_io_ctl
824 {
825 uint64_t u;
826 struct bdk_uaax_io_ctl_s
827 {
828 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
829 uint64_t reserved_4_63 : 60;
830 uint64_t drive : 2; /**< [ 3: 2](R/W) UART bus pin output drive strength.
831 0x0 = 2 mA.
832 0x1 = 4 mA.
833 0x2 = 8 mA.
834 0x3 = 16 mA. */
835 uint64_t reserved_1 : 1;
836 uint64_t slew : 1; /**< [ 0: 0](R/W) UART bus pin output slew rate control.
837 0 = Low slew rate.
838 1 = High slew rate. */
839 #else /* Word 0 - Little Endian */
840 uint64_t slew : 1; /**< [ 0: 0](R/W) UART bus pin output slew rate control.
841 0 = Low slew rate.
842 1 = High slew rate. */
843 uint64_t reserved_1 : 1;
844 uint64_t drive : 2; /**< [ 3: 2](R/W) UART bus pin output drive strength.
845 0x0 = 2 mA.
846 0x1 = 4 mA.
847 0x2 = 8 mA.
848 0x3 = 16 mA. */
849 uint64_t reserved_4_63 : 60;
850 #endif /* Word 0 - End */
851 } s;
852 /* struct bdk_uaax_io_ctl_s cn; */
853 };
854 typedef union bdk_uaax_io_ctl bdk_uaax_io_ctl_t;
855
856 static inline uint64_t BDK_UAAX_IO_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_IO_CTL(unsigned long a)857 static inline uint64_t BDK_UAAX_IO_CTL(unsigned long a)
858 {
859 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
860 return 0x87e028001028ll + 0x1000000ll * ((a) & 0x7);
861 __bdk_csr_fatal("UAAX_IO_CTL", 1, a, 0, 0, 0);
862 }
863
864 #define typedef_BDK_UAAX_IO_CTL(a) bdk_uaax_io_ctl_t
865 #define bustype_BDK_UAAX_IO_CTL(a) BDK_CSR_TYPE_RSL
866 #define basename_BDK_UAAX_IO_CTL(a) "UAAX_IO_CTL"
867 #define device_bar_BDK_UAAX_IO_CTL(a) 0x0 /* PF_BAR0 */
868 #define busnum_BDK_UAAX_IO_CTL(a) (a)
869 #define arguments_BDK_UAAX_IO_CTL(a) (a),-1,-1,-1
870
871 /**
872 * Register (RSL32b) uaa#_lcr_h
873 *
874 * UART Line Control Register
875 */
876 union bdk_uaax_lcr_h
877 {
878 uint32_t u;
879 struct bdk_uaax_lcr_h_s
880 {
881 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
882 uint32_t reserved_8_31 : 24;
883 uint32_t sps : 1; /**< [ 7: 7](R/W) Stick parity select. If set, and [PEN] is set, forces the parity bit to the opposite of EPS. */
884 uint32_t wlen : 2; /**< [ 6: 5](R/W) Word length:
885 0x0 = 5 bits.
886 0x1 = 6 bits.
887 0x2 = 7 bits.
888 0x3 = 8 bits. */
889 uint32_t fen : 1; /**< [ 4: 4](R/W) Enable FIFOs.
890 0 = FIFOs disabled, FIFOs are single character deep.
891 1 = FIFO enabled. */
892 uint32_t stp2 : 1; /**< [ 3: 3](R/W) Two stop bits select. */
893 uint32_t eps : 1; /**< [ 2: 2](R/W) Even parity select. */
894 uint32_t pen : 1; /**< [ 1: 1](R/W) Parity enable. */
895 uint32_t brk : 1; /**< [ 0: 0](R/W) Send break. A low level is continually transmitted after completion of the current character. */
896 #else /* Word 0 - Little Endian */
897 uint32_t brk : 1; /**< [ 0: 0](R/W) Send break. A low level is continually transmitted after completion of the current character. */
898 uint32_t pen : 1; /**< [ 1: 1](R/W) Parity enable. */
899 uint32_t eps : 1; /**< [ 2: 2](R/W) Even parity select. */
900 uint32_t stp2 : 1; /**< [ 3: 3](R/W) Two stop bits select. */
901 uint32_t fen : 1; /**< [ 4: 4](R/W) Enable FIFOs.
902 0 = FIFOs disabled, FIFOs are single character deep.
903 1 = FIFO enabled. */
904 uint32_t wlen : 2; /**< [ 6: 5](R/W) Word length:
905 0x0 = 5 bits.
906 0x1 = 6 bits.
907 0x2 = 7 bits.
908 0x3 = 8 bits. */
909 uint32_t sps : 1; /**< [ 7: 7](R/W) Stick parity select. If set, and [PEN] is set, forces the parity bit to the opposite of EPS. */
910 uint32_t reserved_8_31 : 24;
911 #endif /* Word 0 - End */
912 } s;
913 /* struct bdk_uaax_lcr_h_s cn; */
914 };
915 typedef union bdk_uaax_lcr_h bdk_uaax_lcr_h_t;
916
917 static inline uint64_t BDK_UAAX_LCR_H(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_LCR_H(unsigned long a)918 static inline uint64_t BDK_UAAX_LCR_H(unsigned long a)
919 {
920 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
921 return 0x87e02800002cll + 0x1000000ll * ((a) & 0x3);
922 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
923 return 0x87e02800002cll + 0x1000000ll * ((a) & 0x3);
924 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
925 return 0x87e02400002cll + 0x1000000ll * ((a) & 0x1);
926 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
927 return 0x87e02800002cll + 0x1000000ll * ((a) & 0x7);
928 __bdk_csr_fatal("UAAX_LCR_H", 1, a, 0, 0, 0);
929 }
930
931 #define typedef_BDK_UAAX_LCR_H(a) bdk_uaax_lcr_h_t
932 #define bustype_BDK_UAAX_LCR_H(a) BDK_CSR_TYPE_RSL32b
933 #define basename_BDK_UAAX_LCR_H(a) "UAAX_LCR_H"
934 #define device_bar_BDK_UAAX_LCR_H(a) 0x0 /* PF_BAR0 */
935 #define busnum_BDK_UAAX_LCR_H(a) (a)
936 #define arguments_BDK_UAAX_LCR_H(a) (a),-1,-1,-1
937
938 /**
939 * Register (RSL32b) uaa#_mis
940 *
941 * UART Masked Interrupt Status Register
942 * Indicates state of interrupts after masking.
943 * Internal:
944 * Note this register was not present in SBSA 2.3, but is referenced
945 * by the Linux driver, so has been defined here.
946 */
947 union bdk_uaax_mis
948 {
949 uint32_t u;
950 struct bdk_uaax_mis_s
951 {
952 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
953 uint32_t reserved_11_31 : 21;
954 uint32_t oemis : 1; /**< [ 10: 10](RO/H) Overrun error interrupt status. */
955 uint32_t bemis : 1; /**< [ 9: 9](RO/H) Break error interrupt status. */
956 uint32_t pemis : 1; /**< [ 8: 8](RO/H) Parity error interrupt status. */
957 uint32_t femis : 1; /**< [ 7: 7](RO/H) Framing error interrupt status. */
958 uint32_t rtmis : 1; /**< [ 6: 6](RO/H) Receive timeout interrupt status. */
959 uint32_t txmis : 1; /**< [ 5: 5](RO/H) Transmit interrupt status. */
960 uint32_t rxmis : 1; /**< [ 4: 4](RO/H) Receive interrupt status. */
961 uint32_t dsrmmis : 1; /**< [ 3: 3](RO/H) DSR modem interrupt status. */
962 uint32_t dcdmmis : 1; /**< [ 2: 2](RO/H) DCD modem interrupt status. */
963 uint32_t ctsmmis : 1; /**< [ 1: 1](RO/H) CTS modem interrupt status. */
964 uint32_t rimmis : 1; /**< [ 0: 0](RO/H) Ring indicator interrupt status. Not implemented. */
965 #else /* Word 0 - Little Endian */
966 uint32_t rimmis : 1; /**< [ 0: 0](RO/H) Ring indicator interrupt status. Not implemented. */
967 uint32_t ctsmmis : 1; /**< [ 1: 1](RO/H) CTS modem interrupt status. */
968 uint32_t dcdmmis : 1; /**< [ 2: 2](RO/H) DCD modem interrupt status. */
969 uint32_t dsrmmis : 1; /**< [ 3: 3](RO/H) DSR modem interrupt status. */
970 uint32_t rxmis : 1; /**< [ 4: 4](RO/H) Receive interrupt status. */
971 uint32_t txmis : 1; /**< [ 5: 5](RO/H) Transmit interrupt status. */
972 uint32_t rtmis : 1; /**< [ 6: 6](RO/H) Receive timeout interrupt status. */
973 uint32_t femis : 1; /**< [ 7: 7](RO/H) Framing error interrupt status. */
974 uint32_t pemis : 1; /**< [ 8: 8](RO/H) Parity error interrupt status. */
975 uint32_t bemis : 1; /**< [ 9: 9](RO/H) Break error interrupt status. */
976 uint32_t oemis : 1; /**< [ 10: 10](RO/H) Overrun error interrupt status. */
977 uint32_t reserved_11_31 : 21;
978 #endif /* Word 0 - End */
979 } s;
980 /* struct bdk_uaax_mis_s cn; */
981 };
982 typedef union bdk_uaax_mis bdk_uaax_mis_t;
983
984 static inline uint64_t BDK_UAAX_MIS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_MIS(unsigned long a)985 static inline uint64_t BDK_UAAX_MIS(unsigned long a)
986 {
987 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
988 return 0x87e028000040ll + 0x1000000ll * ((a) & 0x3);
989 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
990 return 0x87e028000040ll + 0x1000000ll * ((a) & 0x3);
991 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
992 return 0x87e024000040ll + 0x1000000ll * ((a) & 0x1);
993 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
994 return 0x87e028000040ll + 0x1000000ll * ((a) & 0x7);
995 __bdk_csr_fatal("UAAX_MIS", 1, a, 0, 0, 0);
996 }
997
998 #define typedef_BDK_UAAX_MIS(a) bdk_uaax_mis_t
999 #define bustype_BDK_UAAX_MIS(a) BDK_CSR_TYPE_RSL32b
1000 #define basename_BDK_UAAX_MIS(a) "UAAX_MIS"
1001 #define device_bar_BDK_UAAX_MIS(a) 0x0 /* PF_BAR0 */
1002 #define busnum_BDK_UAAX_MIS(a) (a)
1003 #define arguments_BDK_UAAX_MIS(a) (a),-1,-1,-1
1004
1005 /**
1006 * Register (RSL) uaa#_msix_pba#
1007 *
1008 * UART MSI-X Pending Bit Array Registers
1009 * This register is the MSI-X PBA table, the bit number is indexed by the UAA_INT_VEC_E enumeration.
1010 */
1011 union bdk_uaax_msix_pbax
1012 {
1013 uint64_t u;
1014 struct bdk_uaax_msix_pbax_s
1015 {
1016 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1017 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for each interrupt, enumerated by UAA_INT_VEC_E. Bits that have no
1018 associated UAA_INT_VEC_E are zero. */
1019 #else /* Word 0 - Little Endian */
1020 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for each interrupt, enumerated by UAA_INT_VEC_E. Bits that have no
1021 associated UAA_INT_VEC_E are zero. */
1022 #endif /* Word 0 - End */
1023 } s;
1024 /* struct bdk_uaax_msix_pbax_s cn; */
1025 };
1026 typedef union bdk_uaax_msix_pbax bdk_uaax_msix_pbax_t;
1027
1028 static inline uint64_t BDK_UAAX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_UAAX_MSIX_PBAX(unsigned long a,unsigned long b)1029 static inline uint64_t BDK_UAAX_MSIX_PBAX(unsigned long a, unsigned long b)
1030 {
1031 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b==0)))
1032 return 0x87e028ff0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
1033 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b==0)))
1034 return 0x87e028ff0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
1035 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b==0)))
1036 return 0x87e024ff0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
1037 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=7) && (b==0)))
1038 return 0x87e028ff0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x0);
1039 __bdk_csr_fatal("UAAX_MSIX_PBAX", 2, a, b, 0, 0);
1040 }
1041
1042 #define typedef_BDK_UAAX_MSIX_PBAX(a,b) bdk_uaax_msix_pbax_t
1043 #define bustype_BDK_UAAX_MSIX_PBAX(a,b) BDK_CSR_TYPE_RSL
1044 #define basename_BDK_UAAX_MSIX_PBAX(a,b) "UAAX_MSIX_PBAX"
1045 #define device_bar_BDK_UAAX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
1046 #define busnum_BDK_UAAX_MSIX_PBAX(a,b) (a)
1047 #define arguments_BDK_UAAX_MSIX_PBAX(a,b) (a),(b),-1,-1
1048
1049 /**
1050 * Register (RSL) uaa#_msix_vec#_addr
1051 *
1052 * UART MSI-X Vector Table Address Registers
1053 * This register is the MSI-X vector table, indexed by the UAA_INT_VEC_E enumeration.
1054 */
1055 union bdk_uaax_msix_vecx_addr
1056 {
1057 uint64_t u;
1058 struct bdk_uaax_msix_vecx_addr_s
1059 {
1060 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1061 uint64_t reserved_53_63 : 11;
1062 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1063 uint64_t reserved_1 : 1;
1064 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1065 0 = This vector may be read or written by either secure or nonsecure states.
1066 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1067 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1068 by the nonsecure world.
1069
1070 If PCCPF_UAA(0..1)_VSEC_SCTL[MSIX_SEC] (for documentation, see
1071 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1072 was set. */
1073 #else /* Word 0 - Little Endian */
1074 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1075 0 = This vector may be read or written by either secure or nonsecure states.
1076 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1077 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1078 by the nonsecure world.
1079
1080 If PCCPF_UAA(0..1)_VSEC_SCTL[MSIX_SEC] (for documentation, see
1081 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1082 was set. */
1083 uint64_t reserved_1 : 1;
1084 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1085 uint64_t reserved_53_63 : 11;
1086 #endif /* Word 0 - End */
1087 } s;
1088 struct bdk_uaax_msix_vecx_addr_cn9
1089 {
1090 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1091 uint64_t reserved_53_63 : 11;
1092 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1093 uint64_t reserved_1 : 1;
1094 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1095 0 = This vector may be read or written by either secure or nonsecure states.
1096 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1097 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1098 by the nonsecure world.
1099
1100 If PCCPF_UAA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
1101 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1102 was set. */
1103 #else /* Word 0 - Little Endian */
1104 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1105 0 = This vector may be read or written by either secure or nonsecure states.
1106 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1107 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1108 by the nonsecure world.
1109
1110 If PCCPF_UAA()_VSEC_SCTL[MSIX_SEC] (for documentation, see
1111 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1112 was set. */
1113 uint64_t reserved_1 : 1;
1114 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1115 uint64_t reserved_53_63 : 11;
1116 #endif /* Word 0 - End */
1117 } cn9;
1118 struct bdk_uaax_msix_vecx_addr_cn81xx
1119 {
1120 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1121 uint64_t reserved_49_63 : 15;
1122 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1123 uint64_t reserved_1 : 1;
1124 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1125 0 = This vector may be read or written by either secure or nonsecure states.
1126 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1127 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1128 by the nonsecure world.
1129
1130 If PCCPF_UAA(0..3)_VSEC_SCTL[MSIX_SEC] (for documentation, see
1131 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1132 was set. */
1133 #else /* Word 0 - Little Endian */
1134 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1135 0 = This vector may be read or written by either secure or nonsecure states.
1136 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1137 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1138 by the nonsecure world.
1139
1140 If PCCPF_UAA(0..3)_VSEC_SCTL[MSIX_SEC] (for documentation, see
1141 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1142 was set. */
1143 uint64_t reserved_1 : 1;
1144 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1145 uint64_t reserved_49_63 : 15;
1146 #endif /* Word 0 - End */
1147 } cn81xx;
1148 struct bdk_uaax_msix_vecx_addr_cn88xx
1149 {
1150 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1151 uint64_t reserved_49_63 : 15;
1152 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1153 uint64_t reserved_1 : 1;
1154 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1155 0 = This vector may be read or written by either secure or nonsecure states.
1156 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1157 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1158 by the nonsecure world.
1159
1160 If PCCPF_UAA(0..1)_VSEC_SCTL[MSIX_SEC] (for documentation, see
1161 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1162 was set. */
1163 #else /* Word 0 - Little Endian */
1164 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
1165 0 = This vector may be read or written by either secure or nonsecure states.
1166 1 = This vector's UAA()_MSIX_VEC()_ADDR, UAA()_MSIX_VEC()_CTL, and
1167 corresponding bit of UAA()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
1168 by the nonsecure world.
1169
1170 If PCCPF_UAA(0..1)_VSEC_SCTL[MSIX_SEC] (for documentation, see
1171 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is set, all vectors are secure and function as if [SECVEC]
1172 was set. */
1173 uint64_t reserved_1 : 1;
1174 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
1175 uint64_t reserved_49_63 : 15;
1176 #endif /* Word 0 - End */
1177 } cn88xx;
1178 /* struct bdk_uaax_msix_vecx_addr_cn81xx cn83xx; */
1179 };
1180 typedef union bdk_uaax_msix_vecx_addr bdk_uaax_msix_vecx_addr_t;
1181
1182 static inline uint64_t BDK_UAAX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_UAAX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)1183 static inline uint64_t BDK_UAAX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
1184 {
1185 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
1186 return 0x87e028f00000ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x1);
1187 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=1)))
1188 return 0x87e028f00000ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x1);
1189 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=1)))
1190 return 0x87e024f00000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
1191 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=7) && (b<=1)))
1192 return 0x87e028f00000ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x1);
1193 __bdk_csr_fatal("UAAX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
1194 }
1195
1196 #define typedef_BDK_UAAX_MSIX_VECX_ADDR(a,b) bdk_uaax_msix_vecx_addr_t
1197 #define bustype_BDK_UAAX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_RSL
1198 #define basename_BDK_UAAX_MSIX_VECX_ADDR(a,b) "UAAX_MSIX_VECX_ADDR"
1199 #define device_bar_BDK_UAAX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
1200 #define busnum_BDK_UAAX_MSIX_VECX_ADDR(a,b) (a)
1201 #define arguments_BDK_UAAX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
1202
1203 /**
1204 * Register (RSL) uaa#_msix_vec#_ctl
1205 *
1206 * UART MSI-X Vector Table Control and Data Registers
1207 * This register is the MSI-X vector table, indexed by the UAA_INT_VEC_E enumeration.
1208 */
1209 union bdk_uaax_msix_vecx_ctl
1210 {
1211 uint64_t u;
1212 struct bdk_uaax_msix_vecx_ctl_s
1213 {
1214 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1215 uint64_t reserved_33_63 : 31;
1216 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
1217 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
1218 #else /* Word 0 - Little Endian */
1219 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
1220 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
1221 uint64_t reserved_33_63 : 31;
1222 #endif /* Word 0 - End */
1223 } s;
1224 struct bdk_uaax_msix_vecx_ctl_cn8
1225 {
1226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1227 uint64_t reserved_33_63 : 31;
1228 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
1229 uint64_t reserved_20_31 : 12;
1230 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
1231 #else /* Word 0 - Little Endian */
1232 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
1233 uint64_t reserved_20_31 : 12;
1234 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
1235 uint64_t reserved_33_63 : 31;
1236 #endif /* Word 0 - End */
1237 } cn8;
1238 /* struct bdk_uaax_msix_vecx_ctl_s cn9; */
1239 };
1240 typedef union bdk_uaax_msix_vecx_ctl bdk_uaax_msix_vecx_ctl_t;
1241
1242 static inline uint64_t BDK_UAAX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_UAAX_MSIX_VECX_CTL(unsigned long a,unsigned long b)1243 static inline uint64_t BDK_UAAX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
1244 {
1245 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
1246 return 0x87e028f00008ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x1);
1247 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=1)))
1248 return 0x87e028f00008ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x1);
1249 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=1)))
1250 return 0x87e024f00008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1);
1251 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a<=7) && (b<=1)))
1252 return 0x87e028f00008ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x1);
1253 __bdk_csr_fatal("UAAX_MSIX_VECX_CTL", 2, a, b, 0, 0);
1254 }
1255
1256 #define typedef_BDK_UAAX_MSIX_VECX_CTL(a,b) bdk_uaax_msix_vecx_ctl_t
1257 #define bustype_BDK_UAAX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_RSL
1258 #define basename_BDK_UAAX_MSIX_VECX_CTL(a,b) "UAAX_MSIX_VECX_CTL"
1259 #define device_bar_BDK_UAAX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
1260 #define busnum_BDK_UAAX_MSIX_VECX_CTL(a,b) (a)
1261 #define arguments_BDK_UAAX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
1262
1263 /**
1264 * Register (RSL32b) uaa#_pidr0
1265 *
1266 * UART Component Identification Register 0
1267 */
1268 union bdk_uaax_pidr0
1269 {
1270 uint32_t u;
1271 struct bdk_uaax_pidr0_s
1272 {
1273 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1274 uint32_t reserved_8_31 : 24;
1275 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. ARM-assigned PL011 compatible. */
1276 #else /* Word 0 - Little Endian */
1277 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. ARM-assigned PL011 compatible. */
1278 uint32_t reserved_8_31 : 24;
1279 #endif /* Word 0 - End */
1280 } s;
1281 /* struct bdk_uaax_pidr0_s cn; */
1282 };
1283 typedef union bdk_uaax_pidr0 bdk_uaax_pidr0_t;
1284
1285 static inline uint64_t BDK_UAAX_PIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR0(unsigned long a)1286 static inline uint64_t BDK_UAAX_PIDR0(unsigned long a)
1287 {
1288 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1289 return 0x87e028000fe0ll + 0x1000000ll * ((a) & 0x3);
1290 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1291 return 0x87e028000fe0ll + 0x1000000ll * ((a) & 0x3);
1292 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1293 return 0x87e024000fe0ll + 0x1000000ll * ((a) & 0x1);
1294 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1295 return 0x87e028000fe0ll + 0x1000000ll * ((a) & 0x7);
1296 __bdk_csr_fatal("UAAX_PIDR0", 1, a, 0, 0, 0);
1297 }
1298
1299 #define typedef_BDK_UAAX_PIDR0(a) bdk_uaax_pidr0_t
1300 #define bustype_BDK_UAAX_PIDR0(a) BDK_CSR_TYPE_RSL32b
1301 #define basename_BDK_UAAX_PIDR0(a) "UAAX_PIDR0"
1302 #define device_bar_BDK_UAAX_PIDR0(a) 0x0 /* PF_BAR0 */
1303 #define busnum_BDK_UAAX_PIDR0(a) (a)
1304 #define arguments_BDK_UAAX_PIDR0(a) (a),-1,-1,-1
1305
1306 /**
1307 * Register (RSL32b) uaa#_pidr1
1308 *
1309 * UART Peripheral Identification Register 1
1310 */
1311 union bdk_uaax_pidr1
1312 {
1313 uint32_t u;
1314 struct bdk_uaax_pidr1_s
1315 {
1316 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1317 uint32_t reserved_8_31 : 24;
1318 uint32_t idcode : 4; /**< [ 7: 4](RO) ARM identification. */
1319 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. ARM-assigned PL011 compatible. */
1320 #else /* Word 0 - Little Endian */
1321 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. ARM-assigned PL011 compatible. */
1322 uint32_t idcode : 4; /**< [ 7: 4](RO) ARM identification. */
1323 uint32_t reserved_8_31 : 24;
1324 #endif /* Word 0 - End */
1325 } s;
1326 /* struct bdk_uaax_pidr1_s cn; */
1327 };
1328 typedef union bdk_uaax_pidr1 bdk_uaax_pidr1_t;
1329
1330 static inline uint64_t BDK_UAAX_PIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR1(unsigned long a)1331 static inline uint64_t BDK_UAAX_PIDR1(unsigned long a)
1332 {
1333 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1334 return 0x87e028000fe4ll + 0x1000000ll * ((a) & 0x3);
1335 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1336 return 0x87e028000fe4ll + 0x1000000ll * ((a) & 0x3);
1337 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1338 return 0x87e024000fe4ll + 0x1000000ll * ((a) & 0x1);
1339 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1340 return 0x87e028000fe4ll + 0x1000000ll * ((a) & 0x7);
1341 __bdk_csr_fatal("UAAX_PIDR1", 1, a, 0, 0, 0);
1342 }
1343
1344 #define typedef_BDK_UAAX_PIDR1(a) bdk_uaax_pidr1_t
1345 #define bustype_BDK_UAAX_PIDR1(a) BDK_CSR_TYPE_RSL32b
1346 #define basename_BDK_UAAX_PIDR1(a) "UAAX_PIDR1"
1347 #define device_bar_BDK_UAAX_PIDR1(a) 0x0 /* PF_BAR0 */
1348 #define busnum_BDK_UAAX_PIDR1(a) (a)
1349 #define arguments_BDK_UAAX_PIDR1(a) (a),-1,-1,-1
1350
1351 /**
1352 * Register (RSL32b) uaa#_pidr2
1353 *
1354 * UART Peripheral Identification Register 2
1355 */
1356 union bdk_uaax_pidr2
1357 {
1358 uint32_t u;
1359 struct bdk_uaax_pidr2_s
1360 {
1361 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1362 uint32_t reserved_8_31 : 24;
1363 uint32_t revision : 4; /**< [ 7: 4](RO) UART architectural revision.
1364 0x3 = r1p5. */
1365 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. 0 = Legacy UART assignment. */
1366 uint32_t idcode : 3; /**< [ 2: 0](RO) ARM-design compatible. */
1367 #else /* Word 0 - Little Endian */
1368 uint32_t idcode : 3; /**< [ 2: 0](RO) ARM-design compatible. */
1369 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. 0 = Legacy UART assignment. */
1370 uint32_t revision : 4; /**< [ 7: 4](RO) UART architectural revision.
1371 0x3 = r1p5. */
1372 uint32_t reserved_8_31 : 24;
1373 #endif /* Word 0 - End */
1374 } s;
1375 /* struct bdk_uaax_pidr2_s cn; */
1376 };
1377 typedef union bdk_uaax_pidr2 bdk_uaax_pidr2_t;
1378
1379 static inline uint64_t BDK_UAAX_PIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR2(unsigned long a)1380 static inline uint64_t BDK_UAAX_PIDR2(unsigned long a)
1381 {
1382 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1383 return 0x87e028000fe8ll + 0x1000000ll * ((a) & 0x3);
1384 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1385 return 0x87e028000fe8ll + 0x1000000ll * ((a) & 0x3);
1386 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1387 return 0x87e024000fe8ll + 0x1000000ll * ((a) & 0x1);
1388 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1389 return 0x87e028000fe8ll + 0x1000000ll * ((a) & 0x7);
1390 __bdk_csr_fatal("UAAX_PIDR2", 1, a, 0, 0, 0);
1391 }
1392
1393 #define typedef_BDK_UAAX_PIDR2(a) bdk_uaax_pidr2_t
1394 #define bustype_BDK_UAAX_PIDR2(a) BDK_CSR_TYPE_RSL32b
1395 #define basename_BDK_UAAX_PIDR2(a) "UAAX_PIDR2"
1396 #define device_bar_BDK_UAAX_PIDR2(a) 0x0 /* PF_BAR0 */
1397 #define busnum_BDK_UAAX_PIDR2(a) (a)
1398 #define arguments_BDK_UAAX_PIDR2(a) (a),-1,-1,-1
1399
1400 /**
1401 * Register (RSL32b) uaa#_pidr3
1402 *
1403 * UART Peripheral Identification Register 3
1404 */
1405 union bdk_uaax_pidr3
1406 {
1407 uint32_t u;
1408 struct bdk_uaax_pidr3_s
1409 {
1410 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1411 uint32_t reserved_8_31 : 24;
1412 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
1413 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
1414 product, major and minor pass numbers. */
1415 #else /* Word 0 - Little Endian */
1416 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
1417 product, major and minor pass numbers. */
1418 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
1419 uint32_t reserved_8_31 : 24;
1420 #endif /* Word 0 - End */
1421 } s;
1422 /* struct bdk_uaax_pidr3_s cn; */
1423 };
1424 typedef union bdk_uaax_pidr3 bdk_uaax_pidr3_t;
1425
1426 static inline uint64_t BDK_UAAX_PIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR3(unsigned long a)1427 static inline uint64_t BDK_UAAX_PIDR3(unsigned long a)
1428 {
1429 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1430 return 0x87e028000fecll + 0x1000000ll * ((a) & 0x3);
1431 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1432 return 0x87e028000fecll + 0x1000000ll * ((a) & 0x3);
1433 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1434 return 0x87e024000fecll + 0x1000000ll * ((a) & 0x1);
1435 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1436 return 0x87e028000fecll + 0x1000000ll * ((a) & 0x7);
1437 __bdk_csr_fatal("UAAX_PIDR3", 1, a, 0, 0, 0);
1438 }
1439
1440 #define typedef_BDK_UAAX_PIDR3(a) bdk_uaax_pidr3_t
1441 #define bustype_BDK_UAAX_PIDR3(a) BDK_CSR_TYPE_RSL32b
1442 #define basename_BDK_UAAX_PIDR3(a) "UAAX_PIDR3"
1443 #define device_bar_BDK_UAAX_PIDR3(a) 0x0 /* PF_BAR0 */
1444 #define busnum_BDK_UAAX_PIDR3(a) (a)
1445 #define arguments_BDK_UAAX_PIDR3(a) (a),-1,-1,-1
1446
1447 /**
1448 * Register (RSL32b) uaa#_pidr4
1449 *
1450 * UART Peripheral Identification Register 4
1451 */
1452 union bdk_uaax_pidr4
1453 {
1454 uint32_t u;
1455 struct bdk_uaax_pidr4_s
1456 {
1457 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1458 uint32_t reserved_0_31 : 32;
1459 #else /* Word 0 - Little Endian */
1460 uint32_t reserved_0_31 : 32;
1461 #endif /* Word 0 - End */
1462 } s;
1463 /* struct bdk_uaax_pidr4_s cn; */
1464 };
1465 typedef union bdk_uaax_pidr4 bdk_uaax_pidr4_t;
1466
1467 static inline uint64_t BDK_UAAX_PIDR4(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR4(unsigned long a)1468 static inline uint64_t BDK_UAAX_PIDR4(unsigned long a)
1469 {
1470 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1471 return 0x87e028000fd0ll + 0x1000000ll * ((a) & 0x3);
1472 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1473 return 0x87e028000fd0ll + 0x1000000ll * ((a) & 0x3);
1474 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1475 return 0x87e024000fd0ll + 0x1000000ll * ((a) & 0x1);
1476 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1477 return 0x87e028000fd0ll + 0x1000000ll * ((a) & 0x7);
1478 __bdk_csr_fatal("UAAX_PIDR4", 1, a, 0, 0, 0);
1479 }
1480
1481 #define typedef_BDK_UAAX_PIDR4(a) bdk_uaax_pidr4_t
1482 #define bustype_BDK_UAAX_PIDR4(a) BDK_CSR_TYPE_RSL32b
1483 #define basename_BDK_UAAX_PIDR4(a) "UAAX_PIDR4"
1484 #define device_bar_BDK_UAAX_PIDR4(a) 0x0 /* PF_BAR0 */
1485 #define busnum_BDK_UAAX_PIDR4(a) (a)
1486 #define arguments_BDK_UAAX_PIDR4(a) (a),-1,-1,-1
1487
1488 /**
1489 * Register (RSL32b) uaa#_pidr5
1490 *
1491 * UART Peripheral Identification Register 5
1492 */
1493 union bdk_uaax_pidr5
1494 {
1495 uint32_t u;
1496 struct bdk_uaax_pidr5_s
1497 {
1498 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1499 uint32_t reserved_0_31 : 32;
1500 #else /* Word 0 - Little Endian */
1501 uint32_t reserved_0_31 : 32;
1502 #endif /* Word 0 - End */
1503 } s;
1504 /* struct bdk_uaax_pidr5_s cn; */
1505 };
1506 typedef union bdk_uaax_pidr5 bdk_uaax_pidr5_t;
1507
1508 static inline uint64_t BDK_UAAX_PIDR5(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR5(unsigned long a)1509 static inline uint64_t BDK_UAAX_PIDR5(unsigned long a)
1510 {
1511 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1512 return 0x87e028000fd4ll + 0x1000000ll * ((a) & 0x3);
1513 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1514 return 0x87e028000fd4ll + 0x1000000ll * ((a) & 0x3);
1515 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1516 return 0x87e024000fd4ll + 0x1000000ll * ((a) & 0x1);
1517 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1518 return 0x87e028000fd4ll + 0x1000000ll * ((a) & 0x7);
1519 __bdk_csr_fatal("UAAX_PIDR5", 1, a, 0, 0, 0);
1520 }
1521
1522 #define typedef_BDK_UAAX_PIDR5(a) bdk_uaax_pidr5_t
1523 #define bustype_BDK_UAAX_PIDR5(a) BDK_CSR_TYPE_RSL32b
1524 #define basename_BDK_UAAX_PIDR5(a) "UAAX_PIDR5"
1525 #define device_bar_BDK_UAAX_PIDR5(a) 0x0 /* PF_BAR0 */
1526 #define busnum_BDK_UAAX_PIDR5(a) (a)
1527 #define arguments_BDK_UAAX_PIDR5(a) (a),-1,-1,-1
1528
1529 /**
1530 * Register (RSL32b) uaa#_pidr6
1531 *
1532 * UART Peripheral Identification Register 6
1533 */
1534 union bdk_uaax_pidr6
1535 {
1536 uint32_t u;
1537 struct bdk_uaax_pidr6_s
1538 {
1539 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1540 uint32_t reserved_0_31 : 32;
1541 #else /* Word 0 - Little Endian */
1542 uint32_t reserved_0_31 : 32;
1543 #endif /* Word 0 - End */
1544 } s;
1545 /* struct bdk_uaax_pidr6_s cn; */
1546 };
1547 typedef union bdk_uaax_pidr6 bdk_uaax_pidr6_t;
1548
1549 static inline uint64_t BDK_UAAX_PIDR6(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR6(unsigned long a)1550 static inline uint64_t BDK_UAAX_PIDR6(unsigned long a)
1551 {
1552 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1553 return 0x87e028000fd8ll + 0x1000000ll * ((a) & 0x3);
1554 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1555 return 0x87e028000fd8ll + 0x1000000ll * ((a) & 0x3);
1556 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1557 return 0x87e024000fd8ll + 0x1000000ll * ((a) & 0x1);
1558 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1559 return 0x87e028000fd8ll + 0x1000000ll * ((a) & 0x7);
1560 __bdk_csr_fatal("UAAX_PIDR6", 1, a, 0, 0, 0);
1561 }
1562
1563 #define typedef_BDK_UAAX_PIDR6(a) bdk_uaax_pidr6_t
1564 #define bustype_BDK_UAAX_PIDR6(a) BDK_CSR_TYPE_RSL32b
1565 #define basename_BDK_UAAX_PIDR6(a) "UAAX_PIDR6"
1566 #define device_bar_BDK_UAAX_PIDR6(a) 0x0 /* PF_BAR0 */
1567 #define busnum_BDK_UAAX_PIDR6(a) (a)
1568 #define arguments_BDK_UAAX_PIDR6(a) (a),-1,-1,-1
1569
1570 /**
1571 * Register (RSL32b) uaa#_pidr7
1572 *
1573 * UART Peripheral Identification Register 7
1574 */
1575 union bdk_uaax_pidr7
1576 {
1577 uint32_t u;
1578 struct bdk_uaax_pidr7_s
1579 {
1580 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1581 uint32_t reserved_0_31 : 32;
1582 #else /* Word 0 - Little Endian */
1583 uint32_t reserved_0_31 : 32;
1584 #endif /* Word 0 - End */
1585 } s;
1586 /* struct bdk_uaax_pidr7_s cn; */
1587 };
1588 typedef union bdk_uaax_pidr7 bdk_uaax_pidr7_t;
1589
1590 static inline uint64_t BDK_UAAX_PIDR7(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_PIDR7(unsigned long a)1591 static inline uint64_t BDK_UAAX_PIDR7(unsigned long a)
1592 {
1593 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1594 return 0x87e028000fdcll + 0x1000000ll * ((a) & 0x3);
1595 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1596 return 0x87e028000fdcll + 0x1000000ll * ((a) & 0x3);
1597 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1598 return 0x87e024000fdcll + 0x1000000ll * ((a) & 0x1);
1599 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1600 return 0x87e028000fdcll + 0x1000000ll * ((a) & 0x7);
1601 __bdk_csr_fatal("UAAX_PIDR7", 1, a, 0, 0, 0);
1602 }
1603
1604 #define typedef_BDK_UAAX_PIDR7(a) bdk_uaax_pidr7_t
1605 #define bustype_BDK_UAAX_PIDR7(a) BDK_CSR_TYPE_RSL32b
1606 #define basename_BDK_UAAX_PIDR7(a) "UAAX_PIDR7"
1607 #define device_bar_BDK_UAAX_PIDR7(a) 0x0 /* PF_BAR0 */
1608 #define busnum_BDK_UAAX_PIDR7(a) (a)
1609 #define arguments_BDK_UAAX_PIDR7(a) (a),-1,-1,-1
1610
1611 /**
1612 * Register (RSL) uaa#_redirect
1613 *
1614 * UART REDIRECT Control Register
1615 */
1616 union bdk_uaax_redirect
1617 {
1618 uint64_t u;
1619 struct bdk_uaax_redirect_s
1620 {
1621 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1622 uint64_t reserved_4_63 : 60;
1623 uint64_t in_ena : 1; /**< [ 3: 3](SR/W) 0 = UAA receive and modem control inputs are from hard-assigned pins or GPIO virtual pins.
1624 1 = UAA receive and modem control come from the UAA specified by [IN_SEL]. */
1625 uint64_t in_sel : 3; /**< [ 2: 0](SR/W) 0x0 = Inputs from UAA0.
1626 0x1 = Inputs from UAA1.
1627 0x2 = Inputs from UAA2.
1628 0x3 = Inputs from UAA3.
1629 0x4 = Inputs from UAA4.
1630 0x5 = Inputs from UAA5.
1631 0x6 = Inputs from UAA6.
1632 0x7 = Inputs from UAA7. */
1633 #else /* Word 0 - Little Endian */
1634 uint64_t in_sel : 3; /**< [ 2: 0](SR/W) 0x0 = Inputs from UAA0.
1635 0x1 = Inputs from UAA1.
1636 0x2 = Inputs from UAA2.
1637 0x3 = Inputs from UAA3.
1638 0x4 = Inputs from UAA4.
1639 0x5 = Inputs from UAA5.
1640 0x6 = Inputs from UAA6.
1641 0x7 = Inputs from UAA7. */
1642 uint64_t in_ena : 1; /**< [ 3: 3](SR/W) 0 = UAA receive and modem control inputs are from hard-assigned pins or GPIO virtual pins.
1643 1 = UAA receive and modem control come from the UAA specified by [IN_SEL]. */
1644 uint64_t reserved_4_63 : 60;
1645 #endif /* Word 0 - End */
1646 } s;
1647 /* struct bdk_uaax_redirect_s cn; */
1648 };
1649 typedef union bdk_uaax_redirect bdk_uaax_redirect_t;
1650
1651 static inline uint64_t BDK_UAAX_REDIRECT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_REDIRECT(unsigned long a)1652 static inline uint64_t BDK_UAAX_REDIRECT(unsigned long a)
1653 {
1654 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1655 return 0x87e028001020ll + 0x1000000ll * ((a) & 0x7);
1656 __bdk_csr_fatal("UAAX_REDIRECT", 1, a, 0, 0, 0);
1657 }
1658
1659 #define typedef_BDK_UAAX_REDIRECT(a) bdk_uaax_redirect_t
1660 #define bustype_BDK_UAAX_REDIRECT(a) BDK_CSR_TYPE_RSL
1661 #define basename_BDK_UAAX_REDIRECT(a) "UAAX_REDIRECT"
1662 #define device_bar_BDK_UAAX_REDIRECT(a) 0x0 /* PF_BAR0 */
1663 #define busnum_BDK_UAAX_REDIRECT(a) (a)
1664 #define arguments_BDK_UAAX_REDIRECT(a) (a),-1,-1,-1
1665
1666 /**
1667 * Register (RSL32b) uaa#_ris
1668 *
1669 * UART Raw Interrupt Status Register
1670 * Indicates state of interrupts before masking.
1671 */
1672 union bdk_uaax_ris
1673 {
1674 uint32_t u;
1675 struct bdk_uaax_ris_s
1676 {
1677 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1678 uint32_t reserved_11_31 : 21;
1679 uint32_t oeris : 1; /**< [ 10: 10](RO/H) Overrun error interrupt status. */
1680 uint32_t beris : 1; /**< [ 9: 9](RO/H) Break error interrupt status. */
1681 uint32_t peris : 1; /**< [ 8: 8](RO/H) Parity error interrupt status. */
1682 uint32_t feris : 1; /**< [ 7: 7](RO/H) Framing error interrupt status. */
1683 uint32_t rtris : 1; /**< [ 6: 6](RO/H) Receive timeout interrupt status. */
1684 uint32_t txris : 1; /**< [ 5: 5](RO/H) Transmit interrupt status. */
1685 uint32_t rxris : 1; /**< [ 4: 4](RO/H) Receive interrupt status. */
1686 uint32_t dsrrmis : 1; /**< [ 3: 3](RO/H) DSR modem interrupt status. */
1687 uint32_t dcdrmis : 1; /**< [ 2: 2](RO/H) DCD modem interrupt status. */
1688 uint32_t ctsrmis : 1; /**< [ 1: 1](RO/H) CTS modem interrupt status. */
1689 uint32_t rirmis : 1; /**< [ 0: 0](RO/H) Ring indicator interrupt status. Not implemented. */
1690 #else /* Word 0 - Little Endian */
1691 uint32_t rirmis : 1; /**< [ 0: 0](RO/H) Ring indicator interrupt status. Not implemented. */
1692 uint32_t ctsrmis : 1; /**< [ 1: 1](RO/H) CTS modem interrupt status. */
1693 uint32_t dcdrmis : 1; /**< [ 2: 2](RO/H) DCD modem interrupt status. */
1694 uint32_t dsrrmis : 1; /**< [ 3: 3](RO/H) DSR modem interrupt status. */
1695 uint32_t rxris : 1; /**< [ 4: 4](RO/H) Receive interrupt status. */
1696 uint32_t txris : 1; /**< [ 5: 5](RO/H) Transmit interrupt status. */
1697 uint32_t rtris : 1; /**< [ 6: 6](RO/H) Receive timeout interrupt status. */
1698 uint32_t feris : 1; /**< [ 7: 7](RO/H) Framing error interrupt status. */
1699 uint32_t peris : 1; /**< [ 8: 8](RO/H) Parity error interrupt status. */
1700 uint32_t beris : 1; /**< [ 9: 9](RO/H) Break error interrupt status. */
1701 uint32_t oeris : 1; /**< [ 10: 10](RO/H) Overrun error interrupt status. */
1702 uint32_t reserved_11_31 : 21;
1703 #endif /* Word 0 - End */
1704 } s;
1705 /* struct bdk_uaax_ris_s cn; */
1706 };
1707 typedef union bdk_uaax_ris bdk_uaax_ris_t;
1708
1709 static inline uint64_t BDK_UAAX_RIS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_RIS(unsigned long a)1710 static inline uint64_t BDK_UAAX_RIS(unsigned long a)
1711 {
1712 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1713 return 0x87e02800003cll + 0x1000000ll * ((a) & 0x3);
1714 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1715 return 0x87e02800003cll + 0x1000000ll * ((a) & 0x3);
1716 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1717 return 0x87e02400003cll + 0x1000000ll * ((a) & 0x1);
1718 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1719 return 0x87e02800003cll + 0x1000000ll * ((a) & 0x7);
1720 __bdk_csr_fatal("UAAX_RIS", 1, a, 0, 0, 0);
1721 }
1722
1723 #define typedef_BDK_UAAX_RIS(a) bdk_uaax_ris_t
1724 #define bustype_BDK_UAAX_RIS(a) BDK_CSR_TYPE_RSL32b
1725 #define basename_BDK_UAAX_RIS(a) "UAAX_RIS"
1726 #define device_bar_BDK_UAAX_RIS(a) 0x0 /* PF_BAR0 */
1727 #define busnum_BDK_UAAX_RIS(a) (a)
1728 #define arguments_BDK_UAAX_RIS(a) (a),-1,-1,-1
1729
1730 /**
1731 * Register (RSL32b) uaa#_rsr_ecr
1732 *
1733 * UART Receive Status Register/Error Clear Register
1734 */
1735 union bdk_uaax_rsr_ecr
1736 {
1737 uint32_t u;
1738 struct bdk_uaax_rsr_ecr_s
1739 {
1740 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1741 uint32_t reserved_4_31 : 28;
1742 uint32_t oe : 1; /**< [ 3: 3](R/W1/H) Overrun error. Write of any value clears. */
1743 uint32_t be : 1; /**< [ 2: 2](R/W1/H) Break error. Associated with the character at the top of the FIFO; only one 0 character is
1744 loaded. The next character is only enabled after the receive data goes to 1. Write of any
1745 value clears. */
1746 uint32_t pe : 1; /**< [ 1: 1](R/W1/H) Parity error. Associated with character at top of the FIFO. Write of any value clears. */
1747 uint32_t fe : 1; /**< [ 0: 0](R/W1/H) Framing error. Associated with character at top of the FIFO. Write of any value clears. */
1748 #else /* Word 0 - Little Endian */
1749 uint32_t fe : 1; /**< [ 0: 0](R/W1/H) Framing error. Associated with character at top of the FIFO. Write of any value clears. */
1750 uint32_t pe : 1; /**< [ 1: 1](R/W1/H) Parity error. Associated with character at top of the FIFO. Write of any value clears. */
1751 uint32_t be : 1; /**< [ 2: 2](R/W1/H) Break error. Associated with the character at the top of the FIFO; only one 0 character is
1752 loaded. The next character is only enabled after the receive data goes to 1. Write of any
1753 value clears. */
1754 uint32_t oe : 1; /**< [ 3: 3](R/W1/H) Overrun error. Write of any value clears. */
1755 uint32_t reserved_4_31 : 28;
1756 #endif /* Word 0 - End */
1757 } s;
1758 /* struct bdk_uaax_rsr_ecr_s cn; */
1759 };
1760 typedef union bdk_uaax_rsr_ecr bdk_uaax_rsr_ecr_t;
1761
1762 static inline uint64_t BDK_UAAX_RSR_ECR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_RSR_ECR(unsigned long a)1763 static inline uint64_t BDK_UAAX_RSR_ECR(unsigned long a)
1764 {
1765 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1766 return 0x87e028000004ll + 0x1000000ll * ((a) & 0x3);
1767 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1768 return 0x87e028000004ll + 0x1000000ll * ((a) & 0x3);
1769 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1770 return 0x87e024000004ll + 0x1000000ll * ((a) & 0x1);
1771 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1772 return 0x87e028000004ll + 0x1000000ll * ((a) & 0x7);
1773 __bdk_csr_fatal("UAAX_RSR_ECR", 1, a, 0, 0, 0);
1774 }
1775
1776 #define typedef_BDK_UAAX_RSR_ECR(a) bdk_uaax_rsr_ecr_t
1777 #define bustype_BDK_UAAX_RSR_ECR(a) BDK_CSR_TYPE_RSL32b
1778 #define basename_BDK_UAAX_RSR_ECR(a) "UAAX_RSR_ECR"
1779 #define device_bar_BDK_UAAX_RSR_ECR(a) 0x0 /* PF_BAR0 */
1780 #define busnum_BDK_UAAX_RSR_ECR(a) (a)
1781 #define arguments_BDK_UAAX_RSR_ECR(a) (a),-1,-1,-1
1782
1783 /**
1784 * Register (RSL) uaa#_uctl_csclk_active_pc
1785 *
1786 * UAA UCTL Conditional Clock Counter Register
1787 * This register counts conditional clocks, for power analysis.
1788 * Reset by RSL reset.
1789 */
1790 union bdk_uaax_uctl_csclk_active_pc
1791 {
1792 uint64_t u;
1793 struct bdk_uaax_uctl_csclk_active_pc_s
1794 {
1795 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1796 uint64_t count : 64; /**< [ 63: 0](R/W/H) Counts conditional-clock active cycles since reset. */
1797 #else /* Word 0 - Little Endian */
1798 uint64_t count : 64; /**< [ 63: 0](R/W/H) Counts conditional-clock active cycles since reset. */
1799 #endif /* Word 0 - End */
1800 } s;
1801 /* struct bdk_uaax_uctl_csclk_active_pc_s cn; */
1802 };
1803 typedef union bdk_uaax_uctl_csclk_active_pc bdk_uaax_uctl_csclk_active_pc_t;
1804
1805 static inline uint64_t BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(unsigned long a)1806 static inline uint64_t BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(unsigned long a)
1807 {
1808 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1809 return 0x87e028001018ll + 0x1000000ll * ((a) & 0x7);
1810 __bdk_csr_fatal("UAAX_UCTL_CSCLK_ACTIVE_PC", 1, a, 0, 0, 0);
1811 }
1812
1813 #define typedef_BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(a) bdk_uaax_uctl_csclk_active_pc_t
1814 #define bustype_BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(a) BDK_CSR_TYPE_RSL
1815 #define basename_BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(a) "UAAX_UCTL_CSCLK_ACTIVE_PC"
1816 #define device_bar_BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(a) 0x0 /* PF_BAR0 */
1817 #define busnum_BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(a) (a)
1818 #define arguments_BDK_UAAX_UCTL_CSCLK_ACTIVE_PC(a) (a),-1,-1,-1
1819
1820 /**
1821 * Register (RSL) uaa#_uctl_ctl
1822 *
1823 * UART UCTL Control Register
1824 */
1825 union bdk_uaax_uctl_ctl
1826 {
1827 uint64_t u;
1828 struct bdk_uaax_uctl_ctl_s
1829 {
1830 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1831 uint64_t reserved_31_63 : 33;
1832 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) UART controller clock enable. When set to 1, the UART controller clock is generated. This
1833 also enables access to UCTL registers 0x30-0xF8. */
1834 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the UART controller clock divider.
1835 0 = Use the divided coprocessor clock from the [H_CLKDIV_SEL] divider.
1836 1 = Use the bypass clock from the GPIO pins.
1837
1838 This signal is just a multiplexer-select signal; it does not enable the UART
1839 controller and APB clock. Software must still set [H_CLK_EN]
1840 separately. [H_CLK_BYP_SEL] select should not be changed unless [H_CLK_EN] is
1841 disabled. The bypass clock can be selected and running even if the UART
1842 controller clock dividers are not running.
1843
1844 Internal:
1845 Generally bypass is only used for scan purposes. */
1846 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) UART controller clock divider reset. Divided clocks are not generated while the divider is
1847 being reset.
1848 This also resets the suspend-clock divider. */
1849 uint64_t reserved_27 : 1;
1850 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) The UARTCLK and APB CLK frequency select.
1851 The divider values are the following:
1852 0x0 = Divide by 1.
1853 0x1 = Divide by 2.
1854 0x2 = Divide by 4.
1855 0x3 = Divide by 6.
1856 0x4 = Divide by 8.
1857 0x5 = Divide by 16.
1858 0x6 = Divide by 24.
1859 0x7 = Divide by 32.
1860
1861 The max and min frequency of the UARTCLK is determined by the following:
1862 _ f_uartclk(min) \>= 16 * baud_rate(max)
1863 _ f_uartclk(max) \<= 16 * 65535 * baud_rate(min) */
1864 uint64_t reserved_5_23 : 19;
1865 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the UCTL interface clock (coprocessor clock).
1866 This enables the UCTL registers starting from 0x30 via the RSL bus. */
1867 uint64_t reserved_2_3 : 2;
1868 uint64_t uaa_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAA controller; active-high.
1869 Internal:
1870 Note that soft-resetting the UAHC while it is active may cause violations of RSL
1871 protocols. */
1872 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
1873 Resets UCTL RSL registers 0x30-0xF8.
1874 Does not reset UCTL RSL registers 0x0-0x28.
1875 UCTL RSL registers starting from 0x30 can be accessed only after the UART controller clock
1876 is active and [UCTL_RST] is deasserted.
1877
1878 Internal:
1879 Note that soft-resetting the UCTL while it is active may cause violations of
1880 RSL and CIB protocols. */
1881 #else /* Word 0 - Little Endian */
1882 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
1883 Resets UCTL RSL registers 0x30-0xF8.
1884 Does not reset UCTL RSL registers 0x0-0x28.
1885 UCTL RSL registers starting from 0x30 can be accessed only after the UART controller clock
1886 is active and [UCTL_RST] is deasserted.
1887
1888 Internal:
1889 Note that soft-resetting the UCTL while it is active may cause violations of
1890 RSL and CIB protocols. */
1891 uint64_t uaa_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAA controller; active-high.
1892 Internal:
1893 Note that soft-resetting the UAHC while it is active may cause violations of RSL
1894 protocols. */
1895 uint64_t reserved_2_3 : 2;
1896 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the UCTL interface clock (coprocessor clock).
1897 This enables the UCTL registers starting from 0x30 via the RSL bus. */
1898 uint64_t reserved_5_23 : 19;
1899 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) The UARTCLK and APB CLK frequency select.
1900 The divider values are the following:
1901 0x0 = Divide by 1.
1902 0x1 = Divide by 2.
1903 0x2 = Divide by 4.
1904 0x3 = Divide by 6.
1905 0x4 = Divide by 8.
1906 0x5 = Divide by 16.
1907 0x6 = Divide by 24.
1908 0x7 = Divide by 32.
1909
1910 The max and min frequency of the UARTCLK is determined by the following:
1911 _ f_uartclk(min) \>= 16 * baud_rate(max)
1912 _ f_uartclk(max) \<= 16 * 65535 * baud_rate(min) */
1913 uint64_t reserved_27 : 1;
1914 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) UART controller clock divider reset. Divided clocks are not generated while the divider is
1915 being reset.
1916 This also resets the suspend-clock divider. */
1917 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the UART controller clock divider.
1918 0 = Use the divided coprocessor clock from the [H_CLKDIV_SEL] divider.
1919 1 = Use the bypass clock from the GPIO pins.
1920
1921 This signal is just a multiplexer-select signal; it does not enable the UART
1922 controller and APB clock. Software must still set [H_CLK_EN]
1923 separately. [H_CLK_BYP_SEL] select should not be changed unless [H_CLK_EN] is
1924 disabled. The bypass clock can be selected and running even if the UART
1925 controller clock dividers are not running.
1926
1927 Internal:
1928 Generally bypass is only used for scan purposes. */
1929 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) UART controller clock enable. When set to 1, the UART controller clock is generated. This
1930 also enables access to UCTL registers 0x30-0xF8. */
1931 uint64_t reserved_31_63 : 33;
1932 #endif /* Word 0 - End */
1933 } s;
1934 /* struct bdk_uaax_uctl_ctl_s cn8; */
1935 struct bdk_uaax_uctl_ctl_cn9
1936 {
1937 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1938 uint64_t reserved_31_63 : 33;
1939 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) UART controller clock enable. When set to 1, the UART controller clock is generated. This
1940 also enables access to UCTL registers 0x30-0xF8. */
1941 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the UART controller clock divider.
1942 0 = Use the divided coprocessor clock from the [H_CLKDIV_SEL] divider.
1943 1 = Use the bypass clock from the GPIO pins.
1944
1945 This signal is just a multiplexer-select signal; it does not enable the UART
1946 controller and APB clock. Software must still set [H_CLK_EN]
1947 separately. [H_CLK_BYP_SEL] select should not be changed unless [H_CLK_EN] is
1948 disabled. The bypass clock can be selected and running even if the UART
1949 controller clock dividers are not running.
1950
1951 Internal:
1952 Generally bypass is only used for scan purposes. */
1953 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) UART controller clock divider reset. Divided clocks are not generated while the divider is
1954 being reset.
1955 This also resets the suspend-clock divider. */
1956 uint64_t reserved_27 : 1;
1957 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) The UARTCLK and APB CLK frequency select.
1958 The divider values are the following:
1959 0x0 = Divide by 1 (100 MHz).
1960 0x1 = Divide by 2 (50 MHz).
1961 0x2 = Divide by 4 (25 MHz).
1962 0x3 = Divide by 6 (16.66 MHz).
1963 0x4 = Divide by 8 (12.50 MHz).
1964 0x5 = Divide by 16 (6.25 MHz).
1965 0x6 = Divide by 24 (4.167 MHz).
1966 0x7 = Divide by 32 (3.125 MHz).
1967
1968 The max and min frequency of the UARTCLK is determined by the following:
1969 _ f_uartclk(min) \>= 16 * baud_rate(max)
1970 _ f_uartclk(max) \<= 16 * 65535 * baud_rate(min) */
1971 uint64_t reserved_5_23 : 19;
1972 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the UCTL interface clock (coprocessor clock).
1973 This enables the UCTL registers starting from 0x30 via the RSL bus. */
1974 uint64_t reserved_2_3 : 2;
1975 uint64_t uaa_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAA controller; active-high.
1976 Internal:
1977 Note that soft-resetting the UAHC while it is active may cause violations of RSL
1978 protocols. */
1979 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
1980 Resets UCTL RSL registers 0x30-0xF8.
1981 Does not reset UCTL RSL registers 0x0-0x28.
1982 UCTL RSL registers starting from 0x30 can be accessed only after the UART controller clock
1983 is active and [UCTL_RST] is deasserted.
1984
1985 Internal:
1986 Note that soft-resetting the UCTL while it is active may cause violations of
1987 RSL and CIB protocols. */
1988 #else /* Word 0 - Little Endian */
1989 uint64_t uctl_rst : 1; /**< [ 0: 0](R/W) Software reset; resets UCTL; active-high.
1990 Resets UCTL RSL registers 0x30-0xF8.
1991 Does not reset UCTL RSL registers 0x0-0x28.
1992 UCTL RSL registers starting from 0x30 can be accessed only after the UART controller clock
1993 is active and [UCTL_RST] is deasserted.
1994
1995 Internal:
1996 Note that soft-resetting the UCTL while it is active may cause violations of
1997 RSL and CIB protocols. */
1998 uint64_t uaa_rst : 1; /**< [ 1: 1](R/W) Software reset; resets UAA controller; active-high.
1999 Internal:
2000 Note that soft-resetting the UAHC while it is active may cause violations of RSL
2001 protocols. */
2002 uint64_t reserved_2_3 : 2;
2003 uint64_t csclk_en : 1; /**< [ 4: 4](R/W) Turns on the UCTL interface clock (coprocessor clock).
2004 This enables the UCTL registers starting from 0x30 via the RSL bus. */
2005 uint64_t reserved_5_23 : 19;
2006 uint64_t h_clkdiv_sel : 3; /**< [ 26: 24](R/W) The UARTCLK and APB CLK frequency select.
2007 The divider values are the following:
2008 0x0 = Divide by 1 (100 MHz).
2009 0x1 = Divide by 2 (50 MHz).
2010 0x2 = Divide by 4 (25 MHz).
2011 0x3 = Divide by 6 (16.66 MHz).
2012 0x4 = Divide by 8 (12.50 MHz).
2013 0x5 = Divide by 16 (6.25 MHz).
2014 0x6 = Divide by 24 (4.167 MHz).
2015 0x7 = Divide by 32 (3.125 MHz).
2016
2017 The max and min frequency of the UARTCLK is determined by the following:
2018 _ f_uartclk(min) \>= 16 * baud_rate(max)
2019 _ f_uartclk(max) \<= 16 * 65535 * baud_rate(min) */
2020 uint64_t reserved_27 : 1;
2021 uint64_t h_clkdiv_rst : 1; /**< [ 28: 28](R/W) UART controller clock divider reset. Divided clocks are not generated while the divider is
2022 being reset.
2023 This also resets the suspend-clock divider. */
2024 uint64_t h_clk_byp_sel : 1; /**< [ 29: 29](R/W) Select the bypass input to the UART controller clock divider.
2025 0 = Use the divided coprocessor clock from the [H_CLKDIV_SEL] divider.
2026 1 = Use the bypass clock from the GPIO pins.
2027
2028 This signal is just a multiplexer-select signal; it does not enable the UART
2029 controller and APB clock. Software must still set [H_CLK_EN]
2030 separately. [H_CLK_BYP_SEL] select should not be changed unless [H_CLK_EN] is
2031 disabled. The bypass clock can be selected and running even if the UART
2032 controller clock dividers are not running.
2033
2034 Internal:
2035 Generally bypass is only used for scan purposes. */
2036 uint64_t h_clk_en : 1; /**< [ 30: 30](R/W) UART controller clock enable. When set to 1, the UART controller clock is generated. This
2037 also enables access to UCTL registers 0x30-0xF8. */
2038 uint64_t reserved_31_63 : 33;
2039 #endif /* Word 0 - End */
2040 } cn9;
2041 };
2042 typedef union bdk_uaax_uctl_ctl bdk_uaax_uctl_ctl_t;
2043
2044 static inline uint64_t BDK_UAAX_UCTL_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_UCTL_CTL(unsigned long a)2045 static inline uint64_t BDK_UAAX_UCTL_CTL(unsigned long a)
2046 {
2047 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
2048 return 0x87e028001000ll + 0x1000000ll * ((a) & 0x3);
2049 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2050 return 0x87e028001000ll + 0x1000000ll * ((a) & 0x3);
2051 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
2052 return 0x87e024001000ll + 0x1000000ll * ((a) & 0x1);
2053 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
2054 return 0x87e028001000ll + 0x1000000ll * ((a) & 0x7);
2055 __bdk_csr_fatal("UAAX_UCTL_CTL", 1, a, 0, 0, 0);
2056 }
2057
2058 #define typedef_BDK_UAAX_UCTL_CTL(a) bdk_uaax_uctl_ctl_t
2059 #define bustype_BDK_UAAX_UCTL_CTL(a) BDK_CSR_TYPE_RSL
2060 #define basename_BDK_UAAX_UCTL_CTL(a) "UAAX_UCTL_CTL"
2061 #define device_bar_BDK_UAAX_UCTL_CTL(a) 0x0 /* PF_BAR0 */
2062 #define busnum_BDK_UAAX_UCTL_CTL(a) (a)
2063 #define arguments_BDK_UAAX_UCTL_CTL(a) (a),-1,-1,-1
2064
2065 /**
2066 * Register (RSL) uaa#_uctl_spare0
2067 *
2068 * UART UCTL Spare Register 0
2069 * This register is a spare register. This register can be reset by NCB reset.
2070 */
2071 union bdk_uaax_uctl_spare0
2072 {
2073 uint64_t u;
2074 struct bdk_uaax_uctl_spare0_s
2075 {
2076 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2077 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
2078 #else /* Word 0 - Little Endian */
2079 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
2080 #endif /* Word 0 - End */
2081 } s;
2082 /* struct bdk_uaax_uctl_spare0_s cn; */
2083 };
2084 typedef union bdk_uaax_uctl_spare0 bdk_uaax_uctl_spare0_t;
2085
2086 static inline uint64_t BDK_UAAX_UCTL_SPARE0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_UCTL_SPARE0(unsigned long a)2087 static inline uint64_t BDK_UAAX_UCTL_SPARE0(unsigned long a)
2088 {
2089 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
2090 return 0x87e028001010ll + 0x1000000ll * ((a) & 0x3);
2091 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2092 return 0x87e028001010ll + 0x1000000ll * ((a) & 0x3);
2093 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
2094 return 0x87e024001010ll + 0x1000000ll * ((a) & 0x1);
2095 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
2096 return 0x87e028001010ll + 0x1000000ll * ((a) & 0x7);
2097 __bdk_csr_fatal("UAAX_UCTL_SPARE0", 1, a, 0, 0, 0);
2098 }
2099
2100 #define typedef_BDK_UAAX_UCTL_SPARE0(a) bdk_uaax_uctl_spare0_t
2101 #define bustype_BDK_UAAX_UCTL_SPARE0(a) BDK_CSR_TYPE_RSL
2102 #define basename_BDK_UAAX_UCTL_SPARE0(a) "UAAX_UCTL_SPARE0"
2103 #define device_bar_BDK_UAAX_UCTL_SPARE0(a) 0x0 /* PF_BAR0 */
2104 #define busnum_BDK_UAAX_UCTL_SPARE0(a) (a)
2105 #define arguments_BDK_UAAX_UCTL_SPARE0(a) (a),-1,-1,-1
2106
2107 /**
2108 * Register (RSL) uaa#_uctl_spare1
2109 *
2110 * UART UCTL Spare Register 1
2111 * This register is a spare register. This register can be reset by NCB reset.
2112 */
2113 union bdk_uaax_uctl_spare1
2114 {
2115 uint64_t u;
2116 struct bdk_uaax_uctl_spare1_s
2117 {
2118 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2119 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
2120 #else /* Word 0 - Little Endian */
2121 uint64_t spare : 64; /**< [ 63: 0](R/W) Spare. */
2122 #endif /* Word 0 - End */
2123 } s;
2124 /* struct bdk_uaax_uctl_spare1_s cn; */
2125 };
2126 typedef union bdk_uaax_uctl_spare1 bdk_uaax_uctl_spare1_t;
2127
2128 static inline uint64_t BDK_UAAX_UCTL_SPARE1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_UAAX_UCTL_SPARE1(unsigned long a)2129 static inline uint64_t BDK_UAAX_UCTL_SPARE1(unsigned long a)
2130 {
2131 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
2132 return 0x87e0280010f8ll + 0x1000000ll * ((a) & 0x3);
2133 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2134 return 0x87e0280010f8ll + 0x1000000ll * ((a) & 0x3);
2135 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
2136 return 0x87e0240010f8ll + 0x1000000ll * ((a) & 0x1);
2137 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
2138 return 0x87e0280010f8ll + 0x1000000ll * ((a) & 0x7);
2139 __bdk_csr_fatal("UAAX_UCTL_SPARE1", 1, a, 0, 0, 0);
2140 }
2141
2142 #define typedef_BDK_UAAX_UCTL_SPARE1(a) bdk_uaax_uctl_spare1_t
2143 #define bustype_BDK_UAAX_UCTL_SPARE1(a) BDK_CSR_TYPE_RSL
2144 #define basename_BDK_UAAX_UCTL_SPARE1(a) "UAAX_UCTL_SPARE1"
2145 #define device_bar_BDK_UAAX_UCTL_SPARE1(a) 0x0 /* PF_BAR0 */
2146 #define busnum_BDK_UAAX_UCTL_SPARE1(a) (a)
2147 #define arguments_BDK_UAAX_UCTL_SPARE1(a) (a),-1,-1,-1
2148
2149 #endif /* __BDK_CSRS_UAA_H__ */
2150