1 /*===================== begin_copyright_notice ================================== 2 3 Copyright (c) 2017-2019, Intel Corporation 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included 13 in all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_hcp_g12_X.h 26 //! \brief Defines functions for constructing Vdbox HCP commands on Gen11-based platforms 27 //! 28 29 #ifndef __MHW_VDBOX_HCP_G12_X_H__ 30 #define __MHW_VDBOX_HCP_G12_X_H__ 31 32 #include "mhw_vdbox_hcp_generic.h" 33 #include "mhw_vdbox_hcp_hwcmd_g12_X.h" 34 #include "mhw_vdbox_g12_X.h" 35 #include "codec_def_decode_hevc.h" 36 37 //definition for row store cache offset on GEN12 38 #define VDENCHEVC_RSC_OFFSET_C420OR422_DXX_LCU32OR64_4K_G12 1824 39 #define VDENCHEVC_RSC_OFFSET_C420OR422_DXX_LCU32OR64_8K_G12 2304 40 #define VDENCHEVC_RSC_OFFSET_C444_D8_LCU32OR64_4K_G12 1568 41 #define VDENCHEVC_RSC_OFFSET_C444_D8_LCU32OR64_8K_G12 2112 42 #define VDENCHEVC_RSC_OFFSET_C444_D10_LCU32OR64_4K_G12 2336 43 #define VDENCHEVC_RSC_OFFSET_C444_D10_LCU32OR64_8K_G12 1600 44 #define VDENCHEVC_RSC_OFFSET_C444_D12_LCU32OR64_4K_G12 2336 45 #define VDENCHEVC_RSC_OFFSET_C444_D12_LCU32OR64_8K_G12 1600 46 47 #define HEVCDAT_RSC_OFFSET_CXXX_DXX_LCUXX_XX_G12 0 48 49 #define HEVCDF_RSC_OFFSET_C420OR422_DXX_LCUXX_4K_G12 256 50 #define HEVCDF_RSC_OFFSET_C420OR422_DXX_LCU16_8K_G12 512 51 #define HEVCDF_RSC_OFFSET_C420OR422_DXX_LCU32OR64_8K_G12 256 52 #define HEVCDF_RSC_OFFSET_C444_D8_LCU16_4K_G12 256 53 #define HEVCDF_RSC_OFFSET_C444_D8_LCU16_8K_G12 512 54 #define HEVCDF_RSC_OFFSET_C444_D10_LCU16_4K_G12 256 55 #define HEVCDF_RSC_OFFSET_C444_D12_LCU16_4K_G12 256 56 #define HEVCDF_RSC_OFFSET_C444_D8_LCU32OR64_4K_G12 256 57 #define HEVCDF_RSC_OFFSET_C444_D8_LCU32OR64_8K_G12 512 58 #define HEVCDF_RSC_OFFSET_C444_D10_LCU32OR64_4K_G12 256 59 #define HEVCDF_RSC_OFFSET_C444_D12_LCU32OR64_4K_G12 128 60 61 #define HEVCSAO_RSC_OFFSET_C420OR422_DXX_LCUXX_4K_G12 1280 62 #define HEVCSAO_RSC_OFFSET_C444_D8_LCU16_4K_G12 1024 63 #define HEVCSAO_RSC_OFFSET_C444_D10_LCU16_4K_G12 1792 64 #define HEVCSAO_RSC_OFFSET_C444_D10_LCU16_8K_G12 512 65 #define HEVCSAO_RSC_OFFSET_C444_D12_LCU16_4K_G12 1792 66 #define HEVCSAO_RSC_OFFSET_C444_D12_LCU16_8K_G12 256 67 #define HEVCSAO_RSC_OFFSET_C444_D8_LCU32OR64_4K_G12 1024 68 #define HEVCSAO_RSC_OFFSET_C444_D10_LCU32OR64_4K_G12 1792 69 #define HEVCSAO_RSC_OFFSET_C444_D10_LCU32OR64_8K_G12 512 70 #define HEVCSAO_RSC_OFFSET_C444_D12_LCU32OR64_4K_G12 1664 71 #define HEVCSAO_RSC_OFFSET_C444_D12_LCU32OR64_8K_G12 256 72 73 #define HEVCHSAO_RSC_OFFSET_C420OR422_DXX_LCU16_4K_G12 2048 74 #define HEVCHSAO_RSC_OFFSET_C420OR422_DXX_LCU32OR64_4K_G12 1792 75 #define HEVCHSAO_RSC_OFFSET_C444_D8_LCU16_4K_G12 1792 76 #define HEVCHSAO_RSC_OFFSET_C444_D8_LCU16_8K_G12 2048 77 #define HEVCHSAO_RSC_OFFSET_C444_D10_LCU16_8K_G12 2048 78 #define HEVCHSAO_RSC_OFFSET_C444_D12_LCU16_8K_G12 1792 79 #define HEVCHSAO_RSC_OFFSET_C444_D8_LCU32OR64_4K_G12 1536 80 #define HEVCHSAO_RSC_OFFSET_C444_D8_LCU32OR64_8K_G12 2048 81 #define HEVCHSAO_RSC_OFFSET_C444_D10_LCU32OR64_4K_G12 2304 82 #define HEVCHSAO_RSC_OFFSET_C444_D10_LCU32OR64_8K_G12 1536 83 #define HEVCHSAO_RSC_OFFSET_C444_D12_LCU32OR64_4K_G12 2304 84 #define HEVCHSAO_RSC_OFFSET_C444_D12_LCU32OR64_8K_G12 1536 85 86 // TGL rowstore Cache Values 87 #define VP9DATROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 32 88 #define VP9DATROWSTORE_BASEADDRESS_128 128 89 #define VP9DFROWSTORE_BASEADDRESS_64 64 90 #define VP9DFROWSTORE_BASEADDRESS_192 192 91 92 #define MHW_HCP_WORST_CASE_LCU_CU_TU_INFO (26 * MHW_CACHELINE_SIZE) // 18+4+4 93 #define MHW_HCP_WORST_CASE_LCU_CU_TU_INFO_REXT (35 * MHW_CACHELINE_SIZE) // 27+4+4 94 95 #define MHW_HCP_WORST_CASE_CU_TU_INFO (4 * MHW_CACHELINE_SIZE) // 2+1+1 96 #define MHW_HCP_WORST_CASE_CU_TU_INFO_REXT (6 * MHW_CACHELINE_SIZE) // 4+1+1 97 98 struct HcpPakObjectG12 99 { 100 // DW0 101 struct 102 { 103 uint32_t DwordLength : 16; 104 uint32_t SubOp : 7; 105 uint32_t Opcode : 6; 106 uint32_t Type : 3; 107 } DW0; 108 109 //DW1 110 struct 111 { 112 uint32_t Split_flag_level2_level1part0 : 4; 113 uint32_t Split_flag_level2_level1part1 : 4; 114 uint32_t Split_flag_level2_level1part2 : 4; 115 uint32_t Split_flag_level2_level1part3 : 4; 116 uint32_t Split_flag_level1 : 4; 117 uint32_t Split_flag_level0 : 1; 118 uint32_t Reserved21_23 : 3; 119 uint32_t CU_count_minus1 : 6; 120 uint32_t LastCtbOfTileFlag : 1; 121 uint32_t LastCtbOfSliceFlag : 1; 122 } DW1; 123 124 //DW2 125 struct 126 { 127 uint32_t Current_LCU_X_Addr : 16; 128 uint32_t Current_LCU_Y_Addr : 16; 129 } DW2; 130 131 //DW3 132 struct 133 { 134 uint32_t Estimated_LCU_Size_In_Bytes : 32; 135 } DW3; 136 137 //DW4 138 struct 139 { 140 uint32_t SSE_ClassID_32x32_0 : 4; 141 uint32_t SSE_ClassID_32x32_1 : 4; 142 uint32_t SSE_ClassID_32x32_2 : 4; 143 uint32_t SSE_ClassID_32x32_3 : 4; 144 uint32_t LCUForceZeroCoeff : 1; 145 uint32_t Disable_SAO_On_LCU_Flag : 1; 146 uint32_t Reserve18_31 : 14; 147 } DW4; 148 149 uint32_t DW5; 150 uint32_t DW6; 151 uint32_t DW7; 152 }; 153 154 // CU Record structure 155 struct EncodeHevcCuDataG12 156 { 157 //DWORD 0 158 union 159 { 160 struct 161 { 162 uint32_t DW0_L0_Mv0x : MOS_BITFIELD_RANGE(0, 15); 163 uint32_t DW0_L0_Mv0y : MOS_BITFIELD_RANGE(16, 31); 164 }; 165 struct 166 { 167 uint32_t DW0_LumaIntraModeSecondBest : MOS_BITFIELD_RANGE(0, 5); 168 uint32_t DW0_LumaIntraModeSecondBest4x4_1 : MOS_BITFIELD_RANGE(6, 11); 169 uint32_t DW0_LumaIntraModeSecondBest4x4_2 : MOS_BITFIELD_RANGE(12, 17); 170 uint32_t DW0_LumaIntraModeSecondBest4x4_3 : MOS_BITFIELD_RANGE(18, 23); 171 uint32_t DW0_ChromaIntraModeSecondBest_o3a_p : MOS_BITFIELD_RANGE(24, 26); 172 uint32_t DW0_Reserved0 : MOS_BITFIELD_RANGE(27, 31); 173 }; 174 }; 175 176 //DWORD 1 177 uint32_t DW1_L0_Mv1x : MOS_BITFIELD_RANGE(0, 15); 178 uint32_t DW1_L0_Mv1y : MOS_BITFIELD_RANGE(16, 31); 179 180 //DWORD 2 181 uint32_t DW2_L1_Mv0x : MOS_BITFIELD_RANGE(0, 15); 182 uint32_t DW2_L1_Mv0y : MOS_BITFIELD_RANGE(16, 31); 183 184 //DWORD 3 185 uint32_t DW3_L1_Mv1x : MOS_BITFIELD_RANGE(0, 15); 186 uint32_t DW3_L1_Mv1y : MOS_BITFIELD_RANGE(16, 31); 187 188 //DWORD 4 189 uint32_t DW4_L0Mv0RefIdx : MOS_BITFIELD_RANGE(0, 3); 190 uint32_t DW4_L0Mv1RefIdx_ChromaIntraMode : MOS_BITFIELD_RANGE(4, 7); 191 uint32_t DW4_L1Mv0RefIdx_ChromaIntraMode2 : MOS_BITFIELD_RANGE(8, 11); 192 uint32_t DW4_L1Mv1RefIdx_ChromaIntraMode1 : MOS_BITFIELD_RANGE(12, 15); 193 uint32_t DW4_Tu_Yuv_TransformSkip : MOS_BITFIELD_RANGE(16, 31); 194 195 //DWORD 5 196 uint32_t DW5_TuSize : MOS_BITFIELD_RANGE(0, 31); 197 198 //DWORD 6 199 uint32_t DW6_LumaIntraMode4x4_1 : MOS_BITFIELD_RANGE(0, 5); 200 uint32_t DW6_LumaIntraMode4x4_2 : MOS_BITFIELD_RANGE(6, 11); 201 uint32_t DW6_LumaIntraMode4x4_3 : MOS_BITFIELD_RANGE(12, 17); 202 uint32_t DW6_RoundingSelect : MOS_BITFIELD_RANGE(18, 21); 203 uint32_t DW6_Reserved0 : MOS_BITFIELD_RANGE(22, 23); 204 uint32_t DW6_TuCountMinus1 : MOS_BITFIELD_RANGE(24, 27); 205 uint32_t DW6_Reserved1 : MOS_BITFIELD_RANGE(28, 31); 206 207 //DWORD 7 208 uint32_t DW7_LumaIntraMode : MOS_BITFIELD_RANGE(0, 5); 209 uint32_t DW7_CuSize : MOS_BITFIELD_RANGE(6, 7); 210 uint32_t DW7_ChromaIntraMode : MOS_BITFIELD_RANGE(8, 10); 211 uint32_t DW7_CuTransquantBypassFlag : MOS_BITFIELD_BIT(11); 212 uint32_t DW7_CuPartMode : MOS_BITFIELD_RANGE(12, 14); 213 uint32_t DW7_CuPredMode : MOS_BITFIELD_BIT(15); 214 uint32_t DW7_InterPredIdcMv0 : MOS_BITFIELD_RANGE(16, 17); 215 uint32_t DW7_InterPredIdcMv1 : MOS_BITFIELD_RANGE(18, 19); 216 uint32_t DW7_ModifiedFlag : MOS_BITFIELD_BIT(20); 217 uint32_t DW7_ForceZeroCoeff : MOS_BITFIELD_BIT(21); 218 uint32_t DW7_Reserved0 : MOS_BITFIELD_RANGE(22, 23); 219 uint32_t DW7_CuQp : MOS_BITFIELD_RANGE(24, 30); 220 uint32_t DW7_CuQpSign : MOS_BITFIELD_BIT(31); 221 222 }; 223 224 struct MHW_VDBOX_HEVC_SLICE_STATE_G12 : public MHW_VDBOX_HEVC_SLICE_STATE 225 { 226 // GEN11+ Tile coding params 227 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 pTileCodingParams = nullptr; 228 uint32_t dwTileID = 0; 229 uint32_t dwNumPipe = 0; 230 231 // For real tile decoding across tile 232 bool bTileInSlice = false; //!< This slice across tiles 233 bool bIsNotFirstTile = false; //!< Not first tile in slice 234 uint16_t u16SliceHeaderLength = 0; //!< Slice header length in this entrypoint 235 uint16_t u16TileCtbX = 0; //!< Ctb X index for this tile 236 uint16_t u16TileCtbY = 0; //!< Ctb Y index for this tile 237 uint16_t u16NextTileCtbX = 0; //!< Ctb X index for next tile 238 uint16_t u16NextTileCtbY = 0; //!< Ctb Y index for next tile 239 uint16_t u16OrigCtbX = 0; //!< Original slice start Ctb X index 240 uint16_t u16OrigCtbY = 0; //!< Original slice start Ctb Y index 241 242 PCODEC_HEVC_EXT_SLICE_PARAMS pHevcExtSliceParams = nullptr; 243 PCODEC_HEVC_EXT_PIC_PARAMS pHevcExtPicParam = nullptr; 244 PCODEC_HEVC_SCC_PIC_PARAMS pHevcSccPicParam = nullptr; 245 246 // For SCC 247 uint8_t ucRecNotFilteredID = 0; 248 }; 249 using PMHW_VDBOX_HEVC_SLICE_STATE_G12 = MHW_VDBOX_HEVC_SLICE_STATE_G12 *; 250 251 struct MHW_VDBOX_HEVC_REF_IDX_PARAMS_G12 : public MHW_VDBOX_HEVC_REF_IDX_PARAMS 252 { 253 // For SCC 254 bool bIBCEnabled = false;; 255 uint8_t ucRecNotFilteredID = 0;; 256 }; 257 using PMHW_VDBOX_HEVC_REF_IDX_PARAMS_G12 = MHW_VDBOX_HEVC_REF_IDX_PARAMS_G12 *; 258 259 struct MHW_VDBOX_HEVC_PIC_STATE_G12 : public MHW_VDBOX_HEVC_PIC_STATE 260 { 261 PCODEC_HEVC_EXT_PIC_PARAMS pHevcExtPicParams = nullptr; 262 PCODEC_HEVC_SCC_PIC_PARAMS pHevcSccPicParams = nullptr; 263 264 // For SCC 265 uint8_t ucRecNotFilteredID = 0; 266 uint8_t IBCControl = 0; 267 bool PartialFrameUpdateEnable = false; 268 }; 269 using PMHW_VDBOX_HEVC_PIC_STATE_G12 = MHW_VDBOX_HEVC_PIC_STATE_G12 *; 270 271 struct MHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G12 : public MHW_VDBOX_PIPE_BUF_ADDR_PARAMS 272 { 273 //Scalable 274 PMOS_RESOURCE presSliceStateStreamOutBuffer = nullptr; 275 PMOS_RESOURCE presMvUpRightColStoreBuffer = nullptr; 276 PMOS_RESOURCE presIntraPredUpRightColStoreBuffer = nullptr; 277 PMOS_RESOURCE presIntraPredLeftReconColStoreBuffer = nullptr; 278 PMOS_RESOURCE presCABACSyntaxStreamOutBuffer = nullptr; 279 PMOS_RESOURCE presCABACSyntaxStreamOutMaxAddr = nullptr; 280 281 //Reference Mmc 282 bool bSpecificReferencedMmcRequired = false; 283 MOS_MEMCOMP_STATE ReferencesMmcState = MOS_MEMCOMP_DISABLED; 284 }; 285 using PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G12 = MHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G12 *; 286 287 // the tile size record is streamed out serving 2 purposes 288 // in vp9 for back annotation of tile size into the bitstream 289 struct HCPPakHWTileSizeRecord_G12 290 { 291 //DW0 292 uint32_t 293 Address_31_0; 294 295 //DW1 296 uint32_t 297 Address_63_32; 298 299 //DW2 300 uint32_t 301 Length; // Bitstream length per tile; includes header len in first tile, and tail len in last tile 302 303 //DW3 304 uint32_t 305 TileSize; // In Vp9, it is used for back annotation, In Hevc, it is the mmio register bytecountNoHeader 306 307 //DW4 308 uint32_t 309 AddressOffset; // Cacheline offset 310 311 //DW5 312 uint32_t 313 ByteOffset : 6, //[5:0] // Byte offset within cacheline 314 Res_95_70 : 26; //[31:6] 315 316 //DW6 317 uint32_t 318 Hcp_Bs_SE_Bitcount_Tile; // bitstream size for syntax element per tile 319 320 //DW7 321 uint32_t 322 Hcp_Cabac_BinCnt_Tile; // bitstream size for syntax element per tile 323 324 //DW8 325 uint32_t 326 Res_DW8_31_0; 327 328 //DW9 329 uint32_t 330 Hcp_Image_Status_Ctrl; // image status control per tile 331 332 //DW10 333 uint32_t 334 Hcp_Qp_Status_Count; // Qp status count per tile 335 336 //DW11 337 uint32_t 338 Hcp_Slice_Count_Tile; // number of slices per tile 339 340 //DW12-15 341 uint32_t 342 Res_DW12_DW15[4]; // reserved bits added so that QwordDisables are set correctly 343 }; 344 345 //! MHW Vdbox Hcp interface for Gen11 346 /*! 347 This class defines the Hcp command construction functions for Gen11 platform 348 */ 349 class MhwVdboxHcpInterfaceG12 : public MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g12_X> 350 { 351 protected: 352 #define PATCH_LIST_COMMAND(x) (x##_NUMBER_OF_ADDRESSES) 353 354 enum CommandsNumberOfAddresses 355 { 356 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 357 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 358 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 359 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 360 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 361 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 4, // 4 DW for 2 address fields 362 MI_SEMAPHORE_WAIT_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address fields 363 MI_ATOMIC_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 364 365 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 366 367 HCP_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 368 HCP_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 369 HCP_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 45, // 45 address fields 370 HCP_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 11, // 22 DW for 11 address field 371 HCP_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 372 HCP_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 373 HCP_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 374 HCP_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 375 HCP_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 376 HCP_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 377 HCP_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 378 HCP_TILE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 379 HCP_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 380 HCP_VP9_SEGMENT_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 381 HCP_VP9_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 382 HCP_TILE_CODING_COMMAND_NUMBER_OF_ADDRESSES = 1, // 0 DW for address fields 383 HCP_PALETTE_INITIALIZER_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 384 385 VDENC_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 12, // 12 DW for 12 address fields 386 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields 387 }; 388 389 enum HcpPicStateIbcConfigurationInVdencMode 390 { 391 HCP_PIC_STATE_IBC_CONFIGURATION_IN_VDENC_MODE_UNNAMED0 = 0, ///< When IBC configuration in VDENC mode is set to 0, Intra block search is disabled. 392 HCP_PIC_STATE_IBC_CONFIGURATION_IN_VDENC_MODE_UNNAMED1 = 1, ///< When IBC configuration in VDENC mode is set to 1, Intra block search includes only left region. 393 HCP_PIC_STATE_IBC_CONFIGURATION_IN_VDENC_MODE_UNNAMED2 = 2, ///< 394 HCP_PIC_STATE_IBC_CONFIGURATION_IN_VDENC_MODE_UNNAMED3 = 3, ///< When IBC configuration in VDENC mode is set to 2, Intra block search includes top and left regions. 395 }; 396 397 bool m_hevcRDOQPerfDisabled = false; //!< Flag to indicate if HEVC RDOQ Perf is disabled 398 uint32_t m_watchDogTimerThreshold = 0; //!< For Watch Dog Timer threshold on Gen11+ 399 bool m_disableTlbPrefetch = false; //!< To disable TLB pre-fetch or not 400 401 static const uint32_t m_HevcSccPaletteSize = 96; //!< For HEVC SCC palette size on Gen12+ 402 static const uint32_t m_hcpPakObjSize = MOS_BYTES_TO_DWORDS(sizeof(HcpPakObjectG12)); //!< hcp pak object size 403 404 static const uint32_t m_veboxRgbHistogramSizePerSlice = 256 * 4; 405 static const uint32_t m_veboxNumRgbChannel = 3; 406 static const uint32_t m_veboxAceHistogramSizePerFramePerSlice = 256 * 4; 407 static const uint32_t m_veboxNumFramePreviousCurrent = 2; 408 409 static const uint32_t m_veboxMaxSlices = 4; 410 static const uint32_t m_veboxRgbHistogramSize = m_veboxRgbHistogramSizePerSlice * m_veboxNumRgbChannel * m_veboxMaxSlices; 411 static const uint32_t m_veboxRgbAceHistogramSizeReserved = 3072 * 4; 412 static const uint32_t m_veboxLaceHistogram256BinPerBlock = 256 * 2; 413 static const uint32_t m_veboxStatisticsSize = 32 * 8; 414 415 public: 416 static const uint32_t m_watchDogEnableCounter = 0x0; 417 static const uint32_t m_watchDogDisableCounter = 0x00000001; 418 static const uint32_t m_watchDogTimeoutInMs = 120; // derived from WDT threshold in KMD 419 420 //! 421 //! \brief Constructor 422 //! MhwVdboxHcpInterfaceG12(PMOS_INTERFACE osInterface,MhwMiInterface * miInterface,MhwCpInterface * cpInterface,bool decodeInUse)423 MhwVdboxHcpInterfaceG12( 424 PMOS_INTERFACE osInterface, 425 MhwMiInterface *miInterface, 426 MhwCpInterface *cpInterface, 427 bool decodeInUse) 428 : MhwVdboxHcpInterfaceGeneric(osInterface, miInterface, cpInterface, decodeInUse) 429 { 430 MHW_FUNCTION_ENTER; 431 432 m_rhoDomainStatsEnabled = true; 433 434 // Debug hook for HEVC RDOQ issue on Gen11 435 MOS_USER_FEATURE_VALUE_DATA userFeatureData; 436 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); 437 #if (_DEBUG || _RELEASE_INTERNAL) 438 MOS_UserFeature_ReadValue_ID( 439 nullptr, 440 __MEDIA_USER_FEATURE_VALUE_HEVC_ENCODE_RDOQ_PERF_DISABLE_ID, 441 &userFeatureData, 442 this->m_osInterface->pOsContext); 443 #endif // _DEBUG || _RELEASE_INTERNAL 444 m_hevcRDOQPerfDisabled = userFeatureData.i32Data ? true : false; 445 446 m_watchDogTimerThreshold = m_watchDogTimeoutInMs; 447 #if (_DEBUG || _RELEASE_INTERNAL) 448 // User feature config of watchdog timer threshold 449 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); 450 MOS_UserFeature_ReadValue_ID( 451 nullptr, 452 __MEDIA_USER_FEATURE_VALUE_WATCHDOG_TIMER_THRESHOLD, 453 &userFeatureData, 454 this->m_osInterface->pOsContext); 455 if (userFeatureData.u32Data != 0) 456 { 457 m_watchDogTimerThreshold = userFeatureData.u32Data; 458 } 459 #endif 460 461 if (MEDIA_IS_WA(m_osInterface->pfnGetWaTable(m_osInterface), Wa_14012254246)) 462 { 463 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); 464 MOS_UserFeature_ReadValue_ID( 465 nullptr, 466 __MEDIA_USER_FEATURE_VALUE_DISABLE_TLB_PREFETCH_ID, 467 &userFeatureData, 468 this->m_osInterface->pOsContext); 469 m_disableTlbPrefetch = userFeatureData.u32Data ? true : false; 470 } 471 472 m_hevcEncCuRecordSize = sizeof(EncodeHevcCuDataG12); 473 m_pakHWTileSizeRecordSize = sizeof(HCPPakHWTileSizeRecord_G12); 474 475 InitRowstoreUserFeatureSettings(); 476 InitMmioRegisters(); 477 } 478 479 //! 480 //! \brief Destructor 481 //! 482 virtual ~MhwVdboxHcpInterfaceG12(); 483 GetHcpPakObjSize()484 uint32_t GetHcpPakObjSize() 485 { 486 return m_hcpPakObjSize; 487 } 488 GetHcpHevcVp9RdoqStateCommandSize()489 inline uint32_t GetHcpHevcVp9RdoqStateCommandSize() 490 { 491 return mhw_vdbox_hcp_g12_X::HEVC_VP9_RDOQ_STATE_CMD::byteSize; 492 } 493 GetHcpVp9PicStateCommandSize()494 inline uint32_t GetHcpVp9PicStateCommandSize() 495 { 496 return mhw_vdbox_hcp_g12_X::HCP_VP9_PIC_STATE_CMD::byteSize; 497 } 498 GetHcpVp9SegmentStateCommandSize()499 inline uint32_t GetHcpVp9SegmentStateCommandSize() 500 { 501 return mhw_vdbox_hcp_g12_X::HCP_VP9_SEGMENT_STATE_CMD::byteSize; 502 } 503 GetWatchDogTimerThrehold()504 inline uint32_t GetWatchDogTimerThrehold() 505 { 506 return m_watchDogTimerThreshold; 507 } 508 509 void InitMmioRegisters(); 510 511 void InitRowstoreUserFeatureSettings(); 512 513 MOS_STATUS GetRowstoreCachingAddrs( 514 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams); 515 516 MOS_STATUS GetHcpStateCommandSize( 517 uint32_t mode, 518 uint32_t *commandsSize, 519 uint32_t *patchListSize, 520 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params); 521 522 MOS_STATUS GetHcpPrimitiveCommandSize( 523 uint32_t mode, 524 uint32_t *commandsSize, 525 uint32_t *patchListSize, 526 bool modeSpecific); 527 528 MOS_STATUS GetHevcBufferSize( 529 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 530 PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam); 531 532 MOS_STATUS GetVp9BufferSize( 533 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 534 PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam); 535 536 MOS_STATUS IsHevcBufferReallocNeeded( 537 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 538 PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam); 539 540 MOS_STATUS IsVp9BufferReallocNeeded( 541 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 542 PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam); 543 544 MOS_STATUS AddHcpPipeModeSelectCmd( 545 PMOS_COMMAND_BUFFER cmdBuffer, 546 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS params); 547 548 MOS_STATUS AddHcpDecodeSurfaceStateCmd( 549 PMOS_COMMAND_BUFFER cmdBuffer, 550 PMHW_VDBOX_SURFACE_PARAMS params); 551 552 MOS_STATUS AddHcpEncodeSurfaceStateCmd( 553 PMOS_COMMAND_BUFFER cmdBuffer, 554 PMHW_VDBOX_SURFACE_PARAMS params); 555 556 MOS_STATUS AddHcpPipeBufAddrCmd( 557 PMOS_COMMAND_BUFFER cmdBuffer, 558 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS params); 559 560 MOS_STATUS AddHcpIndObjBaseAddrCmd( 561 PMOS_COMMAND_BUFFER cmdBuffer, 562 PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS params); 563 564 MOS_STATUS AddHcpDecodePicStateCmd( 565 PMOS_COMMAND_BUFFER cmdBuffer, 566 PMHW_VDBOX_HEVC_PIC_STATE params); 567 568 MOS_STATUS AddHcpEncodePicStateCmd( 569 PMOS_COMMAND_BUFFER cmdBuffer, 570 PMHW_VDBOX_HEVC_PIC_STATE params); 571 572 MOS_STATUS AddHcpTileStateCmd( 573 PMOS_COMMAND_BUFFER cmdBuffer, 574 PMHW_VDBOX_HEVC_TILE_STATE params); 575 576 MOS_STATUS AddHcpRefIdxStateCmd( 577 PMOS_COMMAND_BUFFER cmdBuffer, 578 PMHW_BATCH_BUFFER batchBuffer, 579 PMHW_VDBOX_HEVC_REF_IDX_PARAMS params); 580 581 MOS_STATUS AddHcpWeightOffsetStateCmd( 582 PMOS_COMMAND_BUFFER cmdBuffer, 583 PMHW_BATCH_BUFFER batchBuffer, 584 PMHW_VDBOX_HEVC_WEIGHTOFFSET_PARAMS params); 585 586 MOS_STATUS AddHcpFqmStateCmd( 587 PMOS_COMMAND_BUFFER cmdBuffer, 588 PMHW_VDBOX_QM_PARAMS params); 589 590 MOS_STATUS AddHcpDecodeSliceStateCmd( 591 PMOS_COMMAND_BUFFER cmdBuffer, 592 PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState); 593 594 MOS_STATUS AddHcpEncodeSliceStateCmd( 595 PMOS_COMMAND_BUFFER cmdBuffer, 596 PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState); 597 598 MOS_STATUS AddHcpPakInsertObject( 599 PMOS_COMMAND_BUFFER cmdBuffer, 600 PMHW_VDBOX_PAK_INSERT_PARAMS params); 601 602 MOS_STATUS AddHcpVp9PicStateCmd( 603 PMOS_COMMAND_BUFFER cmdBuffer, 604 PMHW_BATCH_BUFFER batchBuffer, 605 PMHW_VDBOX_VP9_PIC_STATE params); 606 607 MOS_STATUS AddHcpVp9PicStateEncCmd( 608 PMOS_COMMAND_BUFFER cmdBuffer, 609 PMHW_BATCH_BUFFER batchBuffer, 610 PMHW_VDBOX_VP9_ENCODE_PIC_STATE params); 611 612 MOS_STATUS AddHcpVp9SegmentStateCmd( 613 PMOS_COMMAND_BUFFER cmdBuffer, 614 PMHW_BATCH_BUFFER batchBuffer, 615 PMHW_VDBOX_VP9_SEGMENT_STATE params); 616 617 MOS_STATUS AddHcpHevcVp9RdoqStateCmd( 618 PMOS_COMMAND_BUFFER cmdBuffer, 619 PMHW_VDBOX_HEVC_PIC_STATE params); 620 621 //! 622 //! \brief Adds HCP tile coding command in command buffer for decoder 623 //! 624 //! \param [in] cmdBuffer 625 //! Command buffer to which HW command is added 626 //! \param [in] params 627 //! Params structure used to populate the HW command 628 //! 629 //! \return MOS_STATUS 630 //! MOS_STATUS_SUCCESS if success, else fail reason 631 //! 632 MOS_STATUS AddHcpDecodeTileCodingCmd( 633 PMOS_COMMAND_BUFFER cmdBuffer, 634 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params); 635 636 //! 637 //! \brief Adds HCP tile coding command in command buffer for encoder 638 //! 639 //! \param [in] cmdBuffer 640 //! Command buffer to which HW command is added 641 //! \param [in] params 642 //! Params structure used to populate the HW command 643 //! 644 //! \return MOS_STATUS 645 //! MOS_STATUS_SUCCESS if success, else fail reason 646 //! 647 MOS_STATUS AddHcpEncodeTileCodingCmd( 648 PMOS_COMMAND_BUFFER cmdBuffer, 649 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params); 650 651 MOS_STATUS AddHcpHevcPicBrcBuffer( 652 PMOS_RESOURCE hcpImgStates, 653 PMHW_VDBOX_HEVC_PIC_STATE hevcPicState); 654 655 //! 656 //! \brief Adds HCP tile coding command in command buffer 657 //! \details Client facing function to add HCP tile coding command in command buffer 658 //! 659 //! \param [in] cmdBuffer 660 //! Command buffer to which HW command is added 661 //! \param [in] params 662 //! Params structure used to populate the HW command 663 //! 664 //! \return MOS_STATUS 665 //! MOS_STATUS_SUCCESS if success, else fail reason 666 //! 667 MOS_STATUS AddHcpTileCodingCmd( 668 PMOS_COMMAND_BUFFER cmdBuffer, 669 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params); 670 671 //! 672 //! \brief Adds Hcp palette initializer state in command buffer 673 //! 674 //! \param [in] cmdBuffer 675 //! Command buffer to which HW command is added 676 //! \param [in] params 677 //! Params structure used to populate the HW command 678 //! 679 //! \return MOS_STATUS 680 //! MOS_STATUS_SUCCESS if success, else fail reason 681 //! 682 MOS_STATUS AddHcpPaletteInitializerStateCmd( 683 PMOS_COMMAND_BUFFER cmdBuffer, 684 PCODEC_HEVC_SCC_PIC_PARAMS params); 685 686 MOS_STATUS GetOsResLaceOrAceOrRgbHistogramBufferSize( 687 uint32_t width, 688 uint32_t height, 689 uint32_t *size); 690 691 MOS_STATUS GetOsResStatisticsOutputBufferSize( 692 uint32_t width, 693 uint32_t height, 694 uint32_t *size); 695 }; 696 697 #endif