1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "dramc_int_global.h" //for gu1BroadcastIsLP4
8 #include "dramc_dv_init.h"
9 #include "x_hal_io.h"
10 #if (FOR_DV_SIMULATION_USED == 0)
11 #include "dramc_top.h"
12 #endif
13 #include "emi.h"
14 //#include "dramc_register.h"
15 #if __ETT__
16 #include <barriers.h>
17 #endif
18 #if DRAM_AUXADC_CONFIG
19 #include <mtk_auxadc_sw.h>
20 #endif
21 //-----------------------------------------------------------------------------
22 // Global variables
23 //-----------------------------------------------------------------------------
24
25 #if (fcFOR_CHIP_ID == fcA60868)
26 U8 u1EnterRuntime;
27 #endif
28
u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type)29 U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type)
30 {
31 if (dram_type == TYPE_LPDDR5)
32 return FALSE;
33 else
34 return TRUE;
35 }
36
is_lp5_family(DRAMC_CTX_T * p)37 u8 is_lp5_family(DRAMC_CTX_T *p)
38 {
39 return p->dram_type == TYPE_LPDDR5? TRUE: FALSE;
40 }
41
is_heff_mode(DRAMC_CTX_T * p)42 u8 is_heff_mode(DRAMC_CTX_T *p)
43 {
44 u8 res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
45 SHU_COMMON0_LP5HEFF_MODE);
46 mcSHOW_DBG_MSG5(("HEFF Mode: %d\n", res));
47 return res? TRUE: FALSE;
48 }
49
50 #if FOR_DV_SIMULATION_USED
51 U8 u1BroadcastOnOff = 0;
52 #endif
GetDramcBroadcast(void)53 U32 GetDramcBroadcast(void)
54 {
55 #if (fcFOR_CHIP_ID == fcA60868)
56 return 0;
57 #endif
58
59 #if (FOR_DV_SIMULATION_USED == 0)
60 return *((volatile unsigned int *)(DRAMC_WBR));
61 #else
62 return u1BroadcastOnOff;
63 #endif
64 }
65
DramcBroadcastOnOff(U32 bOnOff)66 void DramcBroadcastOnOff(U32 bOnOff)
67 {
68 #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
69
70 #if (fcFOR_CHIP_ID == fcA60868)
71 return;
72 #endif
73
74 #if __Petrus_TO_BE_PORTING__
75 U8 u1BroadcastStatus = 0;
76
77 u1BroadcastStatus = (*((volatile unsigned int *)(INFRA_RSVD3)) >> 8) & 0x3;
78 if (u1BroadcastStatus & 0x1)
79 {
80 if (bOnOff == DRAMC_BROADCAST_ON)
81 *((volatile unsigned int *)(DRAMC_WBR_SET)) = DRAMC_BROADCAST_SET;
82 else
83 *((volatile unsigned int *)(DRAMC_WBR_CLR)) = DRAMC_BROADCAST_CLR;
84 }
85 else
86 #endif
87 if (bOnOff == DRAMC_BROADCAST_ON) {
88 if (channel_num_auxadc > 2)
89 *((volatile unsigned int *)(DRAMC_WBR)) = DRAMC_BROADCAST_ON_4CH;
90 else
91 *((volatile unsigned int *)(DRAMC_WBR)) = DRAMC_BROADCAST_ON_2CH;
92 }
93 else {
94 *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff;
95 }
96 dsb();
97 #endif
98
99 #if (FOR_DV_SIMULATION_USED == 1)
100 if (gu1BroadcastIsLP4 == TRUE)
101 {
102 #if (fcFOR_CHIP_ID == fcA60868)
103 bOnOff = 0;
104 #endif
105 if (bOnOff)
106 {
107 broadcast_on();
108 mcSHOW_DBG_MSG2(("Broadcast ON\n"));
109 u1BroadcastOnOff = bOnOff;
110 }
111 else
112 {
113 broadcast_off();
114 mcSHOW_DBG_MSG2(("Broadcast OFF\n"));
115 u1BroadcastOnOff = bOnOff;
116 }
117 }
118 #endif
119
120 #ifdef DUMP_INIT_RG_LOG_TO_DE
121 if(gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag)
122 {
123 U8 u1BroadcastStatus = 0;
124 U32 addr, val;
125
126 addr = DRAMC_WBR;
127 val = bOnOff;
128 // *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff;
129
130 mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",addr, val));
131 // mcDELAY_MS(1);
132 #if (FOR_DV_SIMULATION_USED==0)
133 GPT_Delay_ms(1);
134 #endif
135 }
136 #endif
137 }
138
139
140
141 #if __ETT__
142 const U32 u4Cannot_Use_Dramc_WBR_Reg[]=
143 {
144 DDRPHY_REG_CA_DLL_ARPI5,
145 DDRPHY_REG_B0_DLL_ARPI5,
146 DDRPHY_REG_B1_DLL_ARPI5,
147
148 DDRPHY_REG_SHU_CA_DLL0,
149 DDRPHY_REG_SHU_CA_DLL1,
150
151 DDRPHY_REG_CA_LP_CTRL0,
152
153 DDRPHY_REG_MISC_DVFSCTL2,
154 DDRPHY_REG_MISC_SHU_OPT,
155
156 DDRPHY_REG_MISC_DVFSCTL,
157 DDRPHY_REG_MISC_DVFSCTL3,
158
159 DDRPHY_REG_MISC_CKMUX_SEL,
160 DRAMC_REG_DVFS_CTRL0
161 };
162 #define CANNOT_USE_WBR_SIZE ((sizeof(u4Cannot_Use_Dramc_WBR_Reg)) / (sizeof(U32)))
CheckDramcWBR(U32 u4address)163 void CheckDramcWBR(U32 u4address)
164 {
165
166 U32 i, channel_and_value;
167 if (GetDramcBroadcast()==DRAMC_BROADCAST_ON)
168 {
169 #if (CHANNEL_NUM > 2)
170 if (channel_num_auxadc > 2) {
171 channel_and_value = 0x3;
172 }
173 #else
174 channel_and_value = 0x1;
175 #endif
176 if ((((u4address - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & channel_and_value) != CHANNEL_A)
177 {
178 mcSHOW_ERR_MSG(("Error! virtual address 0x%x is not CHA and cannot use Dramc WBR\n", u4address));
179 while (1);
180 }
181 for (i = 0; i < CANNOT_USE_WBR_SIZE; i++)
182 {
183 if (u4Cannot_Use_Dramc_WBR_Reg[i] == u4address)
184 {
185 mcSHOW_ERR_MSG(("Error! virtual address 0x%x cannot use Dramc WBR\n", u4address));
186 while (1);
187 }
188 }
189 }
190 }
191 #endif
192
vSetPHY2ChannelMapping(DRAMC_CTX_T * p,U8 u1Channel)193 void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel)
194 {
195 p->channel = (DRAM_CHANNEL_T)u1Channel;
196 }
197
vGetPHY2ChannelMapping(DRAMC_CTX_T * p)198 U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p)
199 {
200 return p->channel;
201 }
202 #if 0
203 static U8 GetChannelInfoToConf(DRAMC_CTX_T *p)
204 {
205 U8 u1ch_num = CHANNEL_NUM;
206 #if ((fcFOR_CHIP_ID == fc8195) && (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0))
207 EMI_SETTINGS *emi_set;
208 U32 u4value = 0;
209
210 emi_set = &g_default_emi_setting;
211
212 u4value = (emi_set->EMI_CONA_VAL >> 8) & 0x3;
213
214 if (u4value == 0)
215 u1ch_num = CHANNEL_SINGLE;
216 else if (u4value == 1)
217 u1ch_num = CHANNEL_DUAL;
218 #if (CHANNEL_NUM > 2)
219 else if (u4value == 2)
220 if (channel_num_auxadc > 2) {
221 u1ch_num = CHANNEL_FOURTH;
222 }
223 #endif
224 mcSHOW_DBG_MSG2(("Channel num: %d, CONA[0x%x]\n", u1ch_num, emi_set->EMI_CONA_VAL));
225 #endif
226 return u1ch_num;
227 }
228 #endif
vSetChannelNumber(DRAMC_CTX_T * p)229 void vSetChannelNumber(DRAMC_CTX_T *p)
230 {
231 #if DRAM_AUXADC_CONFIG
232 p->support_channel_num = channel_num_auxadc;//GetChannelInfoToConf(p);
233 #else
234 p->support_channel_num = CHANNEL_FOURTH;
235 #endif
236 }
237
vSetRank(DRAMC_CTX_T * p,U8 ucRank)238 void vSetRank(DRAMC_CTX_T *p, U8 ucRank)
239 {
240 p->rank = (DRAM_RANK_T)ucRank;
241 }
242
u1GetRank(DRAMC_CTX_T * p)243 U8 u1GetRank(DRAMC_CTX_T *p)
244 {
245 return p->rank;
246 }
247
vSetRankNumber(DRAMC_CTX_T * p)248 void vSetRankNumber(DRAMC_CTX_T *p)
249 {
250 #if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
251 if (u4IO32ReadFldAlign(DRAMC_REG_SA_RESERVE, SA_RESERVE_SINGLE_RANK) == 1)
252 {
253 p->support_rank_num =RANK_SINGLE;
254 }
255 else
256 #endif
257 {
258 p->support_rank_num = RANK_DUAL;
259 }
260 }
261
vSetFSPNumber(DRAMC_CTX_T * p)262 void vSetFSPNumber(DRAMC_CTX_T *p)
263 {
264 p->support_fsp_num = 2;
265 }
266
setFreqGroup(DRAMC_CTX_T * p)267 static void setFreqGroup(DRAMC_CTX_T *p)
268 {
269
270
271 {
272 if (p->frequency <= 200)
273 {
274 p->freqGroup = 200;
275 }
276 else if (p->frequency <= 400)
277 {
278 p->freqGroup = 400;
279 }
280 else if (p->frequency <= 600)
281 {
282 p->freqGroup = 600;
283 }
284 else if (p->frequency <= 800)
285 {
286 p->freqGroup = 800;
287 }
288 else if (p->frequency <= 933)
289 {
290 p->freqGroup = 933;
291 }
292 else if (p->frequency <= 1200)
293 {
294 p->freqGroup = 1200;
295 }
296 else if (p->frequency <= 1333)
297 {
298 p->freqGroup = 1333;
299 }
300 else if (p->frequency <= 1600)
301 {
302 p->freqGroup = 1600;
303 }
304 else if (p->frequency <= 1866)
305 {
306 p->freqGroup = 1866;
307 }
308 else
309 {
310 p->freqGroup = 2133;
311 }
312 }
313
314 mcSHOW_DBG_MSG4(("[setFreqGroup] p-> frequency %u, freqGroup: %u\n", p->frequency, p->freqGroup));
315 return;
316 }
317
318
319 #define CKGEN_FMETER 0x0
320 #define ABIST_FMETER 0x1
321
322 U16 gddrphyfmeter_value[DRAM_DFS_SRAM_MAX] = {0};
323
DDRPhyGetRealFreq(DRAMC_CTX_T * p)324 U16 DDRPhyGetRealFreq(DRAMC_CTX_T *p)
325 {
326 U8 u1SRAMShuLevel = vGet_Current_SRAMIdx(p);
327
328
329 if(gddrphyfmeter_value[u1SRAMShuLevel])
330 {
331 return gddrphyfmeter_value[u1SRAMShuLevel];
332 }else{
333 mcSHOW_ERR_MSG(("gddrphyfmeter_value[%d] = 0, return p->frequency\n", u1SRAMShuLevel));
334 return p->frequency;
335 }
336 }
337
338 #if __ETT__ || defined(SLT)
GetPhyPllFrequency(DRAMC_CTX_T * p)339 void GetPhyPllFrequency(DRAMC_CTX_T *p)
340 {
341
342 U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP);
343 U32 u4PLL5_ADDR = DDRPHY_REG_SHU_PHYPLL1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
344 U32 u4PLL8_ADDR = DDRPHY_REG_SHU_PHYPLL2 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
345 U32 u4B0_DQ = DDRPHY_REG_SHU_B0_DQ1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
346 U32 u4PLL3_ADDR = DDRPHY_REG_SHU_PHYPLL3 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
347
348 U32 u4B0_DQ6 = DDRPHY_REG_SHU_B0_DQ6 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
349
350 U32 u4SDM_PCW = u4IO32ReadFldAlign(u4PLL5_ADDR, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW);
351 U32 u4PREDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_PREDIV);
352 U32 u4POSDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_POSDIV);
353 U32 u4CKDIV4 = u4IO32ReadFldAlign(u4B0_DQ, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0);
354 U8 u1FBKSEL = u4IO32ReadFldAlign(u4PLL3_ADDR, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL);
355
356 U8 u1SopenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0);
357 U8 u1OpenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0);
358
359 U32 u4VCOFreq = (((52>>u4PREDIV)*(u4SDM_PCW>>8))>>u4POSDIV) << u1FBKSEL;
360 U32 u4DataRate = u4VCOFreq>>u4CKDIV4;
361 if ((u1SopenDQ == ENABLE)||(u1OpenDQ == ENABLE))
362 u4DataRate >>= 2;
363
364 //mcSHOW_DBG_MSG(("PCW=0x%X, u4PREDIV=%d, u4POSDIV=%d, CKDIV4=%d, DataRate=%d\n", u4SDM_PCW, u4PREDIV, u4POSDIV, u4CKDIV4, u4DataRate));
365 mcSHOW_DBG_MSG2(("[F] DataRate=%d at SHU%d\n", u4DataRate, u1ShuLevel));
366 }
367 #endif
368
vGet_PLL_FreqSel(DRAMC_CTX_T * p)369 DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p)
370 {
371 return p->pDFSTable->freq_sel;
372 }
373
vSet_PLL_FreqSel(DRAMC_CTX_T * p,DRAM_PLL_FREQ_SEL_T sel)374 void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
375 {
376 p->pDFSTable->freq_sel = sel;
377 }
378
vGet_DDR_Loop_Mode(DRAMC_CTX_T * p)379 DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p)
380 {
381 return p->pDFSTable->ddr_loop_mode;
382 }
383
vSet_Div_Mode(DRAMC_CTX_T * p,DIV_MODE_T eMode)384 void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode)
385 {
386 p->pDFSTable->divmode = eMode;
387 }
388
vGet_Div_Mode(DRAMC_CTX_T * p)389 DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p)
390 {
391 return p->pDFSTable->divmode;
392 }
393
vSet_Current_SRAMIdx(DRAMC_CTX_T * p,DRAM_DFS_SRAM_SHU_T u1SRAMIdx)394 void vSet_Current_SRAMIdx(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1SRAMIdx)
395 {
396 p->pDFSTable->SRAMIdx = u1SRAMIdx;
397 }
398
vGet_Current_SRAMIdx(DRAMC_CTX_T * p)399 DRAM_DFS_SRAM_SHU_T vGet_Current_SRAMIdx(DRAMC_CTX_T *p)
400 {
401 return p->pDFSTable->SRAMIdx;
402 }
403
404 #if 0
405 void vSet_Duty_Calibration_Mode(DRAMC_CTX_T *p, U8 kMode)
406 {
407 p->pDFSTable->duty_calibration_mode = kMode;
408 }
409 #endif
410
Get_Duty_Calibration_Mode(DRAMC_CTX_T * p)411 DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p)
412 {
413 return p->pDFSTable->duty_calibration_mode;
414 }
415
Get_Vref_Calibration_OnOff(DRAMC_CTX_T * p)416 VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p)
417 {
418 #if FOR_DV_SIMULATION_USED
419 return VREF_CALI_OFF;
420 #else
421 return p->pDFSTable->vref_calibartion_enable;
422 #endif
423 }
424
425
vGet_Dram_CBT_Mode(DRAMC_CTX_T * p)426 DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p)
427 {
428 if (p->support_rank_num == RANK_DUAL)
429 {
430 if(p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE && p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)
431 return CBT_NORMAL_MODE;
432 }
433 else // Single rank
434 {
435 if(p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE)
436 return CBT_NORMAL_MODE;
437 }
438
439 return CBT_BYTE_MODE1;
440 }
441
442
vPrintCalibrationBasicInfo(DRAMC_CTX_T * p)443 void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p)
444 {
445 #if __ETT__
446 mcSHOW_DBG_MSG(("===============================================================================\n"));
447 mcSHOW_DBG_MSG(("Dram Type= %d, Freq= %u, FreqGroup= %u, CH_%d, rank %d\n"
448 "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n",
449 p->dram_type, DDRPhyGetRealFreq(p), p->freqGroup, p->channel, p->rank,
450 p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p)));
451 mcSHOW_DBG_MSG(("===============================================================================\n"));
452
453 #else
454 mcSHOW_DBG_MSG(("===============================================================================\n"
455 "Dram Type= %d, Freq= %u, CH_%d, rank %d\n"
456 "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n"
457 "===============================================================================\n",
458 p->dram_type,
459 p->frequency,
460 p->channel,
461 p->rank,
462 p->dram_fsp,
463 p->odt_onoff,
464 p->dram_cbt_mode[p->rank],
465 vGet_Div_Mode(p)));
466 #endif
467 }
468
469 #if 0
470 void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p)
471 {
472 mcSHOW_DBG_MSG5(("\n\nDram type:"));
473
474 switch (p->dram_type)
475 {
476 case TYPE_LPDDR4:
477 mcSHOW_DBG_MSG5(("LPDDR4\t"));
478 break;
479
480 case TYPE_LPDDR4X:
481 mcSHOW_DBG_MSG5(("LPDDR4X\t"));
482 break;
483
484 case TYPE_LPDDR4P:
485 mcSHOW_DBG_MSG5(("LPDDR4P\t"));
486 break;
487 }
488
489 mcSHOW_DBG_MSG5(("Freq: %d, FreqGroup %u, channel %d, rank %d\n"
490 "dram_fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n\n",
491 p->frequency, p->freqGroup, p->channel, p->rank,
492 p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p)));
493
494 return;
495 }
496 #endif
497
GetFreqBySel(DRAMC_CTX_T * p,DRAM_PLL_FREQ_SEL_T sel)498 U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
499 {
500 U16 u2freq=0;
501
502 switch(sel)
503 {
504 case LP4_DDR4266:
505 u2freq=2133;
506 break;
507 case LP4_DDR3733:
508 u2freq=1866;
509 break;
510 case LP4_DDR3200:
511 u2freq=1600;
512 break;
513 case LP4_DDR2667:
514 u2freq=1333;
515 break;
516 case LP4_DDR2400:
517 u2freq=1200;
518 break;
519 case LP4_DDR1866:
520 u2freq=933;
521 break;
522 case LP4_DDR1600:
523 u2freq=800;
524 break;
525 case LP4_DDR1200:
526 u2freq=600;
527 break;
528 case LP4_DDR800:
529 u2freq=400;
530 break;
531 case LP4_DDR400:
532 u2freq=200;
533 break;
534
535 case LP5_DDR6400:
536 u2freq=3200;
537 break;
538 case LP5_DDR6000:
539 u2freq=3000;
540 break;
541 case LP5_DDR5500:
542 u2freq=2750;
543 break;
544 case LP5_DDR4800:
545 u2freq=2400;
546 break;
547 case LP5_DDR4266:
548 u2freq=2133;
549 break;
550 case LP5_DDR3733:
551 u2freq=1866;
552 break;
553 case LP5_DDR3200:
554 u2freq=1600;
555 break;
556 case LP5_DDR2400:
557 u2freq=1200;
558 break;
559 case LP5_DDR1600:
560 u2freq=800;
561 break;
562 case LP5_DDR1200:
563 u2freq=600;
564 break;
565 case LP5_DDR800:
566 u2freq=400;
567 break;
568
569 default:
570 mcSHOW_ERR_MSG(("[GetFreqBySel] freq sel is incorrect !!!\n"));
571 break;
572 }
573
574 return u2freq;
575 }
576
GetSelByFreq(DRAMC_CTX_T * p,U16 u2freq)577 DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq)
578 {
579 DRAM_PLL_FREQ_SEL_T sel=0;
580
581 switch(u2freq)
582 {
583 case 2133:
584 sel=LP4_DDR4266;
585 break;
586 case 1866:
587 sel=LP4_DDR3733;
588 break;
589 case 1600:
590 sel=LP4_DDR3200;
591 break;
592 case 1333:
593 sel=LP4_DDR2667;
594 break;
595 case 1200:
596 sel=LP4_DDR2400;
597 break;
598 case 933:
599 sel=LP4_DDR1866;
600 break;
601 case 800:
602 sel=LP4_DDR1600;
603 break;
604 case 600:
605 sel=LP4_DDR1200;
606 break;
607 case 400:
608 sel=LP4_DDR800;
609 break;
610 case 200:
611 sel=LP4_DDR400;
612 break;
613 default:
614 mcSHOW_ERR_MSG(("[GetSelByFreq] sel is incorrect !!!\n"));
615 break;
616 }
617
618 return sel;
619 }
620
DDRPhyFreqSel(DRAMC_CTX_T * p,DRAM_PLL_FREQ_SEL_T sel)621 void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
622 {
623 p->freq_sel = sel;
624 p->frequency = GetFreqBySel(p, sel);
625
626 {
627 p->dram_fsp = (p->frequency < LP4_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
628 p->odt_onoff = (p->frequency < LP4_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
629 }
630
631 if (p->dram_type == TYPE_LPDDR4P)
632 p->odt_onoff = ODT_OFF;
633
634 setFreqGroup(p);
635
636 //p->DBI_onoff = p->odt_onoff;
637 }
638
639
u2DFSGetHighestFreq(DRAMC_CTX_T * p)640 U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p)
641 {
642 U8 u1ShuffleIdx = 0;
643 U16 u2Freq=0;
644 static U16 u2FreqMax=0;
645
646 if ((u2FreqMax == 0) || (gUpdateHighestFreq == TRUE))
647 {
648 gUpdateHighestFreq = FALSE;
649 u2FreqMax = 0;
650 for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
651 {
652 u2Freq = GetFreqBySel(p, gFreqTbl[u1ShuffleIdx].freq_sel);
653 if(u2FreqMax < u2Freq)
654 u2FreqMax = u2Freq;
655 }
656 }
657
658 return u2FreqMax;
659 }
660
GetEyeScanEnable(DRAMC_CTX_T * p,U8 get_type)661 U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type)
662 {
663 #if ENABLE_EYESCAN_GRAPH
664 #if (fcFOR_CHIP_ID == fcA60868)
665
666 if (get_type == EYESCAN_TYPE_CBT)
667 if (ENABLE_EYESCAN_CBT==1) return ENABLE;
668
669
670 if (get_type == EYESCAN_TYPE_RX)
671 if (ENABLE_EYESCAN_RX==1) return ENABLE;
672
673
674 if (get_type == EYESCAN_TYPE_TX)
675 if (ENABLE_EYESCAN_TX==1) return ENABLE;
676
677 #else
678
679 if (get_type == EYESCAN_TYPE_CBT)
680 {
681 if (gCBT_EYE_Scan_flag==DISABLE) return DISABLE;
682 if (gCBT_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE;
683 if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE;
684 if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE;
685 }
686
687
688 if (get_type == EYESCAN_TYPE_RX)
689 {
690 if (gRX_EYE_Scan_flag==DISABLE) return DISABLE;
691 if (gRX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE;
692 if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE;
693 if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE;
694 }
695
696
697 if (get_type == EYESCAN_TYPE_TX)
698 {
699 if (gTX_EYE_Scan_flag==DISABLE) return DISABLE;
700 if (gTX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE;
701 if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE;
702 if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE;
703 }
704
705 #endif
706 #endif
707
708 return DISABLE;
709 }
710
DramcWriteDBIOnOff(DRAMC_CTX_T * p,U8 onoff)711 void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
712 {
713
714 vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, onoff, SHU_TX_SET0_DBIWR);
715 mcSHOW_DBG_MSG2(("DramC Write-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off")));
716 }
717
DramcReadDBIOnOff(DRAMC_CTX_T * p,U8 onoff)718 void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
719 {
720
721 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, onoff, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
722 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, onoff, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
723 mcSHOW_DBG_MSG2(("DramC Read-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off")));
724 }
725 #if ENABLE_READ_DBI
SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T * p,U8 u1fsp,U8 onoff)726 void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
727 {
728 #if MRW_CHECK_ONLY
729 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
730 #endif
731 //mcSHOW_DBG_MSG(("--Fsp%d --\n", p->dram_fsp));
732
733
734 u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0xbf) | (onoff << 6));
735 DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]);
736 }
737 #endif
738
739 #if ENABLE_WRITE_DBI
SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T * p,U8 u1fsp,U8 onoff)740 void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
741 {
742 #if MRW_CHECK_ONLY
743 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
744 #endif
745
746 u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0x7F) | (onoff << 7));
747 DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]);
748 }
749 #endif
750
751 #if 0
752 static void AutoRefreshCKEOff(DRAMC_CTX_T *p)
753 {
754 U32 u4backup_broadcast= GetDramcBroadcast();
755
756 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
757
758 mcSHOW_DBG_MSG(("AutoRefreshCKEOff AutoREF OFF\n"));
759 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS);
760 mcDELAY_US(3);
761 mcSHOW_DBG_MSG(("DDRPhyPLLSetting-CKEOFF\n"));
762
763 CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL);
764
765 mcDELAY_US(1);
766
767
768 DramcBroadcastOnOff(u4backup_broadcast);
769 }
770 #endif
DramCLKAlwaysOnOff(DRAMC_CTX_T * p,U8 option,CHANNEL_RANK_SEL_T WriteChannelNUM)771 void DramCLKAlwaysOnOff(DRAMC_CTX_T *p, U8 option, CHANNEL_RANK_SEL_T WriteChannelNUM)
772 {
773 if (WriteChannelNUM == TO_ALL_CHANNEL) {
774 vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
775 P_Fld(option, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
776 P_Fld(option, DRAMC_PD_CTRL_TCKFIXON));
777 } else {
778 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL),
779 P_Fld(option, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
780 P_Fld(option, DRAMC_PD_CTRL_TCKFIXON));
781 }
782 }
783
CKEFixOnOff(DRAMC_CTX_T * p,U8 u1RankIdx,CKE_FIX_OPTION option,CHANNEL_RANK_SEL_T WriteChannelNUM)784 void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CHANNEL_RANK_SEL_T WriteChannelNUM)
785 {
786 U8 u1CKEOn, u1CKEOff;
787
788 if (option == CKE_DYNAMIC)
789 {
790 u1CKEOn = u1CKEOff = 0;
791 }
792 else
793 {
794 u1CKEOn = option;
795 u1CKEOff = (1 - option);
796 }
797
798 if (WriteChannelNUM == TO_ALL_CHANNEL)
799 {
800 if((u1RankIdx == RANK_0)||(u1RankIdx == TO_ALL_RANK))
801 {
802 vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(u1CKEOff, CKECTRL_CKEFIXOFF)
803 | P_Fld(u1CKEOn, CKECTRL_CKEFIXON));
804 }
805
806 if(u1RankIdx == RANK_1||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
807 {
808 vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(u1CKEOff, CKECTRL_CKE1FIXOFF)
809 | P_Fld(u1CKEOn, CKECTRL_CKE1FIXON));
810 }
811 }
812 else
813 {
814 if((u1RankIdx == RANK_0) || (u1RankIdx == TO_ALL_RANK))
815 {
816 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(u1CKEOff, CKECTRL_CKEFIXOFF)
817 | P_Fld(u1CKEOn, CKECTRL_CKEFIXON));
818 }
819
820 if((u1RankIdx == RANK_1) ||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
821 {
822 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(u1CKEOff, CKECTRL_CKE1FIXOFF)
823 | P_Fld(u1CKEOn, CKECTRL_CKE1FIXON));
824 }
825 }
826 }
827
828
vAutoRefreshSwitch(DRAMC_CTX_T * p,U8 option)829 void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option)
830 {
831 if (option == ENABLE)
832 {
833
834 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_REFDIS);
835 }
836 else
837 {
838
839 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS);
840
841
842 mcDELAY_US(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_QUEUE_CNT) * 4);
843 }
844 }
845
846
vCKERankCtrl(DRAMC_CTX_T * p,CKE_CTRL_MODE_T CKECtrlMode)847 void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode)
848 {
849
850 typedef struct
851 {
852 U8 u1CKE2Rank: Fld_wid(RKCFG_CKE2RANK);
853 U8 u1CKE2Rank_Opt :Fld_wid(CKECTRL_CKE2RANK_OPT);
854 U8 u1CKE2Rank_Opt2 :Fld_wid(CKECTRL_CKE2RANK_OPT2);
855 U8 u1CKE2Rank_Opt3: Fld_wid(CKECTRL_CKE2RANK_OPT3);
856 U8 u1CKE2Rank_Opt5: Fld_wid(CKECTRL_CKE2RANK_OPT5);
857 U8 u1CKE2Rank_Opt6: Fld_wid(CKECTRL_CKE2RANK_OPT6);
858 U8 u1CKE2Rank_Opt7: Fld_wid(CKECTRL_CKE2RANK_OPT7);
859 U8 u1CKE2Rank_Opt8: Fld_wid(CKECTRL_CKE2RANK_OPT8);
860 U8 u1CKETimer_Sel: Fld_wid(CKECTRL_CKETIMER_SEL);
861 U8 u1FASTWake: Fld_wid(SHU_DCM_CTRL0_FASTWAKE);
862 U8 u1FASTWake2: Fld_wid(SHU_DCM_CTRL0_FASTWAKE2);
863 U8 u1FastWake_Sel: Fld_wid(CKECTRL_FASTWAKE_SEL);
864 U8 u1CKEWake_Sel: Fld_wid(CKECTRL_CKEWAKE_SEL);
865 U8 u1ClkWiTrfc: Fld_wid(ACTIMING_CTRL_CLKWITRFC);
866 } CKE_CTRL_T;
867
868
869 CKE_CTRL_T CKE_Mode, CKE_Rank_Independent = { .u1CKE2Rank = 0, .u1CKE2Rank_Opt3 = 0, .u1CKE2Rank_Opt2 = 1,
870 .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 1, .u1CKE2Rank_Opt8 = 0,
871 .u1CKETimer_Sel = 0, .u1FASTWake = 1, .u1FASTWake2 = 1, .u1FastWake_Sel = 1, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0
872 },
873 CKE_Rank_Dependent = { .u1CKE2Rank = 1, .u1CKE2Rank_Opt3 = 0,
874 .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 0, .u1CKE2Rank_Opt8 = 0, .u1CKETimer_Sel = 1,
875 .u1FASTWake = 1, .u1FASTWake2 = 0, .u1FastWake_Sel = 0, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0
876 };
877
878 CKE_Mode = (CKECtrlMode == CKE_RANK_INDEPENDENT)? CKE_Rank_Independent: CKE_Rank_Dependent;
879
880
881 vIO32WriteFldAlign_All(DRAMC_REG_RKCFG, CKE_Mode.u1CKE2Rank, RKCFG_CKE2RANK);
882 vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(CKE_Mode.u1CKE2Rank_Opt3, CKECTRL_CKE2RANK_OPT3)
883 | P_Fld(CKE_Mode.u1CKE2Rank_Opt, CKECTRL_CKE2RANK_OPT)
884 | P_Fld(CKE_Mode.u1CKE2Rank_Opt2, CKECTRL_CKE2RANK_OPT2)
885 | P_Fld(CKE_Mode.u1CKE2Rank_Opt5, CKECTRL_CKE2RANK_OPT5)
886 | P_Fld(CKE_Mode.u1CKE2Rank_Opt6, CKECTRL_CKE2RANK_OPT6)
887 | P_Fld(CKE_Mode.u1CKE2Rank_Opt7, CKECTRL_CKE2RANK_OPT7)
888 | P_Fld(CKE_Mode.u1CKE2Rank_Opt8, CKECTRL_CKE2RANK_OPT8)
889 | P_Fld(CKE_Mode.u1CKETimer_Sel, CKECTRL_CKETIMER_SEL)
890 | P_Fld(CKE_Mode.u1FastWake_Sel, CKECTRL_FASTWAKE_SEL)
891 | P_Fld(CKE_Mode.u1CKEWake_Sel, CKECTRL_CKEWAKE_SEL));
892
893 vIO32WriteFldMulti_All(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(CKE_Mode.u1FASTWake, SHU_DCM_CTRL0_FASTWAKE) | P_Fld(CKE_Mode.u1FASTWake2, SHU_DCM_CTRL0_FASTWAKE2));
894
895 vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, CKE_Mode.u1ClkWiTrfc, ACTIMING_CTRL_CLKWITRFC);
896 }
897
898
899 #define MAX_CMP_CPT_WAIT_LOOP 100000
DramcSetRWOFOEN(DRAMC_CTX_T * p,U8 u1onoff)900 static void DramcSetRWOFOEN(DRAMC_CTX_T *p, U8 u1onoff)
901 {
902 U32 u4loop_count = 0;
903
904 {
905 while(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REQQ_EMPTY) != 1)
906 {
907 mcDELAY_US(1);
908 u4loop_count ++;
909
910 if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
911 {
912 mcSHOW_ERR_MSG(("RWOFOEN timout! queue is not empty\n"));
913 #if __ETT__
914 while(1);
915 #else
916 break;
917 #endif
918 }
919 }
920 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SCHEDULER_COM), u1onoff, SCHEDULER_COM_RWOFOEN);
921 }
922 }
923
924
925 //static void DramcEngine2CleanWorstSiPattern(DRAMC_CTX_T *p)
926 //{
927 // vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
928 // P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
929 // P_Fld(0, TEST2_A3_HFIDPAT) |
930 // P_Fld(0, TEST2_A3_TEST_AID_EN));
931 //}
932
933
DramcEngine2SetUiShift(DRAMC_CTX_T * p,U8 option)934 static void DramcEngine2SetUiShift(DRAMC_CTX_T *p, U8 option)
935 {
936 if(option == ENABLE)
937 {
938 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0),
939 P_Fld(1, TEST2_A0_TA2_LOOP_EN) |
940 P_Fld(3, TEST2_A0_LOOP_CNT_INDEX));
941 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
942 P_Fld(1, TEST2_A3_TEST2_PAT_SHIFT) |
943 P_Fld(0, TEST2_A3_PAT_SHIFT_SW_EN));
944 }
945 else
946 {
947 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0),
948 P_Fld(0, TEST2_A0_TA2_LOOP_EN) |
949 P_Fld(0, TEST2_A0_LOOP_CNT_INDEX));
950 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
951 P_Fld(0, TEST2_A3_TEST2_PAT_SHIFT));
952 }
953 }
954
955
DramcSetRankEngine2(DRAMC_CTX_T * p,U8 u1RankSel)956 void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel)
957 {
958
959 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), 1, TEST2_A3_ADRDECEN_TARKMODE);
960
961
962 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAGENTRKSEL);
963
964
965 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), u1RankSel, TEST2_A4_TESTAGENTRK);
966 }
967
968
DramcEngine2SetPat(DRAMC_CTX_T * p,U8 u1TestPat,U8 u1LoopCnt,U8 u1Len1Flag,U8 u1EnableUiShift)969 void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift)
970 {
971
972 if ((u1TestPat == TEST_XTALK_PATTERN) || (u1TestPat == TEST_SSOXTALK_PATTERN))
973 {
974
975 if (u1Len1Flag != 0)
976 {
977 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
978 P_Fld(1, TEST2_A4_TEST_REQ_LEN1));
979 DramcSetRWOFOEN(p, 0);
980
981 }
982 else
983 {
984 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
985 P_Fld(0, TEST2_A4_TEST_REQ_LEN1));
986 DramcSetRWOFOEN(p, 1);
987 }
988
989 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
990 P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
991 P_Fld(0, TEST2_A3_HFIDPAT) |
992 P_Fld(0, TEST2_A3_TEST_AID_EN) |
993 P_Fld(0, TEST2_A3_TESTAUDPAT) |
994 P_Fld(u1LoopCnt, TEST2_A3_TESTCNT));
995
996 if (u1TestPat == TEST_SSOXTALK_PATTERN)
997 {
998
999 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1000 P_Fld(1, TEST2_A4_TESTXTALKPAT) |
1001 P_Fld(0, TEST2_A4_TESTAUDMODE) |
1002 P_Fld(0, TEST2_A4_TESTAUDBITINV));
1003
1004
1005 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1006 P_Fld(1, TEST2_A4_TESTSSOPAT) |
1007 P_Fld(0, TEST2_A4_TESTSSOXTALKPAT));
1008 }
1009 else
1010 {
1011
1012 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1013 P_Fld(1, TEST2_A4_TESTXTALKPAT) |
1014 P_Fld(0, TEST2_A4_TESTAUDMODE) |
1015 P_Fld(0, TEST2_A4_TESTAUDBITINV));
1016
1017
1018 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1019 P_Fld(0, TEST2_A4_TESTSSOPAT) |
1020 P_Fld(0, TEST2_A4_TESTSSOXTALKPAT));
1021 }
1022 }
1023 else if (u1TestPat == TEST_AUDIO_PATTERN)
1024 {
1025 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1026 P_Fld(0, TEST2_A4_TEST_REQ_LEN1));
1027
1028 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1029 P_Fld(0x00000011, TEST2_A4_TESTAUDINIT) |
1030 P_Fld(0x0000000d, TEST2_A4_TESTAUDINC) |
1031 P_Fld(0, TEST2_A4_TESTXTALKPAT) |
1032 P_Fld(0, TEST2_A4_TESTAUDMODE) |
1033 P_Fld(1, TEST2_A4_TESTAUDBITINV));
1034
1035
1036 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1037 P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
1038 P_Fld(0, TEST2_A3_HFIDPAT) |
1039 P_Fld(0, TEST2_A3_TEST_AID_EN) |
1040 P_Fld(1, TEST2_A3_TESTAUDPAT) |
1041 P_Fld(u1LoopCnt, TEST2_A3_TESTCNT));
1042 }
1043 else if (u1TestPat == TEST_WORST_SI_PATTERN)
1044 {
1045 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1046 P_Fld(u1Len1Flag, TEST2_A4_TEST_REQ_LEN1)|
1047 P_Fld(0, TEST2_A4_TESTAUDINIT) |
1048 P_Fld(0, TEST2_A4_TESTAUDINC) |
1049 P_Fld(0, TEST2_A4_TESTXTALKPAT) |
1050 P_Fld(0, TEST2_A4_TESTSSOPAT)
1051 );
1052 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1053 P_Fld(0, TEST2_A3_TESTAUDPAT) |
1054 P_Fld(1, TEST2_A3_AUTO_GEN_PAT) |
1055 P_Fld(1, TEST2_A3_HFIDPAT) |
1056 P_Fld(1, TEST2_A3_TEST_AID_EN) |
1057 P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)
1058 );
1059 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x56, TEST2_A2_TEST2_OFF);
1060 }
1061 else
1062 {
1063 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1064 P_Fld(0, TEST2_A4_TEST_REQ_LEN1));
1065
1066 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1067 P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
1068 P_Fld(0, TEST2_A3_HFIDPAT) |
1069 P_Fld(0, TEST2_A3_TEST_AID_EN) |
1070 P_Fld(0, TEST2_A3_TESTAUDPAT) |
1071 P_Fld(u1LoopCnt, TEST2_A3_TESTCNT));
1072 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTXTALKPAT);
1073 }
1074
1075 DramcEngine2SetUiShift(p, u1EnableUiShift);
1076 }
1077
1078 #define CMP_CPT_POLLING_PERIOD 1
1079 #define MAX_CMP_CPT_WAIT_LOOP 100000
DramcEngine2CheckComplete(DRAMC_CTX_T * p,U8 u1status)1080 static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status)
1081 {
1082 U32 u4loop_count = 0;
1083 U32 u4Ta2_loop_count = 0;
1084 U32 u4ShiftUiFlag = 0;
1085
1086 while ((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status)
1087 {
1088 mcDELAY_US(CMP_CPT_POLLING_PERIOD);
1089 u4loop_count++;
1090 if ((u4loop_count > 3) && (u4loop_count <= MAX_CMP_CPT_WAIT_LOOP))
1091 {
1092 //mcSHOW_ERR_MSG(("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count));
1093 }
1094 else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
1095 {
1096
1097 mcSHOW_ERR_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));
1098
1099 //mcFPRINTF((fp_A60501, "fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count));
1100
1101 break;
1102 }
1103 }
1104
1105 u4loop_count = 0;
1106 u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT);
1107 if(u4ShiftUiFlag)
1108 {
1109 while ((u4Ta2_loop_count = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT))) != 8)
1110 {
1111 u4loop_count++;
1112 if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
1113 {
1114 mcSHOW_ERR_MSG(("over MAX_CMP_CPT_WAIT_LOOP[%d] TEST_LOOP_CNT[%d]\n", u4loop_count, u4Ta2_loop_count));
1115 break;
1116 }
1117 }
1118 }
1119 }
1120
DramcEngine2Compare(DRAMC_CTX_T * p,DRAM_TE_OP_T wr)1121 static U32 DramcEngine2Compare(DRAMC_CTX_T *p, DRAM_TE_OP_T wr)
1122 {
1123 U32 u4result = 0xffffffff;
1124 U32 u4loopcount;
1125 U8 u1status = 1;
1126 U32 u4ShiftUiFlag = 0;
1127
1128 u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT);
1129 if (u4loopcount == 1)
1130 u1status = 3;
1131
1132 u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT);
1133
1134 if (wr == TE_OP_WRITE_READ_CHECK)
1135 {
1136 if(!u4ShiftUiFlag)
1137 {
1138
1139 DramcEngine2CheckComplete(p, u1status);
1140
1141
1142 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1143 P_Fld(0, TEST2_A3_TEST2W) |
1144 P_Fld(0, TEST2_A3_TEST2R) |
1145 P_Fld(0, TEST2_A3_TEST1));
1146
1147 mcDELAY_US(1);
1148
1149
1150 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1151 P_Fld(0, TEST2_A3_TEST2W) |
1152 P_Fld(1, TEST2_A3_TEST2R) |
1153 P_Fld(0, TEST2_A3_TEST1));
1154 }
1155 }
1156
1157
1158 DramcEngine2CheckComplete(p, u1status);
1159
1160 //mcDELAY_US(1);
1161
1162 u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & u1status;
1163
1164 return u4result;
1165 }
1166
1167
1168 static U32 uiReg0D0h;
DramcEngine2Init(DRAMC_CTX_T * p,U32 test2_1,U32 test2_2,U8 u1TestPat,U8 u1LoopCnt,U8 u1EnableUiShift)1169 DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift)
1170 {
1171 U8 u1Len1Flag;
1172
1173
1174 if (!p)
1175 {
1176 mcSHOW_ERR_MSG(("context is NULL\n"));
1177 return DRAM_FAIL;
1178 }
1179
1180
1181 // if ((u1LoopCnt > 15) || (u1LoopCnt < 0))
1182 if (u1LoopCnt > 15)
1183 {
1184 mcSHOW_ERR_MSG(("wrong param: u1LoopCnt > 15\n"));
1185 return DRAM_FAIL;
1186 }
1187
1188 u1Len1Flag = (u1TestPat & 0x80) >> 7;
1189 u1TestPat = u1TestPat & 0x7f;
1190
1191 DramcSetRankEngine2(p, p->rank);
1192
1193 uiReg0D0h = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD));
1194 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD),
1195 P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) |
1196 P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) |
1197 P_Fld(0, DUMMY_RD_DUMMY_RD_EN) |
1198 P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) |
1199 P_Fld(0, DUMMY_RD_DMY_RD_DBG) |
1200 P_Fld(0, DUMMY_RD_DMY_WR_DBG));
1201
1202
1203 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1204 P_Fld(0, TEST2_A3_TEST2W) |
1205 P_Fld(0, TEST2_A3_TEST2R) |
1206 P_Fld(0, TEST2_A3_TEST1));
1207
1208
1209 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0),
1210 P_Fld(test2_1 >> 24, TEST2_A0_TEST2_PAT0) |
1211 P_Fld(test2_2 >> 24, TEST2_A0_TEST2_PAT1));
1212
1213 {
1214
1215 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
1216 (test2_1 + 0x10000) & 0x00ffffff, RK_TEST2_A1_TEST2_BASE);
1217 }
1218
1219 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2),
1220 test2_2 & 0x00ffffff, TEST2_A2_TEST2_OFF);
1221
1222
1223 DramcEngine2SetPat(p, u1TestPat, u1LoopCnt, u1Len1Flag, u1EnableUiShift);
1224
1225 return DRAM_OK;
1226 }
1227
1228
DramcEngine2Run(DRAMC_CTX_T * p,DRAM_TE_OP_T wr,U8 u1TestPat)1229 U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat)
1230 {
1231 U32 u4result = 0xffffffff;
1232
1233
1234 if (wr == TE_OP_READ_CHECK)
1235 {
1236 if ((u1TestPat == 1) || (u1TestPat == 2))
1237 {
1238
1239 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAUDMODE);
1240 }
1241
1242
1243 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1244 P_Fld(0, TEST2_A3_TEST2W) |
1245 P_Fld(1, TEST2_A3_TEST2R) |
1246 P_Fld(0, TEST2_A3_TEST1));
1247 }
1248 else if (wr == TE_OP_WRITE_READ_CHECK)
1249 {
1250
1251 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1252 P_Fld(1, TEST2_A3_TEST2W) |
1253 P_Fld(0, TEST2_A3_TEST2R) |
1254 P_Fld(0, TEST2_A3_TEST1));
1255 }
1256 DramcEngine2Compare(p, wr);
1257
1258
1259 mcDELAY_US(1);
1260
1261
1262 u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)));
1263
1264
1265 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
1266 P_Fld(0, TEST2_A3_TEST2W) |
1267 P_Fld(0, TEST2_A3_TEST2R) |
1268 P_Fld(0, TEST2_A3_TEST1));
1269
1270 return u4result;
1271 }
1272
DramcEngine2End(DRAMC_CTX_T * p)1273 void DramcEngine2End(DRAMC_CTX_T *p)
1274 {
1275 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
1276 P_Fld(0, TEST2_A4_TEST_REQ_LEN1));
1277 DramcSetRWOFOEN(p, 1);
1278 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), uiReg0D0h);
1279 }
1280 #if 0
1281
1282 static U32 TestEngineCompare(DRAMC_CTX_T *p)
1283 {
1284 U8 jj;
1285 U32 u4err_value;
1286
1287 if (p->test_pattern <= TEST_XTALK_PATTERN)
1288 {
1289 DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern, 0, TE_NO_UI_SHIFT);
1290 u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern);
1291 DramcEngine2End(p);
1292 }
1293 else if (p->test_pattern == TEST_MIX_PATTERN)
1294 {
1295 DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT);
1296 u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);
1297 DramcEngine2End(p);
1298
1299 DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
1300 u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
1301 DramcEngine2End(p);
1302 }
1303 else
1304 {
1305 mcSHOW_ERR_MSG(("Test pattern error! Using default xtalk pattern\n"));
1306 DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
1307 u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
1308 DramcEngine2End(p);
1309 }
1310 return u4err_value;
1311 }
1312 #endif
1313 #if (fcFOR_CHIP_ID == fcA60868)
1314 #define EMI_APB_BASE 0x10219000
1315 #elif (fcFOR_CHIP_ID == fc8195)
1316 #define EMI_APB_BASE 0x10219000
1317 //#define SUB_EMI_APB_BASE 0x1021D000
1318
1319 #endif
1320
1321 U8 u1MaType = 0x2;
TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p)1322 void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p)
1323 {
1324 U8 u1ChannelIdx = 0;
1325 U8 u1EmiChIdx = 0;
1326 U32 u4matypeR0 = 0, u4matypeR1 = 0;
1327 U32 u4matype = 0;
1328 U32 u4EmiOffset = 0;
1329 DRAM_CHANNEL_T eOriChannel = p->channel;
1330
1331 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1332 {
1333 vSetPHY2ChannelMapping(p, u1ChannelIdx);
1334
1335 u4EmiOffset = 0;
1336 u1EmiChIdx = u1ChannelIdx;
1337 #if (CHANNEL_NUM > 2)
1338 if (channel_num_auxadc > 2) {
1339 if (u1ChannelIdx >= CHANNEL_C)
1340 {
1341 u4EmiOffset = 0x4000;
1342 u1EmiChIdx = u1ChannelIdx-2;
1343 }
1344 }
1345 #endif
1346
1347 u4matype = u4IO32Read4B(EMI_APB_BASE + u4EmiOffset);
1348 u4matypeR0 = ((u4matype >> (4 + u1EmiChIdx * 16)) & 0x3) + 1;
1349 u4matypeR1 = ((u4matype >> (6 + u1EmiChIdx * 16)) & 0x3) + 1;
1350
1351 if(p->support_rank_num==RANK_SINGLE)
1352 {
1353 u4matype = u4matypeR0;
1354 }
1355 else
1356 {
1357 u4matype = (u4matypeR0 > u4matypeR1) ? u4matypeR1 : u4matypeR0;
1358 }
1359 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MATYPE), u4matype, MATYPE_MATYPE);
1360 }
1361 vSetPHY2ChannelMapping(p, eOriChannel);
1362 u1MaType = u4matype;
1363
1364 return;
1365 }
1366
1367
1368 #define TA2_RANK0_ADDRESS (0x40200000)
1369 #define AXI_CHAN_BIT_WIDTH 1
1370 #define OFFSET_OF_RG_BASE_AND_AXI 2
1371 #define LEN1_INTRINSIC_OFFSET 2
1372 #if FOR_DV_SIMULATION_USED
1373 #define TRANSFER_DRAM_ADDR_BY_EMI_API 0
1374 #else
1375 #define TRANSFER_DRAM_ADDR_BY_EMI_API 1
1376 #endif
TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p,U32 len,TA2_RKSEL_TYPE_T rksel_mode)1377 void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode)
1378 {
1379 DRAM_CHANNEL_T eOriChannel = p->channel;
1380 DRAM_RANK_T eOriRank = p->rank;
1381 U32 u4BaseR0, u4BaseR1, u4Offset, u4Addr;
1382 U32 u4matypeR0, u4matypeR1, u4LEN1;
1383 U8 u1ChannelIdx, uiRWOFOEN, u1RkIdx;
1384
1385 u4Addr = TA2_RANK0_ADDRESS & 0x1fffffff;
1386 if (u1IsLP4Family(p->dram_type))
1387 {
1388 #if TRANSFER_DRAM_ADDR_BY_EMI_API
1389 {
1390 dram_addr_t dram_addr;
1391 unsigned long long ull_axi_addr = TA2_RANK0_ADDRESS;
1392
1393 memset(&dram_addr, 0, sizeof(dram_addr));
1394 phy_addr_to_dram_addr(&dram_addr, ull_axi_addr);
1395 u4BaseR0 = ((dram_addr.row << 12) | (dram_addr.bk << 9) | (dram_addr.col >> 1)) >> 3;
1396 }
1397 #else
1398
1399 u4BaseR0 = (((u4Addr & ~0x1ff) >> AXI_CHAN_BIT_WIDTH) | (u4Addr & 0xff)) >> (OFFSET_OF_RG_BASE_AND_AXI + 3);
1400 #endif
1401 //mcSHOW_DBG_MSG(("===u4BaseR0 = 0x%x\n", u4BaseR0));
1402
1403 u4Offset = len >> (AXI_CHAN_BIT_WIDTH + 5);
1404 }
1405 else
1406 {
1407 u4BaseR0 = u4Addr >> 4;
1408 if (rksel_mode == TA2_RKSEL_XRT)
1409 {
1410 u4Offset = len >> 4;
1411 }
1412 else
1413 {
1414 u4Offset = (len >> 4) >> 1;
1415 }
1416 }
1417 u4BaseR1 = u4BaseR0;
1418
1419 u4matypeR0 = ((u4IO32Read4B(EMI_APB_BASE) >> 4) & 0x3) + 1;
1420 u4matypeR1 = ((u4IO32Read4B(EMI_APB_BASE) >> 6) & 0x3) + 1;
1421 if (u4matypeR0 != u4matypeR1)
1422 {
1423 (u4matypeR0 > u4matypeR1)? (u4BaseR0 >>= 1): (u4BaseR1 >>= 1);
1424 u4Offset >>= 1;
1425 }
1426
1427 u4Offset = (u4Offset == 0) ? 1 : u4Offset;
1428
1429 u4LEN1 = u4IO32ReadFldAlign(DRAMC_REG_TEST2_A4, TEST2_A4_TEST_REQ_LEN1);
1430 if(u4LEN1)
1431 {
1432 u4Offset = u4Offset - LEN1_INTRINSIC_OFFSET;
1433 }
1434
1435 #if ENABLE_EMI_LPBK_TEST && EMI_USE_TA2
1436 if (gEmiLpbkTest)
1437 {
1438 u4matypeR0 = 2;
1439 u4matypeR1 = 2;
1440 u4Offset = 3;
1441 //u4Offset = 6;
1442 }
1443 #endif
1444
1445 if (TA2_RKSEL_XRT == rksel_mode)
1446 {
1447
1448 uiRWOFOEN = 0;
1449 mcSHOW_DBG_MSG2(("=== TA2 XRT R2R/W2W\n"));
1450 }
1451 else
1452 {
1453 uiRWOFOEN = 1;
1454 #if !ENABLE_EMI_LPBK_TEST
1455 mcSHOW_DBG_MSG2(("=== TA2 HW\n"));
1456 #endif
1457 }
1458 #if !ENABLE_EMI_LPBK_TEST
1459 mcSHOW_DBG_MSG2(("=== OFFSET:0x%x\n", u4Offset));
1460 #endif
1461 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1462 {
1463 p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
1464
1465 for(u1RkIdx = 0; u1RkIdx < p->support_rank_num; u1RkIdx++)
1466 {
1467 p->rank = (DRAM_RANK_T)u1RkIdx;
1468 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), u4BaseR0, RK_TEST2_A1_TEST2_BASE);
1469 }
1470 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), u4Offset, TEST2_A2_TEST2_OFF);
1471 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), rksel_mode, TEST2_A4_TESTAGENTRKSEL);
1472 DramcSetRWOFOEN(p, uiRWOFOEN);
1473 }
1474 p->channel = eOriChannel;
1475 p->rank = eOriRank;
1476 //TA2_Test_Run_Time_HW_Set_Column_Num(p);
1477
1478 return;
1479 }
1480 #if ETT_MINI_STRESS_USE_TA2_LOOP_MODE
1481 #define TA2_PAT TEST_WORST_SI_PATTERN
1482 #else
1483 #define TA2_PAT TEST_XTALK_PATTERN
1484 #endif
1485
TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T * p,U8 PatSwitch)1486 void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch)
1487 {
1488 static U8 u1Pat = TA2_PAT;
1489 U8 u1ChannelIdx = 0;
1490 DRAM_CHANNEL_T eOriChannel = p->channel;
1491
1492 #if !ENABLE_EMI_LPBK_TEST
1493 mcSHOW_DBG_MSG2(("TA2 PAT: %d\n", u1Pat));
1494 #endif
1495 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1496 {
1497 p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
1498 DramcEngine2SetPat(p, u1Pat, p->support_rank_num - 1, 0, TE_NO_UI_SHIFT);
1499 }
1500 p->channel = eOriChannel;
1501
1502 #if !ETT_MINI_STRESS_USE_TA2_LOOP_MODE
1503 {
1504 U32 u4Value = 0;
1505 u4Value = (u1Pat == TEST_WORST_SI_PATTERN) ? 1 : 0;
1506 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_TA2_LOOP_EN);
1507 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_LOOP_NV_END);
1508 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_ERR_BREAK_EN);
1509 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, u4Value, TEST2_A4_TEST_REQ_LEN1);
1510 }
1511 #endif
1512
1513 if (PatSwitch)
1514 u1Pat = (u1Pat + 1) % 4;
1515
1516 return;
1517 }
1518 #if 0
1519 static void TA2_Test_Run_Time_HW_Read(DRAMC_CTX_T * p, U8 u1Enable)
1520 {
1521 DRAM_CHANNEL_T eOriChannel = p->channel;
1522 U8 u1ChannelIdx;
1523
1524 mcSHOW_DBG_MSG2(("\nTA2 Trigger Read\n"));
1525 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1526 {
1527 p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
1528 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u1Enable, TEST2_A3_TEST2R);
1529 }
1530 p->channel = eOriChannel;
1531 return;
1532 }
1533 #endif
TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p,U8 u1Enable)1534 void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable)
1535 {
1536 DRAM_CHANNEL_T eOriChannel = p->channel;
1537 U8 u1ChannelIdx;
1538
1539 #if !ENABLE_EMI_LPBK_TEST
1540 mcSHOW_DBG_MSG2(("\nTA2 Trigger Write\n"));
1541 #endif
1542 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1543 {
1544 p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
1545 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u1Enable, TEST2_A3_TEST2W);
1546 }
1547 p->channel = eOriChannel;
1548 return;
1549 }
1550
1551 #if defined(RELEASE) && defined(DEVIATION)
1552 #undef mcSHOW_JV_LOG_MSG
1553 #define mcSHOW_JV_LOG_MSG(_x_) opt_print _x_
1554 #endif
TA2_Show_Cnt(DRAMC_CTX_T * p,U32 u4ErrorValue)1555 static void TA2_Show_Cnt(DRAMC_CTX_T * p, U32 u4ErrorValue)
1556 {
1557 static U32 err_count = 0;
1558 static U32 pass_count = 0;
1559 U8 u1RankIdx = 0;
1560
1561 for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
1562 {
1563 if (u4ErrorValue & (1 << u1RankIdx))
1564 {
1565 err_count++;
1566 mcSHOW_DBG_MSG2(("HW channel(%d) Rank(%d), TA2 failed, pass_cnt:%d, err_cnt:%d, err_bit:0x%x\n", p->channel, u1RankIdx, pass_count, err_count, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
1567 }
1568 else
1569 {
1570 pass_count++;
1571 mcSHOW_DBG_MSG2(("HW channel(%d) Rank(%d), TA2 pass, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count));
1572 }
1573 }
1574 }
1575
1576
1577 #if ETT_MINI_STRESS_USE_TA2_LOOP_MODE
1578 #if 0
1579 static void TA2_Test_Run_Time_Stop_Loop_Mode(DRAMC_CTX_T * p)
1580 {
1581 U8 u1ChannelIdx = 0;
1582 U8 u1status = (p->support_rank_num == 2) ? 3 : 1;
1583 U32 u4loop_count = 0;
1584 DRAM_CHANNEL_T eOriChannel = p->channel;
1585
1586 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1587 {
1588 vSetPHY2ChannelMapping(p, u1ChannelIdx);
1589
1590
1591 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);
1592
1593
1594 while (((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status) || (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)))
1595 {
1596 mcDELAY_US(CMP_CPT_POLLING_PERIOD);
1597 u4loop_count++;
1598 if ((u4loop_count > 3) && (u4loop_count <= MAX_CMP_CPT_WAIT_LOOP))
1599 {
1600 //mcSHOW_ERR_MSG(("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count));
1601 }
1602 else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
1603 {
1604 mcSHOW_ERR_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));
1605 break;
1606 }
1607 }
1608
1609
1610 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
1611 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_TA2_LOOP_EN);
1612 }
1613 vSetPHY2ChannelMapping(p, eOriChannel);
1614 }
1615
1616 static void TA2_Test_Run_Time_Start_Loop_Mode(DRAMC_CTX_T *p)
1617 {
1618 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_TA2_LOOP_EN);
1619 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_LOOP_NV_END);
1620 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_ERR_BREAK_EN);
1621 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 1, TEST2_A4_TEST_REQ_LEN1);
1622 }
1623
1624 static U32 TA2_Test_Run_Time_Err_Status(DRAMC_CTX_T *p)
1625 {
1626 static U32 err_count = 0;
1627 static U32 pass_count = 0;
1628 U32 u4Value = 0xffffffff;
1629 U32 u4ErrorValue = 0;
1630 U32 u4AllErrorValue = 0;
1631 U8 u1ChannelIdx = 0;
1632 DRAM_CHANNEL_T bkchannel = p->channel;
1633
1634 for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
1635 {
1636 vSetPHY2ChannelMapping(p, u1ChannelIdx);
1637 u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3;
1638 //mcSHOW_DBG_MSG(("CMP_ERR_RK0/1:0x%x ", u4ErrorValue));
1639 TA2_Show_Cnt(p, u4ErrorValue);
1640 u4AllErrorValue |= u4ErrorValue;
1641
1642 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT));
1643 mcSHOW_DBG_MSG2(("CH[%d] LOOP_CNT:0x%x \n", u1ChannelIdx, u4Value));
1644 }
1645 vSetPHY2ChannelMapping(p, bkchannel);
1646 return u4AllErrorValue;
1647 }
1648 #endif
TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)1649 U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
1650 {
1651 U8 u1ChannelIdx = 0;
1652 U32 u4ErrorValue = 0;
1653 U32 bit_error = 0;
1654 DRAM_CHANNEL_T eOriChannel = p->channel;
1655
1656 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1657 {
1658 vSetPHY2ChannelMapping(p, u1ChannelIdx);
1659 u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK);
1660
1661 if (u4ErrorValue & 0x3)
1662 {
1663 mcSHOW_DBG_MSG2(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
1664 #if defined(SLT)
1665 mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
1666 while (1);
1667 #endif
1668 }
1669 TA2_Show_Cnt(p, u4ErrorValue);
1670
1671 bit_error |= u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR));
1672 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
1673 }
1674 vSetPHY2ChannelMapping(p, eOriChannel);
1675
1676 return bit_error;
1677 }
1678 #else
TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)1679 U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
1680 {
1681 U8 u1ChannelIdx = 0;
1682 U32 u4ErrorValue = 0;
1683 U32 u4Ta2LoopEn = 0;
1684 U32 u4loopcount = 0;
1685 U8 u1status = 0;
1686 U32 bit_error = 0;
1687 static U32 err_count = 0;
1688 static U32 pass_count = 0;
1689 DRAM_CHANNEL_T eOriChannel = p->channel;
1690
1691 for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1692 {
1693 vSetPHY2ChannelMapping(p, u1ChannelIdx);
1694 u4Ta2LoopEn = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), TEST2_A0_TA2_LOOP_EN);
1695 //mcSHOW_DBG_MSG(("### u4Ta2LoopEn:%d ### \n", u4Ta2LoopEn));
1696
1697 if(u4Ta2LoopEn)
1698 {
1699 u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT);
1700 if (u4loopcount == 1)
1701 u1status = 3;
1702
1703 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);
1704 DramcEngine2CheckComplete(p, u1status);
1705 //mcSHOW_DBG_MSG(("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));
1706 u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3;
1707 }
1708 else
1709 u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK);
1710
1711 if (u4ErrorValue & 0x3)
1712 {
1713 mcSHOW_DBG_MSG2(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
1714 #if defined(SLT)
1715 mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
1716 while (1);
1717 #endif
1718 }
1719 TA2_Show_Cnt(p, u4ErrorValue);
1720
1721 bit_error |= u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR));
1722 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
1723 }
1724 vSetPHY2ChannelMapping(p, eOriChannel);
1725
1726 return bit_error;
1727 }
1728 #endif
1729 #if defined(RELEASE) && defined(DEVIATION)
1730 #undef mcSHOW_JV_LOG_MSG
1731 #define mcSHOW_JV_LOG_MSG(_x_)
1732 #endif
1733
1734
TA2_Test_Run_Time_HW(DRAMC_CTX_T * p)1735 void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p)
1736 {
1737 DRAM_CHANNEL_T channel_bak = p->channel;
1738 DRAM_RANK_T rank_bak = p->rank;
1739
1740 TA2_Test_Run_Time_HW_Presetting(p, 0x10000, TA2_RKSEL_HW);
1741 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
1742 TA2_Test_Run_Time_HW_Write(p, ENABLE);
1743 //mcDELAY_MS(1);
1744 TA2_Test_Run_Time_HW_Status(p);
1745
1746 p->channel = channel_bak;
1747 p->rank = rank_bak;
1748 return;
1749 }
1750
Temp_TA2_Test_After_K(DRAMC_CTX_T * p)1751 void Temp_TA2_Test_After_K(DRAMC_CTX_T * p)
1752 {
1753 DRAM_CHANNEL_T channel_bak = p->channel;
1754 DRAM_RANK_T rank_bak = p->rank;
1755
1756 do {
1757 TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
1758 TA2_Test_Run_Time_HW_Presetting(p, 0x200000, TA2_RKSEL_HW);
1759 TA2_Test_Run_Time_HW_Write(p, ENABLE);
1760 TA2_Test_Run_Time_HW_Status(p);
1761 }while(1);
1762
1763 p->channel = channel_bak;
1764 p->rank = rank_bak;
1765 return;
1766 }
1767
DramcFetchGlobalMR(DRAMC_CTX_T * p,U8 mr_idx)1768 static U8 *DramcFetchGlobalMR(DRAMC_CTX_T *p, U8 mr_idx)
1769 {
1770 U8 *pMRGlobalValue = NULL;
1771
1772 switch (mr_idx)
1773 {
1774 case 13: pMRGlobalValue = &u1MR13Value[p->rank]; break;
1775 case 26: pMRGlobalValue = &u1MR26Value[p->rank]; break;
1776 case 30: pMRGlobalValue = &u1MR30Value[p->rank]; break;
1777 default:
1778 mcSHOW_ERR_MSG(("%s NULL\n", __func__));
1779 #if __ETT__
1780 while(1);
1781 #endif
1782 break;
1783 }
1784
1785 return pMRGlobalValue;
1786 }
1787
1788 #if MRW_BACKUP
DramcMRWriteBackup(DRAMC_CTX_T * p,U8 u1MRIdx,U8 u1Rank)1789 U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank)
1790 {
1791 U8 u1Value=0xff;
1792 U8 u1Fsp;
1793 U8 u1MRBackup_ERR_Flag=0, u1backupRK=p->rank;
1794 U16 u2Offset=0x0;
1795 REG_TRANSFER_T TransferReg;
1796
1797 u1Fsp = FSP_0;
1798
1799 {
1800 switch (u1MRIdx)
1801 {
1802 case 1:
1803 case 2:
1804 case 3:
1805 case 11:
1806 case 12:
1807 case 14:
1808 case 22:
1809 u1Fsp = gFSPWR_Flag[u1Rank];
1810 break;
1811 }
1812 }
1813
1814 if (u1Fsp == FSP_0)
1815 {
1816 switch (u1MRIdx)
1817 {
1818 case 1:
1819 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
1820 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR1;
1821 break;
1822 case 2:
1823 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
1824 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR2;
1825 break;
1826 case 3:
1827 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
1828 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR3;
1829 break;
1830 case 4:
1831 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
1832 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR4;
1833 break;
1834 case 9:
1835 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
1836 TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR9;
1837 break;
1838 case 10:
1839 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
1840 TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR10;
1841 break;
1842 case 11:
1843 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
1844 TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR11;
1845 break;
1846 case 12:
1847 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
1848 TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR12;
1849 break;
1850 case 13:
1851 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
1852 TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR13;
1853 break;
1854 case 14:
1855 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
1856 TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR14;
1857 break;
1858 case 15:
1859 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
1860 TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR15;
1861 break;
1862 case 16:
1863 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
1864 TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR16;
1865 break;
1866 case 17:
1867 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
1868 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR17;
1869 break;
1870 case 18:
1871 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
1872 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR18;
1873 break;
1874 case 19:
1875 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
1876 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR19;
1877 break;
1878 case 20:
1879 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
1880 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR20;
1881 break;
1882 case 21:
1883 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
1884 TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR21;
1885 break;
1886 case 22:
1887 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
1888 TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR22;
1889 break;
1890 case 23:
1891 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
1892 TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR23;
1893 break;
1894 case 24:
1895 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
1896 TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR24;
1897 break;
1898 case 25:
1899 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
1900 TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR25;
1901 break;
1902 case 26:
1903 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
1904 TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR26;
1905 break;
1906 case 27:
1907 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
1908 TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR27;
1909 break;
1910 case 28:
1911 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
1912 TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR28;
1913 break;
1914 case 30:
1915 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
1916 TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR30;
1917 break;
1918 case 31:
1919 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
1920 TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR31;
1921 break;
1922 case 32:
1923 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
1924 TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR32;
1925 break;
1926 case 33:
1927 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
1928 TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR33;
1929 break;
1930 case 34:
1931 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
1932 TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR34;
1933 break;
1934 case 37:
1935 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
1936 TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR37;
1937 break;
1938 case 39:
1939 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
1940 TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR39;
1941 break;
1942 case 40:
1943 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
1944 TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR40;
1945 break;
1946 case 41:
1947 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
1948 TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR41;
1949 break;
1950 case 42:
1951 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
1952 TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR42;
1953 break;
1954 case 46:
1955 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
1956 TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR46;
1957 break;
1958 case 48:
1959 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
1960 TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR48;
1961 break;
1962 case 51:
1963 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_09_RK0_FSP0;
1964 TransferReg.u4Fld = MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR51;
1965 break;
1966 case 63:
1967 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_09_RK0_FSP0;
1968 TransferReg.u4Fld = MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR63;
1969 break;
1970 }
1971 }
1972 else if (u1MRIdx == 21 || u1MRIdx == 22)
1973 {
1974 if (u1MRIdx == 21)
1975 {
1976 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP1;
1977 TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR21;
1978 }
1979 else
1980 {
1981 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1;
1982 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22;
1983 }
1984 }
1985 else
1986 {
1987 if (u1MRIdx <= 20)
1988 {
1989 if (u1MRIdx <= 10)
1990 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP1;
1991 else if (u1MRIdx <= 15)
1992 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP1;
1993 else
1994 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1;
1995
1996 TransferReg.u4Addr += ((u1Fsp - FSP_1) * 0x30);
1997
1998 if (u1MRIdx == 1 || u1MRIdx == 11 || u1MRIdx == 17)
1999 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR1;
2000 else if (u1MRIdx == 2 || u1MRIdx == 12 || u1MRIdx == 18)
2001 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR2;
2002 else if (u1MRIdx == 3 || u1MRIdx == 14 || u1MRIdx == 19)
2003 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR3;
2004 else
2005 TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR10;
2006 }
2007 else if (u1Fsp == FSP_2 && u1MRIdx == 24)
2008 {
2009 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP2;
2010 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR24;
2011 }
2012 else if (u1Fsp == FSP_1 && u1MRIdx == 41)
2013 {
2014 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1;
2015 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR41;
2016 }
2017 else
2018 {
2019 TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1 + ((u1Fsp - FSP_1) * 0x30);
2020 if ((u1Fsp == FSP_1 && u1MRIdx == 24) || (u1Fsp == FSP_2 && u1MRIdx == 30))
2021 {
2022 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR24;
2023 }
2024 else
2025 {
2026 TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR30;
2027 }
2028 }
2029 }
2030
2031 vSetRank(p, u1Rank);
2032
2033 if (u1MRBackup_ERR_Flag==0)
2034 {
2035 u1Value=u4IO32ReadFldAlign(DRAMC_REG_ADDR(TransferReg.u4Addr), TransferReg.u4Fld);
2036 mcSHOW_MRW_MSG((" [MRW Backup] Rank%d FSP%d MR%d=0x%x\n",u1Rank, gFSPWR_Flag[u1Rank], u1MRIdx, u1Value));
2037 }
2038 vSetRank(p, u1backupRK);
2039
2040 return u1Value;
2041
2042 }
2043 #endif
2044
DramcMRWriteFldMsk(DRAMC_CTX_T * p,U8 mr_idx,U8 listVal8,U8 msk8,U8 UpdateMode)2045 void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listVal8, U8 msk8, U8 UpdateMode)
2046 {
2047 U8 *pMRGlobalValue = DramcFetchGlobalMR(p, mr_idx);
2048
2049 // ASSERT (pMRGlobalValue != NULL)
2050
2051 *pMRGlobalValue = ((*pMRGlobalValue & ~msk8) | listVal8);
2052
2053 if (UpdateMode == TO_MR)
2054 DramcModeRegWriteByRank(p, p->rank, mr_idx, *pMRGlobalValue);
2055 }
2056
DramcMRWriteFldAlign(DRAMC_CTX_T * p,U8 mr_idx,U8 value,U32 mr_fld,U8 UpdateMode)2057 void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode)
2058 {
2059 U8 *pMRGlobalValue = DramcFetchGlobalMR(p, mr_idx);
2060
2061 // ASSERT (pMRGlobalValue != NULL)
2062
2063 *pMRGlobalValue &= ~(Fld2Msk32(mr_fld));
2064 *pMRGlobalValue |= (value << Fld_shft(mr_fld));
2065
2066 if (UpdateMode == TO_MR)
2067 DramcModeRegWriteByRank(p, p->rank, mr_idx, *pMRGlobalValue);
2068 }
2069
DramcModeRegRead(DRAMC_CTX_T * p,U8 u1MRIdx,U16 * u2pValue)2070 void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u2pValue)
2071 {
2072 U32 u4MRValue;
2073 #ifdef DUMP_INIT_RG_LOG_TO_DE
2074 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=0;
2075 #endif
2076 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), p->rank, SWCMD_CTRL0_MRRRK);
2077 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA);
2078
2079
2080 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN);
2081
2082
2083 while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) == 0)
2084 {
2085 mcDELAY_US(1);
2086 }
2087
2088
2089 U32 u4MRRReg;
2090 if (u1IsLP4Family(p->dram_type))
2091 u4MRRReg = MRR_STATUS_MRR_SW_REG;
2092 else
2093 u4MRRReg = MRR_STATUS_MRR_REG;
2094
2095
2096 u4MRValue = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), u4MRRReg);
2097 *u2pValue = (U16)u4MRValue;
2098
2099
2100 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN);
2101
2102 #ifdef DUMP_INIT_RG_LOG_TO_DE
2103 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=1;
2104 #endif
2105
2106 mcSHOW_DBG_MSG4(("Read MR%d =0x%x\n", u1MRIdx, u4MRValue));
2107 }
2108
2109
DramcModeRegReadByRank(DRAMC_CTX_T * p,U8 u1Rank,U8 u1MRIdx,U16 * u2pValue)2110 void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue)
2111 {
2112 U16 u2Value = 0;
2113 U8 u1RankBak;
2114
2115
2116 u1RankBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK);
2117 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
2118
2119
2120 DramcModeRegRead(p, u1MRIdx, &u2Value);
2121 *u2pValue = u2Value;
2122
2123
2124 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1RankBak, SWCMD_CTRL0_MRSRK);
2125
2126 }
2127
DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T * p,U8 * u1Rank,U8 * u1MRIdx,U8 * u1Value,U8 u1Len)2128 void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len)
2129 {
2130 U32 u4Response, u4TimeCnt, ii;
2131 U8 u1MRRK[6] = {0}, u1MRMA[6] = {0}, u1MROP[6] = {0};
2132
2133 if (u1Len > 6 || u1Len == 0)
2134 return;
2135
2136 for (ii = 0;ii < u1Len;ii++)
2137 {
2138 u1MRRK[ii] = u1Rank[ii];
2139 u1MRMA[ii] = u1MRIdx[ii];
2140 u1MROP[ii] = u1Value[ii];
2141 }
2142
2143 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0),
2144 P_Fld(3, RTMRW_CTRL0_RTMRW_LAT) |
2145 P_Fld(0x20, RTMRW_CTRL0_RTMRW_AGE) |
2146 P_Fld(u1Len - 1, RTMRW_CTRL0_RTMRW_LEN) |
2147 P_Fld(u1MRRK[0], RTMRW_CTRL0_RTMRW0_RK) |
2148 P_Fld(u1MRRK[1], RTMRW_CTRL0_RTMRW1_RK) |
2149 P_Fld(u1MRRK[2], RTMRW_CTRL0_RTMRW2_RK) |
2150 P_Fld(u1MRRK[3], RTMRW_CTRL0_RTMRW3_RK) |
2151 P_Fld(u1MRRK[4], RTMRW_CTRL0_RTMRW4_RK) |
2152 P_Fld(u1MRRK[5], RTMRW_CTRL0_RTMRW5_RK));
2153 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1),
2154 P_Fld(u1MRMA[0], RTMRW_CTRL1_RTMRW0_MA) |
2155 P_Fld(u1MRMA[1], RTMRW_CTRL1_RTMRW1_MA) |
2156 P_Fld(u1MRMA[2], RTMRW_CTRL1_RTMRW2_MA) |
2157 P_Fld(u1MRMA[3], RTMRW_CTRL1_RTMRW3_MA));
2158 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2),
2159 P_Fld(u1MROP[0], RTMRW_CTRL2_RTMRW0_OP) |
2160 P_Fld(u1MROP[1], RTMRW_CTRL2_RTMRW1_OP) |
2161 P_Fld(u1MROP[2], RTMRW_CTRL2_RTMRW2_OP) |
2162 P_Fld(u1MROP[3], RTMRW_CTRL2_RTMRW3_OP));
2163 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3),
2164 P_Fld(u1MRMA[4], RTMRW_CTRL3_RTMRW4_MA) |
2165 P_Fld(u1MRMA[5], RTMRW_CTRL3_RTMRW5_MA) |
2166 P_Fld(u1MROP[4], RTMRW_CTRL3_RTMRW4_OP) |
2167 P_Fld(u1MROP[5], RTMRW_CTRL3_RTMRW5_OP));
2168 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
2169 1, MPC_CTRL_RTMRW_HPRI_EN);
2170 mcDELAY_US(5);
2171 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
2172 1, SWCMD_EN_RTMRWEN);
2173
2174 u4TimeCnt = TIME_OUT_CNT;
2175
2176 do {
2177 u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP),
2178 SPCMDRESP_RTMRW_RESPONSE);
2179 u4TimeCnt--;
2180 mcDELAY_US(5);
2181 } while ((u4Response == 0) && (u4TimeCnt > 0));
2182
2183 if (u4TimeCnt == 0)
2184 {
2185 mcSHOW_ERR_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0]));
2186 }
2187
2188 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
2189 0, SWCMD_EN_RTMRWEN);
2190 }
2191
DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T * p,U8 u1Rank,U8 u1MRIdx,U8 u1Value)2192 static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
2193 {
2194 U32 counter = 0;
2195 U32 u4RabnkBackup;
2196 U32 u4register_024;
2197
2198
2199 u4RabnkBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK);
2200
2201
2202 u4register_024 = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
2203
2204
2205 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
2206
2207
2208 CKEFixOnOff(p, u1Rank, CKE_FIXON, TO_ONE_CHANNEL);
2209
2210 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA);
2211 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Value, SWCMD_CTRL0_MRSOP);
2212
2213
2214 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRWEN);
2215
2216
2217 while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) == 0)
2218 {
2219 counter++;
2220 mcSHOW_DBG_MSG2(("wait MRW command Rank%d MR%d =0x%x fired (%d)\n", u1Rank, u1MRIdx, u1Value, counter));
2221 mcDELAY_US(1);
2222 }
2223
2224
2225 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRWEN);
2226
2227
2228 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4register_024);
2229
2230
2231 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4RabnkBackup, SWCMD_CTRL0_MRSRK);
2232 }
2233
DramcModeRegWriteByRank(DRAMC_CTX_T * p,U8 u1Rank,U8 u1MRIdx,U8 u1Value)2234 void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
2235 {
2236 mcSHOW_DBG_MSG2(("MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value));
2237
2238 #if (fcFOR_CHIP_ID == fcA60868)
2239
2240
2241 if (u1EnterRuntime)
2242 {
2243 DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value);
2244 }
2245 else
2246 #endif
2247 {
2248 {
2249 DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value);
2250 }
2251 }
2252
2253 #if MRW_CHECK_ONLY
2254 u1PrintModeRegWrite = 1;
2255 U8 u1Backup_Rank;
2256 U8 u1RankIdx, u1RankNum, u1RankStart;
2257 U8 u1FSPMRIdx;
2258
2259 u1Backup_Rank=p->rank;
2260
2261 if (u1Rank==3)
2262 {
2263 u1RankNum = 2;
2264 u1RankStart = 0;
2265 }
2266 else
2267 {
2268 u1RankNum = 1;
2269 u1RankStart = u1Rank;
2270 }
2271
2272 u1FSPMRIdx=13;
2273
2274 for (u1RankIdx=u1RankStart;u1RankIdx<u1RankStart+u1RankNum;u1RankIdx++)
2275 {
2276 vSetRank(p, u1RankIdx);
2277 if (u1MRIdx==u1FSPMRIdx)
2278 {
2279 u2MRRecord[p->channel][u1RankIdx][FSP_0][u1FSPMRIdx] =u1Value;
2280 u2MRRecord[p->channel][u1RankIdx][FSP_1][u1FSPMRIdx] =u1Value;
2281 }
2282 else
2283 u2MRRecord[p->channel][u1RankIdx][gFSPWR_Flag[u1RankIdx]][u1MRIdx] = u1Value;
2284
2285 if(u1PrintModeRegWrite)
2286 {
2287 #if VENDER_JV_LOG
2288 mcSHOW_JV_LOG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
2289 #endif
2290 #if MRW_CHECK_ONLY
2291 mcSHOW_MRW_MSG(("MRW CH%d Rank%d FSP%d MR%d =0x%x\n", p->channel, u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, u1Value));
2292 #endif
2293 mcSHOW_DBG_MSG2(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
2294 //mcDUMP_REG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
2295 }
2296 #if MRW_BACKUP
2297 U8 MR_backup;
2298
2299 MR_backup=DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
2300 if (MR_backup!=0xff)
2301 mcSHOW_MRW_MSG((" [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL")));
2302 #endif
2303
2304 {
2305 if (u1MRIdx==u1FSPMRIdx)
2306 gFSPWR_Flag[u1RankIdx] = (u1Value>> 6) & 0x1;
2307 }
2308 }
2309 vSetRank(p, u1Backup_Rank);
2310 #endif
2311 }
2312
2313 #if __ETT__
2314 static U8 u1gpRegBackup;
2315 #endif
2316 U32 u4gpRegBackupVlaue[100];
DramcBackupRegisters(DRAMC_CTX_T * p,U32 * backup_addr,U32 backup_num)2317 void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num)
2318 {
2319 U32 u4RegIdx;
2320
2321 #if __ETT__
2322 if (backup_num > 100 || u1gpRegBackup)
2323 {
2324 mcSHOW_ERR_MSG(("[DramcBackupRegisters] backup number over 64!!!\n"));
2325 while (1);
2326 }
2327
2328 u1gpRegBackup++;
2329 #endif
2330
2331 for (u4RegIdx = 0; u4RegIdx < backup_num; u4RegIdx++)
2332 {
2333 u4gpRegBackupVlaue[u4RegIdx] = u4IO32Read4B(backup_addr[u4RegIdx]);
2334 //mcSHOW_DBG_MSG(("Backup Reg(0x%X) = 0x%X\n", backup_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]));
2335 }
2336 }
2337
DramcRestoreRegisters(DRAMC_CTX_T * p,U32 * restore_addr,U32 restore_num)2338 void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num)
2339 {
2340 U32 u4RegIdx;
2341
2342 #if __ETT__
2343 if (u1gpRegBackup == 0)
2344 {
2345 mcSHOW_ERR_MSG(("[DramcRestoreRegisters] Need to call backup first\n"));
2346 }
2347
2348 u1gpRegBackup--;
2349 #endif
2350
2351 for (u4RegIdx = 0; u4RegIdx < restore_num; u4RegIdx++)
2352 {
2353 vIO32Write4B(restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]);
2354 //mcSHOW_DBG_MSG(("Restore Reg(0x%X) = 0x%X\n", restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]));
2355 }
2356 }
2357
2358
u1GetMR4RefreshRate(DRAMC_CTX_T * p,DRAM_CHANNEL_T channel)2359 U8 u1GetMR4RefreshRate(DRAMC_CTX_T *p, DRAM_CHANNEL_T channel)
2360 {
2361 U8 u1RefreshRate; //u1Dummy
2362
2363 //vSetPHY2ChannelMapping(p, channel);
2364
2365 //DramcModeRegRead(p, 4, &u1Dummy);
2366 //mcSHOW_DBG_MSG(("[u2GetRefreshRate] MR4 0x%x, u1RefreshRate= 0x%x\n", u1Dummy, u1RefreshRate));
2367 u1RefreshRate = (U8)u4IO32ReadFldAlign((DRAMC_REG_MISC_STATUSA) + (channel << POS_BANK_NUM), MISC_STATUSA_REFRESH_RATE);
2368 //mcSHOW_DBG_MSG(("[u2GetRefreshRate] channel = %d, u1RefreshRate= 0x%x\n", channel, u1RefreshRate));
2369
2370 return u1RefreshRate;
2371 }
2372
2373 #if 0
2374 //#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
2375 void DramcConfInfraReset(DRAMC_CTX_T *p)
2376 {
2377 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
2378 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL)
2379 | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN));
2380
2381 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL)
2382 | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM));
2383 mcDELAY_XNS(100);
2384 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM);
2385
2386 #if (fcFOR_CHIP_ID == fcLafite)
2387
2388 vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX)
2389 | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM));
2390 vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM)
2391 | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL));
2392 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);
2393 mcDELAY_US(1);
2394 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);
2395
2396
2397 //mcSHOW_TIME_MSG(("Before infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148)));
2398 *(volatile unsigned *)(0x10001140) = (0x1 << 15);
2399 //mcSHOW_TIME_MSG(("After infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148)));
2400 __asm__ __volatile__ ("dsb" : : : "memory");
2401 mcDELAY_US(200);
2402 //mcSHOW_TIME_MSG(("Before infra clear, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148)));
2403 *(volatile unsigned *)(0x10001144) = (0x1 << 15);
2404 //mcSHOW_TIME_MSG(("After infra clear, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148)));
2405
2406 #if 0
2407 mcDELAY_US(200);
2408 *(volatile unsigned *)(0x10007018) = 0x88000040;
2409 mcDELAY_US(200);
2410 *(volatile unsigned *)(0x10007018) = 0x88000000;
2411 mcDELAY_US(200);
2412 #endif
2413
2414
2415 vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_ARDQ_RESETB_B0);
2416 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
2417 vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_ARDQ_RESETB_B1);
2418 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
2419 vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x0, CA_CMD3_RG_ARCMD_RESETB);
2420 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
2421 vIO32WriteFldAlign(DDRPHY_PLL4, 0x0, PLL4_RG_RPHYPLL_RESETB);
2422 mcDELAY_US(200);
2423 vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0);
2424 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
2425 vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1);
2426 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
2427 vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_ARCMD_RESETB);
2428 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
2429 vIO32WriteFldAlign(DDRPHY_PLL4, 0x1, PLL4_RG_RPHYPLL_RESETB);
2430
2431
2432 vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(0, POWERON_CONFIG_EN_BCLK_CG_EN));
2433
2434
2435 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN);
2436 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON);
2437 #endif
2438 #endif
2439 }
2440 #endif
2441
2442 #if 0
2443 #define PATTERN1 0x5A5A5A5A
2444 #define PATTERN2 0xA5A5A5A5
2445 int dramc_complex_mem_test (unsigned int start, unsigned int len)
2446 {
2447 unsigned char *MEM8_BASE = (unsigned char *) start;
2448 unsigned short *MEM16_BASE = (unsigned short *) start;
2449 unsigned int *MEM32_BASE = (unsigned int *) start;
2450 unsigned int *MEM_BASE = (unsigned int *) start;
2451 unsigned char pattern8;
2452 unsigned short pattern16;
2453 unsigned int i, j, size, pattern32;
2454 unsigned int value;
2455
2456 size = len >> 2;
2457
2458
2459 for (i = 0; i < size; i++)
2460 {
2461 MEM32_BASE[i] = 0;
2462 }
2463
2464 for (i = 0; i < size; i++)
2465 {
2466 if (MEM32_BASE[i] != 0)
2467 {
2468 return -1;
2469 }
2470 else
2471 {
2472 MEM32_BASE[i] = 0xffffffff;
2473 }
2474 }
2475
2476
2477 for (i = 0; i < size; i++)
2478 {
2479 if (MEM32_BASE[i] != 0xffffffff)
2480 {
2481 return -2;
2482 }
2483 else
2484 MEM32_BASE[i] = 0x00;
2485 }
2486
2487
2488 pattern8 = 0x00;
2489 for (i = 0; i < len; i++)
2490 MEM8_BASE[i] = pattern8++;
2491 pattern8 = 0x00;
2492 for (i = 0; i < len; i++)
2493 {
2494 if (MEM8_BASE[i] != pattern8++)
2495 {
2496 return -3;
2497 }
2498 }
2499
2500
2501 pattern8 = 0x00;
2502 for (i = j = 0; i < len; i += 2, j++)
2503 {
2504 if (MEM8_BASE[i] == pattern8)
2505 MEM16_BASE[j] = pattern8;
2506 if (MEM16_BASE[j] != pattern8)
2507 {
2508 return -4;
2509 }
2510 pattern8 += 2;
2511 }
2512
2513
2514 pattern16 = 0x00;
2515 for (i = 0; i < (len >> 1); i++)
2516 MEM16_BASE[i] = pattern16++;
2517 pattern16 = 0x00;
2518 for (i = 0; i < (len >> 1); i++)
2519 {
2520 if (MEM16_BASE[i] != pattern16++)
2521 {
2522 return -5;
2523 }
2524 }
2525
2526
2527 pattern32 = 0x00;
2528 for (i = 0; i < (len >> 2); i++)
2529 MEM32_BASE[i] = pattern32++;
2530 pattern32 = 0x00;
2531 for (i = 0; i < (len >> 2); i++)
2532 {
2533 if (MEM32_BASE[i] != pattern32++)
2534 {
2535 return -6;
2536 }
2537 }
2538
2539
2540 for (i = 0; i < size; i++)
2541 MEM32_BASE[i] = 0x44332211;
2542
2543
2544 for (i = 0; i < size; i++)
2545 {
2546 if (MEM32_BASE[i] != 0x44332211)
2547 {
2548 return -7;
2549 }
2550 else
2551 {
2552 MEM32_BASE[i] = 0xa5a5a5a5;
2553 }
2554 }
2555
2556
2557 for (i = 0; i < size; i++)
2558 {
2559 if (MEM32_BASE[i] != 0xa5a5a5a5)
2560 {
2561 return -8;
2562 }
2563 else
2564 {
2565 MEM8_BASE[i * 4] = 0x00;
2566 }
2567 }
2568
2569
2570 for (i = 0; i < size; i++)
2571 {
2572 if (MEM32_BASE[i] != 0xa5a5a500)
2573 {
2574 return -9;
2575 }
2576 else
2577 {
2578 MEM8_BASE[i * 4 + 2] = 0x00;
2579 }
2580 }
2581
2582
2583 for (i = 0; i < size; i++)
2584 {
2585 if (MEM32_BASE[i] != 0xa500a500)
2586 {
2587 return -10;
2588 }
2589 else
2590 {
2591 MEM8_BASE[i * 4 + 1] = 0x00;
2592 }
2593 }
2594
2595
2596 for (i = 0; i < size; i++)
2597 {
2598 if (MEM32_BASE[i] != 0xa5000000)
2599 {
2600 return -11;
2601 }
2602 else
2603 {
2604 MEM8_BASE[i * 4 + 3] = 0x00;
2605 }
2606 }
2607
2608
2609 for (i = 0; i < size; i++)
2610 {
2611 if (MEM32_BASE[i] != 0x00000000)
2612 {
2613 return -12;
2614 }
2615 else
2616 {
2617 MEM16_BASE[i * 2 + 1] = 0xffff;
2618 }
2619 }
2620
2621
2622 for (i = 0; i < size; i++)
2623 {
2624 if (MEM32_BASE[i] != 0xffff0000)
2625 {
2626 return -13;
2627 }
2628 else
2629 {
2630 MEM16_BASE[i * 2] = 0xffff;
2631 }
2632 }
2633
2634
2635 for (i = 0; i < size; i++)
2636 {
2637 if (MEM32_BASE[i] != 0xffffffff)
2638 {
2639 return -14;
2640 }
2641 }
2642
2643
2644
2645 for (i = 0; i < size; i++)
2646 {
2647 MEM_BASE[i] = PATTERN1;
2648 }
2649
2650
2651 for (i = 0; i < size; i++)
2652 {
2653 value = MEM_BASE[i];
2654
2655 if (value != PATTERN1)
2656 {
2657 return -15;
2658 }
2659 MEM_BASE[i] = PATTERN2;
2660 }
2661
2662
2663 for (i = 0; i < size; i++)
2664 {
2665 value = MEM_BASE[i];
2666 if (value != PATTERN2)
2667 {
2668 return -16;
2669 }
2670 MEM_BASE[i] = PATTERN1;
2671 }
2672
2673
2674
2675 for (i = 0; i < size; i++)
2676 {
2677 value = MEM_BASE[i];
2678 if (value != PATTERN1)
2679 {
2680 return -17;
2681 }
2682 MEM_BASE[i] = PATTERN2;
2683 }
2684
2685
2686 for (i = 0; i < size; i++)
2687 {
2688 value = MEM_BASE[i];
2689 if (value != PATTERN2)
2690 {
2691 return -18;
2692 }
2693 MEM_BASE[i] = PATTERN1;
2694 }
2695
2696
2697 for (i = 0; i < size; i++)
2698 {
2699 value = MEM_BASE[i];
2700 if (value != PATTERN1)
2701 {
2702 return -19;
2703 }
2704 }
2705
2706 #if 1
2707
2708 i = (unsigned int) MEM_BASE;
2709
2710 while (i < (unsigned int) MEM_BASE + (size << 2))
2711 {
2712 *((unsigned char *) i) = 0x78;
2713 i += 1;
2714 *((unsigned char *) i) = 0x56;
2715 i += 1;
2716 *((unsigned short *) i) = 0x1234;
2717 i += 2;
2718 *((unsigned int *) i) = 0x12345678;
2719 i += 4;
2720 *((unsigned short *) i) = 0x5678;
2721 i += 2;
2722 *((unsigned char *) i) = 0x34;
2723 i += 1;
2724 *((unsigned char *) i) = 0x12;
2725 i += 1;
2726 *((unsigned int *) i) = 0x12345678;
2727 i += 4;
2728 *((unsigned char *) i) = 0x78;
2729 i += 1;
2730 *((unsigned char *) i) = 0x56;
2731 i += 1;
2732 *((unsigned short *) i) = 0x1234;
2733 i += 2;
2734 *((unsigned int *) i) = 0x12345678;
2735 i += 4;
2736 *((unsigned short *) i) = 0x5678;
2737 i += 2;
2738 *((unsigned char *) i) = 0x34;
2739 i += 1;
2740 *((unsigned char *) i) = 0x12;
2741 i += 1;
2742 *((unsigned int *) i) = 0x12345678;
2743 i += 4;
2744 }
2745 for (i = 0; i < size; i++)
2746 {
2747 value = MEM_BASE[i];
2748 if (value != 0x12345678)
2749 {
2750 return -20;
2751 }
2752 }
2753 #endif
2754
2755
2756 pattern8 = 0x00;
2757 MEM8_BASE[0] = pattern8;
2758 for (i = 0; i < size * 4; i++)
2759 {
2760 unsigned char waddr8, raddr8;
2761 waddr8 = i + 1;
2762 raddr8 = i;
2763 if (i < size * 4 - 1)
2764 MEM8_BASE[waddr8] = pattern8 + 1;
2765 if (MEM8_BASE[raddr8] != pattern8)
2766 {
2767 return -21;
2768 }
2769 pattern8++;
2770 }
2771
2772
2773 pattern16 = 0x00;
2774 MEM16_BASE[0] = pattern16;
2775 for (i = 0; i < size * 2; i++)
2776 {
2777 if (i < size * 2 - 1)
2778 MEM16_BASE[i + 1] = pattern16 + 1;
2779 if (MEM16_BASE[i] != pattern16)
2780 {
2781 return -22;
2782 }
2783 pattern16++;
2784 }
2785
2786
2787 pattern32 = 0x00;
2788 MEM32_BASE[0] = pattern32;
2789 for (i = 0; i < size; i++)
2790 {
2791 if (i < size - 1)
2792 MEM32_BASE[i + 1] = pattern32 + 1;
2793 if (MEM32_BASE[i] != pattern32)
2794 {
2795 return -23;
2796 }
2797 pattern32++;
2798 }
2799 return 0;
2800 }
2801 #endif
2802
2803 #if defined(DDR_INIT_TIME_PROFILING) || ENABLE_APB_MASK_WRITE
2804 static PROFILING_TIME_T prof_tick0;
2805
TimeProfileGetTick(PROFILING_TIME_T * ptime)2806 void TimeProfileGetTick(PROFILING_TIME_T *ptime)
2807 {
2808 #if __ETT__
2809 ptime->u4TickLow = GPT_GetTickCount(&ptime->u4TickHigh);
2810 #else
2811 ptime->u4TickHigh = 0;
2812 ptime->u4TickLow = get_timer(0);
2813 #endif
2814 }
2815
TimeProfileDiffUS(PROFILING_TIME_T * base)2816 U32 TimeProfileDiffUS(PROFILING_TIME_T *base)
2817 {
2818 U32 u4Diff;
2819
2820 #if __ETT__
2821 const U32 u4TsMax = 0xFFFFFFFFUL;
2822 const U32 u4NsPerTick = 76;
2823 const U32 u4OV = u4TsMax / u4NsPerTick;
2824 U32 u4Acc;
2825 PROFILING_TIME_T end;
2826
2827 u4Acc = 0;
2828 TimeProfileGetTick(&end);
2829
2830
2831 u4Diff = end.u4TickLow - base->u4TickLow;
2832 if (end.u4TickLow > base->u4TickLow)
2833 {
2834 u4Diff = end.u4TickLow - base->u4TickLow;
2835 }
2836 else
2837 {
2838 u4Diff = u4TsMax - base->u4TickLow + end.u4TickLow;
2839 mcSHOW_TIME_MSG(("%s(): overflow detected\n", __func__));
2840 }
2841
2842 while (u4Diff >= u4OV)
2843 {
2844 u4Acc++;
2845 u4Diff -= u4OV;
2846 }
2847
2848 u4Diff = u4Diff * u4NsPerTick / 1000;
2849 u4Diff += u4Acc * (u4TsMax / 1000);
2850 #else
2851 u4Diff = get_timer(base->u4TickLow) * 1000;
2852 #endif
2853
2854 return u4Diff;
2855 }
2856
TimeProfileBegin(void)2857 void TimeProfileBegin(void)
2858 {
2859 TimeProfileGetTick(&prof_tick0);
2860 }
2861
TimeProfileEnd(void)2862 U32 TimeProfileEnd(void)
2863 {
2864 return TimeProfileDiffUS(&prof_tick0);
2865 }
2866 #endif
2867
2868 #if QT_GUI_Tool
TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T * p,U32 test2_1,U32 test2_2,U8 u1TestPat,U8 u1LoopCnt)2869 void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt)
2870 {
2871 u1TestPat = u1TestPat & 0x7f;
2872
2873 DramcSetRankEngine2(p, p->rank);
2874
2875 uiReg0D0h=u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD));
2876 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) | P_Fld(0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0, DUMMY_RD_DMY_RD_DBG) | P_Fld(0, DUMMY_RD_DMY_WR_DBG)); //must close dummy read when do test agent
2877
2878 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT);//Eddie
2879
2880 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
2881
2882
2883 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), P_Fld(test2_1>>24,TEST2_A0_TEST2_PAT0)|P_Fld(test2_2>>24,TEST2_A0_TEST2_PAT1));
2884
2885 #if (FOR_DV_SIMULATION_USED==1 || SW_CHANGE_FOR_SIMULATION==1)
2886
2887 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A1), (test2_1+0x100) & 0x00ffffff, TEST2_A1_TEST2_BASE);
2888 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x10000, RK_TEST2_A1_TEST2_BASE);
2889 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x0, RK_TEST2_A1_TEST2_BASE);
2890 #else
2891 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0, RK_TEST2_A1_TEST2_BASE);
2892 #endif
2893 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x2, TEST2_A2_TEST2_OFF);
2894
2895 return;
2896 }
2897 #endif
2898