1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "dramc_int_global.h"
8 #include "x_hal_io.h"
9 #include "dramc_top.h"
10
11
12 //-----------------------------------------------------------------------------
13 // Global variables
14 //-----------------------------------------------------------------------------
15
16 //U8 gu1MR23Done = FALSE; /* Not used starting from Vinson (all freqs use MR23=0x3F) */
17 U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
18 /* DQSOSCTHRD_INC & _DEC are 12 bits (Starting from Vinson) */
19 U16 gu2DQSOSCTHRD_INC[CHANNEL_NUM][RANK_MAX];
20 U16 gu2DQSOSCTHRD_DEC[CHANNEL_NUM][RANK_MAX];
21 U16 gu2MR18[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR18 (DQS ocillator count - MSB) */
22 U16 gu2MR19[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR19 (DQS ocillator count - LSB) */
23 U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX]; /* Stores tDQSOSC results */
24 U16 gu2DQSOscCnt[CHANNEL_NUM][RANK_MAX][2];
25
26
DramcDQSOSCInit(void)27 void DramcDQSOSCInit(void)
28 {
29 memset(gu1MR23, 0x3F, sizeof(gu1MR23)); /* MR23 should be 0x3F for all freqs (Starting from Vinson) */
30 memset(gu2DQSOSCTHRD_INC, 0x6, sizeof(gu2DQSOSCTHRD_INC));
31 memset(gu2DQSOSCTHRD_DEC, 0x4, sizeof(gu2DQSOSCTHRD_DEC));
32 }
33
DramcStartDQSOSC_SWCMD(DRAMC_CTX_T * p)34 static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
35 {
36 U32 u4Response;
37 U32 u4TimeCnt = TIME_OUT_CNT;
38 U32 u4RegBackupAddress[] = {DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)};
39
40 // Backup rank, CKE fix on/off, HW MIOCK control settings
41 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
42
43 msg3("[ZQCalibration]\n");
44 //mcFPRINTF(fp_A60501, "[ZQCalibration]\n");
45
46 // Disable HW MIOCK control to make CLK always on
47 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
48 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON);
49 mcDELAY_US(1);
50
51 //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank.
52 CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL);
53
54 //ZQCAL Start
55 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_WCK2DQI_START_SWTRIG);
56
57 do
58 {
59 u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE);
60 u4TimeCnt --;
61 mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling
62
63 msg3("%d- ", u4TimeCnt);
64 //mcFPRINTF(fp_A60501, "%d- ", u4TimeCnt);
65 }while((u4Response==0) &&(u4TimeCnt>0));
66
67 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_WCK2DQI_START_SWTRIG);
68
69 if(u4TimeCnt==0)//time out
70 {
71 msg("ZQCAL Start fail (time out)\n");
72 //mcFPRINTF(fp_A60501, "ZQCAL Start fail (time out)\n");
73 return DRAM_FAIL;
74 }
75
76 // Restore rank, CKE fix on, HW MIOCK control settings
77 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
78
79 msg3("\n[DramcZQCalibration] Done\n\n");
80 //mcFPRINTF(fp_A60501, "\n[DramcZQCalibration] Done\n\n");
81
82 return DRAM_OK;
83 }
84
DramcStartDQSOSC(DRAMC_CTX_T * p)85 static DRAM_STATUS_T DramcStartDQSOSC(DRAMC_CTX_T *p)
86 {
87 // return DramcStartDQSOSC_SCSM(p);
88 // return DramcStartDQSOSC_RTSWCMD(p);
89 return DramcStartDQSOSC_SWCMD(p);
90 }
91
DramcDQSOSCAuto(DRAMC_CTX_T * p)92 DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
93 {
94 U8 u1MR23 = gu1MR23[p->channel][p->rank];
95 U16 u2MR18, u2MR19;
96 U16 u2DQSCnt;
97 U16 u2DQSOsc[2];
98 U32 u4RegBak[2];
99
100 #if MRW_CHECK_ONLY
101 mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
102 #endif
103
104 u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
105 u4RegBak[1] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
106
107 //LPDDR4-3200, PI resolution = tCK/64 =9.76ps
108 //Only if MR23>=16, then error < PI resolution.
109 //Set MR23 == 0x3f, stop after 63*16 clock
110 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1GetRank(p), MRS_MRSRK);
111 DramcModeRegWriteByRank(p, p->rank, 23, u1MR23);
112
113 //SW mode
114 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
115
116 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
117 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON);
118
119 CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL);
120
121 DramcStartDQSOSC(p);
122 mcDELAY_US(1);
123
124 DramcModeRegReadByRank(p, p->rank, 18, &u2MR18);
125 DramcModeRegReadByRank(p, p->rank, 19, &u2MR19);
126
127 #if (SW_CHANGE_FOR_SIMULATION == 0)
128 //B0
129 u2DQSCnt = (u2MR18 & 0x00FF) | ((u2MR19 & 0x00FF) << 8);
130 if (u2DQSCnt != 0)
131 u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * p->frequency); //tDQSOSC = 16*MR23*tCK/2*count
132 else
133 u2DQSOsc[0] = 0;
134
135 //B1
136 u2DQSCnt = (u2MR18 >> 8) | ((u2MR19 & 0xFF00));
137 if (u2DQSCnt != 0)
138 u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * p->frequency); //tDQSOSC = 16*MR23*tCK/2*count
139 else
140 u2DQSOsc[1] = 0;
141 msg("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1]);
142 #endif
143
144 gu2MR18[p->channel][p->rank] = u2MR18;
145 gu2MR19[p->channel][p->rank] = u2MR19;
146 gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[0];
147
148 if (u2DQSOsc[1] != 0 && u2DQSOsc[1] < u2DQSOsc[0])
149 gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[1];
150
151 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4RegBak[0]);
152 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4RegBak[1]);
153
154 return DRAM_OK;
155 }
156
157
158 #if ENABLE_TX_TRACKING
159 /* Using gu2DQSOSC results calculated from DramcDQSOSCAuto
160 * -> calculate DQSOSCTHRD_INC, DQSOSCTHRD_DEC
161 * _INC, _DEC formulas are extracted from "Verification plan of Vinson LPDDR4 HW TX Tracking" doc
162 */
DramcDQSOSCMR23(DRAMC_CTX_T * p)163 DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p)
164 {
165 #if (SW_CHANGE_FOR_SIMULATION == 0)
166 /* Preloader doesn't support floating point numbers -> Manually expand/simpify _INC, _DEC formula */
167 U8 u1MR23 = gu1MR23[p->channel][p->rank];
168 U16 u2DQSOSC = gu2DQSOSC[p->channel][p->rank];
169 U32 u4tCK = 1000000 / p->frequency;
170
171 if (u2DQSOSC != 0)
172 {
173 gu2DQSOSCTHRD_INC[p->channel][p->rank] = (3 * u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 20);
174 gu2DQSOSCTHRD_DEC[p->channel][p->rank] = (u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 10);
175 }
176
177 msg("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", p->channel, p->rank,
178 gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank], gu2DQSOSC[p->channel][p->rank],
179 u1MR23, gu2DQSOSCTHRD_INC[p->channel][p->rank], gu2DQSOSCTHRD_DEC[p->channel][p->rank]);
180 #endif
181 return DRAM_OK;
182 }
183
184
185 /* Sets DQSOSC_BASE for specified rank/byte */
DramcDQSOSCSetMR18MR19(DRAMC_CTX_T * p)186 DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p)
187 {
188 U16 u2DQSOscCnt[2];
189
190 DramcDQSOSCAuto(p);
191
192 //B0
193 gu2DQSOscCnt[p->channel][p->rank][0] = u2DQSOscCnt[0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
194 //B1
195 gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
196
197 if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && (gu2DQSOscCnt[p->channel][p->rank][1] == 0))
198 {
199 gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = u2DQSOscCnt[0];
200 }
201
202 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), P_Fld(u2DQSOscCnt[0], SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(u2DQSOscCnt[1], SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
203
204 msg("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]);
205 reg_msg("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]);
206 return DRAM_OK;
207 }
208
DramcDQSOSCShuSettings(DRAMC_CTX_T * p)209 DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
210 {
211 U16 u2PRDCNT = 0x3FF, u2PRDCNTtmp = 0x3FF;
212 U8 u1PRDCNT_DIV = 4;
213 U16 u2DQSOSCENCNT = 0xFFF;
214 U8 u1FILT_PITHRD = 0;
215 U8 u1W2R_SEL = 0;
216 U8 u1RankIdx, u1RankIdxBak;
217 U8 u1DQSOSCRCNT = 0, u1IsDiv4 = 0, u1RoundUp= 0;
218 u1RankIdxBak = u1GetRank(p);
219
220 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
221 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x0, DQSOSCR_R_DMDQS2DQ_FILT_OPT);
222 if (p->frequency <= 400)
223 {
224 u1FILT_PITHRD = 0x5;
225 if (vGet_Div_Mode(p) == DIV4_MODE)
226 u1W2R_SEL = 0x2;
227 else
228 u1W2R_SEL = 0x5;
229 }
230 else if (p->frequency <= 600)
231 {
232 u1FILT_PITHRD = 0x6;
233 if (vGet_Div_Mode(p) == DIV4_MODE)
234 u1W2R_SEL = 0x2;
235 else
236 u1W2R_SEL = 0x5;
237 }
238 else if (p->frequency <= 800)
239 {
240 u1FILT_PITHRD = 0x6;
241 if (vGet_Div_Mode(p) == DIV4_MODE)
242 u1W2R_SEL = 0x2;
243 else
244 u1W2R_SEL = 0x5;
245 }
246 else if (p->frequency <= 933)
247 {
248 u1FILT_PITHRD = 0x9;
249 u1W2R_SEL = 0x2;
250 }
251 else if (p->frequency <= 1200)
252 {
253 u1FILT_PITHRD = 0xb;
254 u1W2R_SEL = 0x2;
255 }
256 else if (p->frequency <= 1333)
257 {
258 u1FILT_PITHRD = 0xc;
259 u1W2R_SEL = 0x2;
260 }
261 else if (p->frequency <= 1600)
262 {
263 u1FILT_PITHRD = 0xE;
264 u1W2R_SEL = 0x2;
265 }
266 else if (p->frequency <= 1866)
267 {
268 u1FILT_PITHRD = 0x12;
269 u1W2R_SEL = 0x2;
270 }
271 else //4266
272 {
273 u1FILT_PITHRD = 0x17;
274 u1W2R_SEL = 0x2;
275 }
276
277 if (vGet_Div_Mode(p) == DIV4_MODE)
278 {
279 u1PRDCNT_DIV = 2;
280 u1IsDiv4 = 1;
281 }
282
283 u1DQSOSCRCNT = ((p->frequency << u1IsDiv4))/100;
284 if ((p->frequency%100) != 0) // @Darren, Round up for tOSCO timing (40ns)
285 u1DQSOSCRCNT++;
286 if (gu1MR23[p->channel][RANK_1] > gu1MR23[p->channel][RANK_0])
287 u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_1]*100)/u1PRDCNT_DIV);
288 else
289 u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_0]*100)/u1PRDCNT_DIV);
290
291 u2PRDCNT = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))/100;
292 u1RoundUp = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))%100;
293 if (u1RoundUp != 0)
294 u2PRDCNT++;
295
296 //Don't power down dram during DQS interval timer run time, (MR23[7:0] /4) + (tOSCO/MCK unit/16)
297 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT);
298
299 //set tOSCO constraint to read MR18/MR19, should be > 40ns/MCK
300 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);//@Darren, unit: MCK to meet spec. tOSCO=40ns/MCK
301 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), (u1FILT_PITHRD>>1), SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
302 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(u1W2R_SEL, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL));
303
304 /* Starting from Vinson, DQSOSCTHRD_INC & _DEC is split into RK0 and RK1 */
305 //Rank 0
306
307
308 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
309 {
310 vSetRank(p, u1RankIdx);
311 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_INC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_INC);
312 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_DEC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC);
313 }
314 vSetRank(p, u1RankIdxBak);
315
316 //set interval to do MPC(start DQSOSC) command, and dramc send DQSOSC start to rank0/1/2 at the same time
317 //TX tracking period unit: 3.9us
318 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2DQSOSCENCNT, SHU_DQSOSC_SET0_DQSOSCENCNT);
319
320 return DRAM_OK;
321 }
322
DramcHwDQSOSC(DRAMC_CTX_T * p)323 void DramcHwDQSOSC(DRAMC_CTX_T *p)
324 {
325 DRAM_RANK_T rank_bak = u1GetRank(p);
326 DRAM_CHANNEL_T ch_bak = p->channel;
327
328 //Enable TX tracking new mode
329 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), 1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT);
330
331 //Enable Freq_RATIO update
332 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0), P_Fld(1, TX_TRACKING_SET0_SHU_PRELOAD_TX_HW)
333 | P_Fld(0, TX_TRACKING_SET0_SHU_PRELOAD_TX_START)
334 | P_Fld(0, TX_TRACKING_SET0_SW_UP_TX_NOW_CASE));
335
336 //DQSOSC MPC command violation
337 #if ENABLE_TMRRI_NEW_MODE
338 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 1, MPC_CTRL_MPC_BLOCKALE_OPT);
339 #else
340 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_MPC_BLOCKALE_OPT);
341 #endif
342
343 //DQS2DQ UI/PI setting controlled by HW
344 #if ENABLE_SW_TX_TRACKING
345 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW);
346 #else
347 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW);
348 #if ENABLE_PA_IMPRO_FOR_TX_TRACKING
349 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
350 #endif
351 #endif
352 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW);
353
354 //Set dqsosc oscillator run time by MRW
355 //write RK0 MR23
356 #if 0
357 vSetRank(p, RANK_0);
358 vSetPHY2ChannelMapping(p, CHANNEL_A);
359 DramcModeRegWrite(p, 23, u1MR23);
360 vSetPHY2ChannelMapping(p, CHANNEL_B);
361 DramcModeRegWrite(p, 23, u1MR23);
362 //write RK1 MR23
363 vSetRank(p, RANK_1);
364 vSetPHY2ChannelMapping(p, CHANNEL_A);
365 DramcModeRegWrite(p, 23, u1MR23);
366 vSetPHY2ChannelMapping(p, CHANNEL_B);
367 DramcModeRegWrite(p, 23, u1MR23);
368 #endif
369
370 //Enable HW read MR18/MR19 for each rank
371 #if ENABLE_SW_TX_TRACKING
372 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSCRDIS);
373 #else
374 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSCRDIS);
375 #endif
376
377 vSetRank(p, RANK_0);
378 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
379 if (p->support_rank_num == RANK_DUAL)
380 {
381 vSetRank(p, RANK_1);
382 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
383 }
384
385 //@Jouling, Update MP setting
386 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN); //Set as 1 to fix issue of RANK_SINGLE, dual rank can also be enable
387
388 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSC_CALEN);
389
390 vSetRank(p, rank_bak);
391 vSetPHY2ChannelMapping(p, ch_bak);
392 }
393
Enable_TX_Tracking(DRAMC_CTX_T * p,U32 u4DramcShuOffset)394 void Enable_TX_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset)
395 {
396 //DDR800 do not enable tracking
397 if (p->pDFSTable->shuffleIdx == SRAM_SHU6) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0
398 {
399 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0 + u4DramcShuOffset, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
400 }
401 else
402 {
403 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0 + u4DramcShuOffset, 0, SHU_DQSOSC_SET0_DQSOSCENDIS);
404 }
405 }
406 #endif
407
408 #if RDSEL_TRACKING_EN
Enable_RDSEL_Tracking(DRAMC_CTX_T * p,U32 u4DramcShuOffset)409 void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset)
410 {
411 //Only enable at DDR3733
412 if (p->pDFSTable->shuffleIdx == SRAM_SHU0) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0
413 {
414 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK + u4DramcShuOffset, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
415 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK + u4DramcShuOffset, P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN)
416 | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK));
417 }
418 else
419 {
420 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK + u4DramcShuOffset, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
421 }
422 }
423 #endif
424
425 #ifdef HW_GATING
Enable_Gating_Tracking(DRAMC_CTX_T * p,U32 u4DDRPhyShuOffset)426 void Enable_Gating_Tracking(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset)
427 {
428 if (p->pDFSTable->shuffleIdx == SRAM_SHU6) {
429 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL + u4DDRPhyShuOffset,
430 P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) |
431 P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN));
432 } else {
433 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL + u4DDRPhyShuOffset,
434 P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) |
435 P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN));
436 }
437 }
438 #endif
439
Enable_ClkTxRxLatchEn(DRAMC_CTX_T * p,U32 u4DDRPhyShuOffset)440 void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset)
441 {
442 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13 + u4DDRPhyShuOffset, 1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
443 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13 + u4DDRPhyShuOffset, 1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
444
445 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10 + u4DDRPhyShuOffset, 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0);
446 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10 + u4DDRPhyShuOffset, 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1);
447
448 // Set 1 to be make TX DQS/DQ/DQM PI take effect when TX OE low, for new cross rank mode.
449 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2 + u4DDRPhyShuOffset, 1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0);
450 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2 + u4DDRPhyShuOffset, 1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1);
451
452 // Default settings before init
453 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11 + u4DDRPhyShuOffset, 1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0);
454 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11 + u4DDRPhyShuOffset, 1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1);
455 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11 + u4DDRPhyShuOffset, 1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA);
456
457 // vReplaceDVInit
458 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10 + u4DDRPhyShuOffset, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
459 }
460
461 #if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration
Enable_TxWDQS(DRAMC_CTX_T * p,U32 u4DDRPhyShuOffset,U16 u2Freq)462 void Enable_TxWDQS(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq)
463 {
464 #if ENABLE_LP4Y_DFS
465 U8 DQSB_READ_BASE = u2Freq<=800 ? 0 : 1; // for LP4Y
466 #else
467 U8 DQSB_READ_BASE = 1;
468 #endif
469
470 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13 + u4DDRPhyShuOffset , P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 )
471 | P_Fld(DQSB_READ_BASE, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 )
472 | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0 )
473 | P_Fld(DQSB_READ_BASE, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0 ));
474 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13 + u4DDRPhyShuOffset , P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 )
475 | P_Fld(DQSB_READ_BASE, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 )
476 | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1 )
477 | P_Fld(DQSB_READ_BASE, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1 ));
478 }
479 #endif
480
481 #if ENABLE_SW_TX_TRACKING & __ETT__
DramcSWTxTracking(DRAMC_CTX_T * p)482 void DramcSWTxTracking(DRAMC_CTX_T *p)
483 {
484 U8 u1MR4OnOff;
485 U8 rankIdx, rankBak;
486 U8 u1SRAMShuLevel = get_shuffleIndex_by_Freq(p);
487 U8 u1CurrentShuLevel;
488 U16 u2MR1819_Base[RANK_MAX][2], u2MR1819_Runtime[RANK_MAX][2];
489 U16 u2DQSOSC_INC[RANK_MAX] = {6}, u2DQSOSC_DEC[RANK_MAX] = {4};
490 U8 u1AdjPI[RANK_MAX][2];
491 U8 u1OriginalPI_DQ[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2];
492 U8 u1UpdatedPI_DQ[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2];
493 U8 u1OriginalPI_DQM[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2];
494 U8 u1UpdatedPI_DQM[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2];
495 U8 u1FreqRatioTX[DRAM_DFS_SHUFFLE_MAX];
496 U8 shuIdx, shuBak, byteIdx;
497
498 for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++)
499 {
500 DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_shuffleIndex(p, shuIdx);
501 if (pDstFreqTbl == NULL)
502 {
503 err("NULL pFreqTbl %d\n", shuIdx);
504 while (1);
505 }
506
507 if (pDstFreqTbl->freq_sel == LP4_DDR800)
508 {
509 u1FreqRatioTX[shuIdx] = 0;
510 }
511 else
512 {
513 u1FreqRatioTX[shuIdx] = ((GetFreqBySel(p, pDstFreqTbl->freq_sel)) * 8) / p->frequency;
514 msg("[SWTxTracking] ShuLevel=%d, Ratio[%d]=%d (%d, %d)\n", u1SRAMShuLevel, shuIdx, u1FreqRatioTX[shuIdx], GetFreqBySel(p, pDstFreqTbl->freq_sel), p->frequency);
515 }
516 }
517
518 msg("[SWTxTracking] channel=%d\n", p->channel);
519 rankBak = u1GetRank(p);
520 shuBak = p->ShuRGAccessIdx;
521
522 u1CurrentShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP);
523
524 for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++)
525 {
526 if (shuIdx == p->pDFSTable->shuffleIdx) {
527 p->ShuRGAccessIdx = u1CurrentShuLevel;
528 } else {
529 LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel);
530 p->ShuRGAccessIdx = !u1CurrentShuLevel;
531 }
532
533 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
534 {
535 vSetRank(p, rankIdx);
536
537 u1OriginalPI_DQ[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B0);
538 u1OriginalPI_DQ[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B1);
539
540 u1OriginalPI_DQM[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B0);
541 u1OriginalPI_DQM[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B1);
542 }
543 }
544
545 u1MR4OnOff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), HMR4_REFRDIS);
546 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
547
548 p->ShuRGAccessIdx = u1CurrentShuLevel;
549
550 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
551 {
552 vSetRank(p, rankIdx);
553
554 u2DQSOSC_INC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_INC);
555 u2DQSOSC_DEC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC);
556
557 u2MR1819_Base[p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0);
558 u2MR1819_Base[p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0_B1);
559
560 DramcDQSOSCAuto(p);
561
562 u2MR1819_Runtime[p->rank][0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
563 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
564 {
565 u2MR1819_Runtime[p->rank][1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
566 }
567 else
568 {
569 u2MR1819_Runtime[p->rank][1] = u2MR1819_Runtime[p->rank][0];
570 }
571
572 //INC : MR1819>base. PI-
573 //DEC : MR1819<base. PI+
574 for (byteIdx = 0; byteIdx < 2; byteIdx++)
575 {
576 U16 deltaMR1819 = 0;
577
578 if (u2MR1819_Runtime[p->rank][byteIdx] >= u2MR1819_Base[p->rank][byteIdx])
579 {
580 deltaMR1819 = u2MR1819_Runtime[p->rank][byteIdx] - u2MR1819_Base[p->rank][byteIdx];
581 u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_INC[rankIdx];
582 for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++)
583 {
584 u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
585 u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
586 msg("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d INC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
587 , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_INC[rankIdx]
588 , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]);
589 }
590 }
591 else
592 {
593 deltaMR1819 = u2MR1819_Base[p->rank][byteIdx] - u2MR1819_Runtime[p->rank][byteIdx];
594 u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_DEC[rankIdx];
595 for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++)
596 {
597 u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
598 u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
599 msg("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d DEC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
600 , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_DEC[rankIdx]
601 , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]);
602 }
603 }
604 }
605 }
606
607 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_TXUPDMODE);
608
609 p->ShuRGAccessIdx = !u1CurrentShuLevel;
610 for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++)
611 {
612 LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel);
613
614 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
615 {
616 vSetRank(p, rankIdx);
617
618 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
619 P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
620 P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0));
621 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
622 P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
623 P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1));
624 }
625
626 DramcSaveToShuffleSRAM(p, !u1CurrentShuLevel, shuIdx);
627 }
628
629 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_MANUTXUPD);
630
631 while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B0_DONE) != 1) && (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B1_DONE) != 1))
632 {
633 mcDELAY_US(1);
634 }
635
636 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_TXUPDMODE);
637 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_MANUTXUPD);
638
639 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), u1MR4OnOff, HMR4_REFRDIS);
640
641 vSetRank(p, rankBak);
642 p->ShuRGAccessIdx = shuBak;
643 }
644 #endif
645
646
647 #if ENABLE_RX_TRACKING
DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T * p)648 void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p)
649 {
650 U8 ii, backup_rank;
651 U32 u4WbrBackup = GetDramcBroadcast();
652
653 backup_rank = u1GetRank(p);
654 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
655
656 //Enable RX_FIFO macro DIV4 clock CG
657 vIO32WriteFldAlign((DDRPHY_REG_MISC_CG_CTRL1), 0xffffffff, MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL);
658
659 for (ii = RANK_0; ii < p->support_rank_num; ii++)
660 {
661 vSetRank(p, ii);
662
663 //DVS mode to RG mode
664 vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0);
665 vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1);
666
667 //Turn off F_DLY individual calibration option (CTO_AGENT_RDAT cannot separate DR/DF error)
668 //tracking rising and update rising/falling together
669 vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x1, RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0);
670 vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x1, RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1);
671
672 //DQ/DQM/DQS DLY MAX/MIN value under Tracking mode
673 /* DQS, DQ, DQM (DQ, DQM are tied together now) -> controlled using DQM MAX_MIN */
674
675 /* Byte 0 */
676 vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS3), P_Fld(0x0, RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0) | P_Fld(0xff, RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0));
677 vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS4), P_Fld(0x0, RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0) | P_Fld(0x1ff, RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0));
678
679 /* Byte 1 */
680 vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS3), P_Fld(0x0, RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1) | P_Fld(0xff, RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1));
681 vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS4), P_Fld(0x0, RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1) | P_Fld(0x1ff, RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1));
682
683 //Threshold for LEAD/LAG filter
684 vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS1), P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD) | P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG));
685 vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS1), P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD) | P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG));
686
687 //DQ/DQS Rx DLY adjustment for tracking mode
688 vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0) | P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0));
689 vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1) | P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1));
690
691 vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0) | P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0));
692 vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1) | P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1));
693
694 }
695 vSetRank(p, backup_rank);
696
697 //Tracking lead/lag counter >> Rx DLY adjustment fixed to 1
698 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x0, B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0);
699 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x0, B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1);
700
701 //DQIEN pre-state option to block update for RX ASVA 1-2
702 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0);
703 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1);
704
705 DramcBroadcastOnOff(u4WbrBackup);
706 }
707 #endif
708
DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T * p)709 void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
710 {
711 U8 u1DVS_Delay;
712 U8 u1DVS_En=1;
713 U32 u4WbrBackup = GetDramcBroadcast();
714 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
715
716 //Monitor window size setting
717 //DDRPHY.SHU*_B*_DQ5.RG_RX_ARDQS0_DVS_DLY_B* (suggested value from A-PHY owner)
718 //WHITNEY_TO_BE_PORTING
719 #if (fcFOR_CHIP_ID == fcMargaux)
720 // 6400 5500 4266 3733 3200 2400 1600 1200 800
721 //UI 156p 181p 234p 268p 312p 417p 625p 833p 1250p
722 //DVS_EN O O O O O O X X X
723 //INI 1 2 3 N=5 N=5 N=7 N=12 N=15 N=15
724 //DVS delay O O O X X X X X X
725 //calibration
726
727 if(p->frequency >= 3200)
728 {
729 u1DVS_Delay =1;
730 }
731 else if(p->frequency >= 2250)
732 {
733 u1DVS_Delay = 2;
734 }
735 else if(p->frequency >= 2133)
736 {
737 u1DVS_Delay = 3;
738 }
739 else if(p->frequency >= 1600)
740 {
741 u1DVS_Delay =5;
742 }
743 else if(p->frequency >= 1200)
744 {
745 u1DVS_Delay =7;
746 }
747 else if(p->frequency >= 800)
748 {
749 u1DVS_Delay =12;
750 u1DVS_En =0;
751 }
752 else
753 {
754 u1DVS_Delay =15;
755 u1DVS_En =0;
756 }
757 #endif
758
759 vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ5), u1DVS_Delay, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
760 vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ5), u1DVS_Delay, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
761
762 /* Bian_co HW design issue: run-time PBYTE flag will lose it's function and become per-bit -> set to 0 */
763 vIO32WriteFldMulti((DDRPHY_REG_SHU_B0_DQ7), P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
764 | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0));
765 vIO32WriteFldMulti((DDRPHY_REG_SHU_B1_DQ7), P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
766 | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1));
767
768 //Enable A-PHY DVS LEAD/LAG
769 vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ11), u1DVS_En, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
770 vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ11), u1DVS_En, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
771
772 DramcBroadcastOnOff(u4WbrBackup);
773 }
774
775 #if ENABLE_RX_TRACKING
DramcRxInputDelayTrackingHW(DRAMC_CTX_T * p)776 void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p)
777 {
778 DRAM_CHANNEL_T channel_bak = p->channel;
779 U8 ii, backup_rank;
780 U32 u4WbrBackup = GetDramcBroadcast();
781 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
782
783 vSetPHY2ChannelMapping(p, CHANNEL_A);
784 backup_rank = u1GetRank(p);
785
786 //Rx DLY tracking setting (Static)
787 vIO32WriteFldMulti((DDRPHY_REG_B0_RXDVS0),
788 P_Fld(1, B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0) |
789 P_Fld(0, B0_RXDVS0_R_RX_RANKINCTL_B0) |
790 P_Fld(1, B0_RXDVS0_R_RX_RANKINSEL_B0));
791
792 vIO32WriteFldMulti((DDRPHY_REG_B1_RXDVS0),
793 P_Fld(1, B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1) |
794 P_Fld(0, B1_RXDVS0_R_RX_RANKINCTL_B1) |
795 P_Fld(1, B1_RXDVS0_R_RX_RANKINSEL_B1));
796
797 vIO32WriteFldMulti((DDRPHY_REG_B0_DQ9), P_Fld(0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 | P_Fld(0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0)));
798 vIO32WriteFldMulti((DDRPHY_REG_B1_DQ9), P_Fld(0x1, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1));
799 vIO32WriteFldMulti((DDRPHY_REG_CA_CMD9), P_Fld(0, CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_VALID_LAT_CA));
800
801 //Rx DLY tracking function CG enable
802 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
803 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
804
805 //Rx DLY tracking lead/lag counter enable
806 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0);
807 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1);
808
809 //fra 0: origin mode (use LEAD/LAG rising tracking) 1: new mode (use LEAD/LAG rising/fall tracking, more faster)
810 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS1), 1, B0_RXDVS1_F_LEADLAG_TRACK_B0);
811 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS1), 1, B1_RXDVS1_F_LEADLAG_TRACK_B1);
812
813 for (ii = RANK_0; ii < RANK_MAX; ii++)
814 {
815 vSetRank(p, ii);
816
817 //Rx DLY tracking update enable (HW mode)
818 vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2),
819 P_Fld(2, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0) |
820 P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0) |
821 P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0));
822
823 vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2),
824 P_Fld(2, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1) |
825 P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1) |
826 P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1));
827 }
828 vSetRank(p, backup_rank);
829
830 //Rx DLY tracking: "TRACK_CLR" let rx_dly reload the correct dly setting
831 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 1, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
832 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 1, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
833 vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
834 vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
835
836 DramcBroadcastOnOff(u4WbrBackup);
837 }
838 #endif
839
840 ///TODO: wait for porting +++
841 #if __A60868_TO_BE_PORTING__
842 #if RX_DLY_TRACK_ONLY_FOR_DEBUG
DramcRxDlyTrackDebug(DRAMC_CTX_T * p)843 void DramcRxDlyTrackDebug(DRAMC_CTX_T *p)
844 {
845 /* indicate ROW_ADR = 2 for dummy write & read for Rx dly track debug feature, avoid pattern overwrite by MEM_TEST
846 * pattern(0xAAAA5555) locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */
847
848 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(2, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
849 | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
850 | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN));
851 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(2, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR)
852 | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR)
853 | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN));
854 vIO32WriteFldAlign_All(DRAMC_REG_RK0_DUMMY_RD_BK, 0, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK);
855 vIO32WriteFldAlign_All(DRAMC_REG_RK1_DUMMY_RD_BK, 0, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK);
856
857 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA0, 0xAAAA5555);
858 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA1, 0xAAAA5555);
859 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA2, 0xAAAA5555);
860 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA3, 0xAAAA5555);
861 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA0, 0xAAAA5555);
862 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA1, 0xAAAA5555);
863 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA2, 0xAAAA5555);
864 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA3, 0xAAAA5555);
865
866 //disable Rx dly track debug and clear status lock
867 vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
868 | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
869 | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
870
871 //trigger dummy write pattern 0xAAAA5555
872 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
873 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
874
875 // enable Rx dly track debug feature
876 vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
877 | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
878 | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
879 }
880
DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T * p)881 void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p)
882 {
883 U32 backup_rank, u1ChannelBak, u4value;
884 U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;//channel A/B ...
885
886 u1ChannelBak = p->channel;
887 backup_rank = u1GetRank(p);
888
889 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
890 {
891 p->channel = u1ChannelIdx;
892
893 u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO18));
894 //msg("\nCH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m\n",u1ChannelIdx,u4value);
895 if (u4value & 1)
896 {
897 msg("=== CH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m, %s %s shu: %d\n", u1ChannelIdx, u4value,
898 u4value & 0x2? "RK0: fail":"",u4value&0x4?"RK1: fail":"", (u4value >> 4) & 0x3);
899 }
900 }
901 }
902 #endif
903
904 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
905 #if (__ETT__ || CPU_RW_TEST_AFTER_K)
DramcPrintRXDQDQSStatus(DRAMC_CTX_T * p,U8 u1Channel)906 void DramcPrintRXDQDQSStatus(DRAMC_CTX_T *p, U8 u1Channel)
907 {
908 U8 u1RankIdx, u1RankMax, u1ChannelBak, u1ByteIdx, ii;
909 U32 u4ResultDQS_PI, u4ResultDQS_UI, u4ResultDQS_UI_P1;
910 U8 u1Dqs_pi[DQS_BIT_NUMBER], u1Dqs_ui[DQS_BIT_NUMBER], u1Dqs_ui_P1[DQS_BIT_NUMBER];
911 U16 u2TmpValue, u2TmpUI[DQS_NUMBER], u2TmpPI[DQS_NUMBER];
912 U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak;
913 U32 backup_rank;
914 U8 u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1;
915
916 u1ChannelBak = p->channel;
917 vSetPHY2ChannelMapping(p, u1Channel);
918 backup_rank = u1GetRank(p);
919
920 if (p->support_rank_num == RANK_DUAL)
921 u1RankMax = RANK_MAX;
922 else
923 u1RankMax = RANK_1;
924
925 for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
926 {
927 vSetRank(p, u1RankIdx);
928 msg("[RXDQDQSStatus] CH%d, RK%d\n", p->channel, u1RankIdx);
929 if (u1RankIdx == 0)
930 u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO22));
931 if (u1RankIdx == 1)
932 u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO23));
933
934 u1DQX_B0 = u4ResultDQS_PI & 0xff;
935 u1DQS0 = (u4ResultDQS_PI >> 8) & 0xff;
936 u1DQX_B1 = (u4ResultDQS_PI >> 16) & 0xff;
937 u1DQS1 = (u4ResultDQS_PI >> 24) & 0xff;
938
939 msg("DQX_B0, DQS0, DQX_B1, DQS1 =(%d, %d, %d, %d)\n\n", u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1);
940
941 }
942 vSetRank(p, backup_rank);
943
944 p->channel = u1ChannelBak;
945 vSetPHY2ChannelMapping(p, u1ChannelBak);
946 }
947 #endif
948 #endif
949
DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T * p,bool bEn)950 void DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T *p, bool bEn)
951 {
952 if (bEn == 1)
953 {
954 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)//Retry once
955 | P_Fld(1, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
956 | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
957 | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN)
958 | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE)
959 | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE)
960 | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS));
961 }
962 else
963 {
964 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
965 | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
966 | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN));
967 }
968 return;
969 }
970
DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T * p,bool bEn)971 void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn)
972 {
973 U8 backup_rank = p->rank;
974 U8 rankIdx;
975
976 if (bEn == 1)
977 {
978 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent
979 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DQSG_DMYRD_EN)
980 | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM)
981 | P_Fld(1, DUMMY_RD_DUMMY_RD_SW));
982 for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++)
983 {
984 vSetRank(p, rankIdx);
985 vIO32WriteFldAlign_All(DRAMC_REG_RK_DUMMY_RD_ADR, 0, RK_DUMMY_RD_ADR_DMY_RD_LEN);
986 }
987 vSetRank(p, backup_rank);
988 }
989 else
990 {
991 }
992 return;
993 }
994
995 #endif // __A60868_TO_BE_PORTING__
996
997 #ifdef DUMMY_READ_FOR_TRACKING
DramcDummyReadAddressSetting(DRAMC_CTX_T * p)998 void DramcDummyReadAddressSetting(DRAMC_CTX_T *p)
999 {
1000 U8 backup_channel = p->channel, backup_rank = p->rank;
1001 U8 channelIdx, rankIdx;
1002 dram_addr_t dram_addr;
1003
1004 for (channelIdx = CHANNEL_A; channelIdx < CHANNEL_NUM; channelIdx++)
1005 {
1006 vSetPHY2ChannelMapping(p, channelIdx);
1007 for (rankIdx = RANK_0; rankIdx < RANK_MAX; rankIdx++)
1008 {
1009 vSetRank(p, rankIdx);
1010
1011 dram_addr.ch = channelIdx;
1012 dram_addr.rk = rankIdx;
1013
1014 get_dummy_read_addr(&dram_addr);
1015 msg3("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n",
1016 channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col);
1017
1018 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR2), P_Fld(dram_addr.row, RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR)
1019 | P_Fld(dram_addr.bk, RK_DUMMY_RD_ADR2_DMY_RD_BK));
1020 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), P_Fld(dram_addr.col, RK_DUMMY_RD_ADR_DMY_RD_COL_ADR)
1021 | P_Fld(0, RK_DUMMY_RD_ADR_DMY_RD_LEN));
1022 }
1023 }
1024
1025 vSetPHY2ChannelMapping(p, backup_channel);
1026 vSetRank(p, backup_rank);
1027
1028 }
1029
DramcDummyReadForTrackingEnable(DRAMC_CTX_T * p)1030 void DramcDummyReadForTrackingEnable(DRAMC_CTX_T *p)
1031 {
1032 U8 backup_rank = p->rank;
1033 U8 rankIdx;
1034
1035 /* Dummy read pattern (Better efficiency during rx dly tracking) DE: YH Tsai, Wei-jen */
1036 for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++)
1037 {
1038 vSetRank(p, rankIdx);
1039
1040 vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA0, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0
1041 vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA1, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1
1042 vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA2, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2
1043 vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA3, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3
1044 }
1045 vSetRank(p, backup_rank);
1046
1047 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent
1048
1049 #if 0//__ETT__
1050 /* indicate ROW_ADR = 2 for Dummy Write pattern address, in order to avoid pattern will be overwrited by MEM_TEST(test range 0xffff)
1051 * Pattern locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */
1052 dram_addr_t dram_addr;
1053
1054 dram_addr.ch = 0;
1055 dram_addr.rk = 0;
1056 get_dummy_read_addr(&dram_addr);
1057
1058 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
1059 | P_Fld(dram_addr.col, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
1060 | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN));
1061 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_BK), dram_addr.bk, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK);
1062
1063 dram_addr.rk = 1;
1064 get_dummy_read_addr(&dram_addr);
1065
1066 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR)
1067 | P_Fld(dram_addr.col, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR)
1068 | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN));
1069 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_BK), dram_addr.bk, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK);
1070
1071 /* trigger dummy write pattern 0xAAAA5555 */
1072 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
1073 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
1074 #else
1075 DramcDummyReadAddressSetting(p);
1076 #endif
1077
1078 /* DUMMY_RD_RX_TRACK = 1:
1079 * During "RX input delay tracking enable" and "DUMMY_RD_EN=1" Dummy read will force a read command to a certain rank,
1080 * ignoring whether or not EMI has executed a read command to that certain rank in the past 4us.
1081 */
1082
1083 if (p->frequency >= 1600)
1084 {
1085 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DMY_RD_RX_TRACK) | P_Fld(1, DUMMY_RD_DUMMY_RD_EN));
1086 msg("High Freq DUMMY_READ_FOR_TRACKING: ON\n");
1087 }
1088 else
1089 {
1090 msg("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n");
1091 }
1092
1093 return;
1094 }
1095 #endif
1096
1097 #ifdef IMPEDANCE_HW_SAVING
DramcImpedanceHWSaving(DRAMC_CTX_T * p)1098 void DramcImpedanceHWSaving(DRAMC_CTX_T *p)
1099 {
1100 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_HWSAVE_EN);
1101 }
1102 #endif
1103
1104 #ifdef IMPEDANCE_TRACKING_ENABLE
DramcImpedanceTrackingEnable(DRAMC_CTX_T * p)1105 void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
1106 {
1107 U8 u1CHAB_en = DISABLE;
1108 #if 0 //Impedance tracking offset for DRVP+2
1109 vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL1, P_Fld(2, IMPEDAMCE_CTRL1_DQS1_OFF) | P_Fld(2, IMPEDAMCE_CTRL1_DOS2_OFF));
1110 vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL2, P_Fld(2, IMPEDAMCE_CTRL2_DQ1_OFF) | P_Fld(2, IMPEDAMCE_CTRL2_DQ2_OFF));
1111 #endif
1112
1113 //Write (DRAMC _BASE+ 0x8B) [31:0] = 32'he4000000//enable impedance tracking
1114 //u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE;// @tg Only CHA do Impcal tracking for Margaux
1115 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);//Set CHA this bit to enable dual channel tracking
1116
1117 //During shuffle, after CH_A IMP update done, CH_B has no enough time to update (IMPCAL_IMPCAL_DRVUPDOPT=1)
1118 //enable ECO function for impedance load last tracking result of previous shuffle level (IMPCAL_IMPCAL_CHGDRV_ECO_OPT=1)
1119 //enable ECO function for impcal_sm hange when DRVP>=0x1D (IMPCAL_IMPCAL_SM_ECO_OPT=1)
1120 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_HW) | P_Fld(0, MISC_IMPCAL_IMPCAL_EN) |
1121 P_Fld(1, MISC_IMPCAL_IMPCAL_SWVALUE_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_NEW_OLD_SL) |
1122 P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT) |
1123 P_Fld(1, MISC_IMPCAL_IMPCAL_SM_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPBINARY) |
1124 P_Fld(1, MISC_IMPCAL_DRV_ECO_OPT));
1125
1126 //dual channel continuously tracking @ system busy, self-refresh, Hhbrid-S1
1127 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, 0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT);
1128 //@tg.Only CHA do Impcal tracking, CHB sync CHA result value
1129 vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
1130 P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
1131 vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
1132 P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
1133
1134 // no update imp CA, because CA is unterm now
1135 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV);
1136
1137 // CH_A set 1, CH_B set 0 (mp setting)
1138 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
1139 P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
1140 P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting
1141 P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting
1142 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
1143 P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
1144 P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting
1145 P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting
1146 #if (CHANNEL_NUM > 2)
1147 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV));
1148 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV));
1149 #endif
1150
1151 //Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode)
1152 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF); //@Maoauo, Wait AB refresh to avoid IO drive via logic design
1153 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DQDRVSWUPD);
1154 }
1155 #endif
1156
1157 /* divRoundClosest() - to round up to the nearest integer
1158 * discard four, but treat five as whole (of decimal points)
1159 */
divRoundClosest(const int n,const int d)1160 static int divRoundClosest(const int n, const int d)
1161 {
1162 return ((n < 0) ^ (d < 0))? ((n - d / 2) / d): ((n + d / 2) / d);
1163 }
1164
1165
1166 #if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
FreqJumpRatioCalculation(DRAMC_CTX_T * p)1167 void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
1168 {
1169 U32 shuffle_src_freq, shuffle_dst_index, jump_ratio_index;
1170 U16 u2JumpRatio[12] = {0}; /* Used to record __DBQUOTE_ANCHOR__ calulation results */
1171 U16 u2Freq = 0;
1172
1173 /* Calculate jump ratios and save to u2JumpRatio array */
1174 jump_ratio_index = 0;
1175
1176 if (p->frequency != 400)
1177 {
1178 shuffle_src_freq = p->frequency;
1179 for (shuffle_dst_index = DRAM_DFS_SHUFFLE_1; shuffle_dst_index < DRAM_DFS_SHUFFLE_MAX; shuffle_dst_index++)
1180 {
1181 DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_shuffleIndex(p, shuffle_dst_index);
1182 if (pDstFreqTbl == NULL)
1183 {
1184 err("NULL pFreqTbl\n");
1185 #if __ETT__
1186 while (1);
1187 #endif
1188 }
1189 #if 0 //cc mark since been removed in new flow
1190 if (pDstFreqTbl->freq_sel == LP4_DDR800)
1191 {
1192 u2JumpRatio[jump_ratio_index] = 0;
1193 }
1194 else
1195 #endif
1196 {
1197 u2Freq = GetFreqBySel(p, pDstFreqTbl->freq_sel);
1198 u2JumpRatio[jump_ratio_index] = divRoundClosest(u2Freq * 32, shuffle_src_freq);
1199 //u2JumpRatio[jump_ratio_index] = (pDstFreqTbl->frequency/shuffle_src_freq)*32;
1200 //msg3("shuffle_%d=DDR%d / shuffle_%d=DDR%d \n", shuffle_dst_index, pFreqTbl->frequency<<1,
1201 // shuffle_src_index, get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency<<1);
1202 //msg3("Jump_RATIO_%d : 0x%x\n", jump_ratio_index, u2JumpRatio[jump_ratio_index],
1203 // get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency);
1204 }
1205 msg3("Jump_RATIO [%d]: %x\tFreq %d -> %d\tDDR%d -> DDR%d\n", jump_ratio_index, u2JumpRatio[jump_ratio_index], get_shuffleIndex_by_Freq(p), shuffle_dst_index, shuffle_src_freq << 1, u2Freq << 1);
1206 jump_ratio_index++;
1207 }
1208 }
1209
1210 /* Save jumpRatios into corresponding register fields */
1211 vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(u2JumpRatio[0], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)
1212 | P_Fld(u2JumpRatio[1], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1)
1213 | P_Fld(u2JumpRatio[2], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2)
1214 | P_Fld(u2JumpRatio[3], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3));
1215 vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET1, P_Fld(u2JumpRatio[4], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4)
1216 | P_Fld(u2JumpRatio[5], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5)
1217 | P_Fld(u2JumpRatio[6], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6)
1218 | P_Fld(u2JumpRatio[7], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7));
1219 vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET2, P_Fld(u2JumpRatio[8], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8)
1220 | P_Fld(u2JumpRatio[9], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
1221 return;
1222 }
1223 #endif
1224
1225
1226 #if TDQSCK_PRECALCULATION_FOR_DVFS
DramcDQSPrecalculation_preset(DRAMC_CTX_T * p)1227 void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
1228 {
1229 U8 mck, ui, pi;
1230 U8 mck_p1, ui_p1;
1231 U8 byte_idx, rank;
1232 U8 backup_rank;
1233 U8 mck2ui;
1234
1235 backup_rank = u1GetRank(p);
1236
1237 #if 1//(fcFOR_CHIP_ID == fcMargaux)
1238 mck2ui = 4;
1239 #else
1240 ///TODO: use vGet_Div_Mode() instead later
1241 if (vGet_Div_Mode(p) == DIV16_MODE)
1242 mck2ui = 4; /* 1:16 mode */
1243 else if (vGet_Div_Mode(p) == DIV8_MODE)
1244 mck2ui = 3; /* 1: 8 mode */
1245 else
1246 mck2ui = 2; /* 1: 4 mode */
1247 #endif
1248
1249 msg("Pre-setting of DQS Precalculation\n");
1250
1251 for (byte_idx = 0; byte_idx < (p->data_width / DQS_BIT_NUMBER); byte_idx++) {
1252 for (rank = RANK_0; rank < p->support_rank_num; rank++) {
1253 vSetRank(p, rank);
1254
1255 if (byte_idx == 0) {
1256 mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1257 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0);
1258 ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1259 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0);
1260
1261 mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1262 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0);
1263 ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1264 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0);
1265
1266 pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
1267 SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
1268
1269 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI),
1270 P_Fld((mck << mck2ui) + ui, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0) |
1271 P_Fld(pi, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0));
1272 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI),
1273 P_Fld((mck << mck2ui) +ui, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) |
1274 P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0) |
1275 P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0));
1276 } else {
1277 mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1278 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1);
1279 ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1280 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1);
1281
1282 mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1283 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1);
1284 ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1285 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1);
1286
1287 pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
1288 SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
1289
1290 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
1291 P_Fld((mck << mck2ui) + ui, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1) |
1292 P_Fld(pi, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1));
1293 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI),
1294 P_Fld((mck << mck2ui) +ui, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) |
1295 P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1) |
1296 P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0));
1297 }
1298 }
1299 }
1300
1301 vSetRank(p, backup_rank);
1302
1303 /* Disable DDR800semi precal */
1304 if (vGet_Current_ShuLevel(p) == SRAM_SHU6) {///TODO: Confirm DDR800's shuffle
1305 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_PRE_TDQSCK),
1306 0x1, SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE);
1307 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL),
1308 0x1, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN);
1309 }
1310 else
1311 {
1312 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_PRE_TDQSCK),
1313 0x0, SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE);
1314 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL),
1315 0x0, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN);
1316 }
1317 }
1318
1319 #if 0
1320 void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calculation
1321 {
1322 U8 u1ByteIdx, u1RankNum, u1RankBackup = p->rank;
1323 U8 u1ShuLevel = vGet_Current_ShuLevel(p);
1324 U8 u1UI_value, u1PI_value, u1MCK_value;
1325 U16 u2Byte_offset;
1326 U32 u1Delay_Addr[2] = {0}, u1Delay_Fld[2];
1327 REG_FLD_DQS_PRE_K TransferReg;
1328
1329 msg("Pre-setting of DQS Precalculation\n");
1330 reg_msg("Pre-setting of DQS Precalculation\n");
1331
1332 if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7))
1333 { //SHU4, 5, 6, 7
1334 u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30; //Offset of phase0 UI register
1335 u1Delay_Addr[1] = 0x38; //Offset of phase1 UI register
1336 u2Byte_offset = 0xc;
1337 }
1338 else if (u1ShuLevel >= SRAM_SHU8)
1339 { //SHU8, 9
1340 u1Delay_Addr[0] = 0x260; //Offset of phase0 UI register
1341 u1Delay_Addr[1] = 0x268; //Offset of phase1 UI register
1342 u2Byte_offset = 0x4;
1343 }
1344 else //SHU0, 1, 2, 3
1345 {
1346 u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4); //Offset of phase0 UI register
1347 u1Delay_Addr[1] = 0x8; //Offset of phase1 UI register
1348 u2Byte_offset = 0xc;
1349 }
1350
1351 u1Delay_Fld[0] = u1ShuLevel % 2; //Field of phase0 PI and UI
1352 u1Delay_Fld[1] = u1ShuLevel % 4; //Field of phase1 UI
1353
1354 switch (u1Delay_Fld[0]) //Phase0 UI and PI
1355 {
1356 case 0:
1357 TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0;
1358 TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0;
1359 break;
1360 case 1:
1361 TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0;
1362 TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0;
1363 break;
1364 default:
1365 break;
1366 }
1367
1368 if (u1ShuLevel == SRAM_SHU8)
1369 {
1370 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0; //Byte0
1371 TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0; //Byte1
1372 }
1373 else if (u1ShuLevel == SRAM_SHU9)
1374 {
1375 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0; //Byte0
1376 TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0; //Byte1
1377 }
1378 else //(u1ShuLevel < SRAM_SHU8)
1379 {
1380 switch (u1Delay_Fld[1]) //Phase1 UI
1381 {
1382 case 0:
1383 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0;
1384 break;
1385 case 1:
1386 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0;
1387 break;
1388 case 2:
1389 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0;
1390 break;
1391 case 3:
1392 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0;
1393 break;
1394 default:
1395 break;
1396 }
1397 }
1398
1399 for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
1400 {
1401 for (u1RankNum = 0; u1RankNum < p->support_rank_num; u1RankNum++)
1402 {
1403 vSetRank(p, u1RankNum);
1404
1405 if (u1ByteIdx == 0)
1406 {
1407 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED);
1408 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
1409 u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS0IEN);
1410 }
1411 else //Byte1
1412 {
1413 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
1414 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
1415 u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS1IEN);
1416 }
1417
1418 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);//UI
1419 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld); //PI
1420
1421 if (u1ByteIdx == 0)
1422 {
1423 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
1424 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
1425 }
1426 else //Byte1
1427 {
1428 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
1429 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
1430 }
1431
1432 if ((u1ShuLevel == SRAM_SHU8) || (u1ShuLevel == SRAM_SHU9))
1433 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]); //phase1 UI
1434 else
1435 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]); //phase1 UI
1436 }
1437 }
1438 vSetRank(p, u1RankBackup);
1439
1440 return;
1441 }
1442 #endif
1443
DramcDQSPrecalculation_enable(DRAMC_CTX_T * p)1444 void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p)
1445 {
1446 //DQS pre-K new mode
1447 //cc mark removed vIO32WriteFldAlign_All(DRAMC_REG_RK0_PRE_TDQSCK15, 0x1, RK0_PRE_TDQSCK15_SHUFFLE_LEVEL_MODE_SELECT);
1448 //Enable pre-K HW
1449 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW);
1450 //Select HW flow
1451 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS);
1452 //Set Auto save to RG
1453 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL);
1454 }
1455 #endif
1456
1457 #if 0 /* CC mark to use DV initial setting */
1458 void DramcHWGatingInit(DRAMC_CTX_T *p)
1459 {
1460 #ifdef HW_GATING
1461 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1462 0, MISC_SHU_STBCAL_STBCALEN);
1463 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
1464 P_Fld(0, MISC_STBCAL_STBCAL2R) |
1465 //cc mark P_Fld(0,STBCAL_STB_SELPHYCALEN) |
1466 P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
1467 P_Fld(0, MISC_STBCAL_RKCHGMASKDIS) |
1468 P_Fld(0, MISC_STBCAL_REFUICHG) |
1469 P_Fld(1, MISC_STBCAL_PICGEN));
1470
1471 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(1, MISC_STBCAL_DQSIENCG_CHG_EN));
1472 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_CG_RKEN);
1473 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_DQSIENCG_NORMAL_EN);
1474 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMDQSIENCG_EN);
1475
1476 DramcHWDQSGatingTracking_ModeSetting(p);
1477 #endif
1478 }
1479 #endif
1480
DramcHWGatingOnOff(DRAMC_CTX_T * p,U8 u1OnOff)1481 void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
1482 {
1483 #ifdef HW_GATING
1484 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2,
1485 P_Fld(u1OnOff, MISC_DVFSCTL2_R_DVFS_OPTION) |
1486 P_Fld(u1OnOff, MISC_DVFSCTL2_R_DVFS_PARK_N));
1487 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
1488 u1OnOff, MISC_STBCAL2_STB_GERRSTOP);
1489 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1490 u1OnOff, MISC_SHU_STBCAL_STBCALEN);
1491 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1492 u1OnOff, MISC_SHU_STBCAL_STB_SELPHCALEN);
1493 #else
1494 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2,
1495 P_Fld(0x0, MISC_DVFSCTL2_R_DVFS_OPTION) |
1496 P_Fld(0x0, MISC_DVFSCTL2_R_DVFS_PARK_N));
1497 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0,
1498 MISC_STBCAL2_STB_GERRSTOP);
1499 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1500 0, MISC_SHU_STBCAL_STBCALEN);
1501 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1502 0, MISC_SHU_STBCAL_STB_SELPHCALEN);
1503 #endif
1504 }
1505
1506
DramcHWGatingDebugOnOff(DRAMC_CTX_T * p,U8 u1OnOff)1507 void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
1508 {
1509 #ifdef HW_GATING
1510 // STBCAL2_STB_DBG_EN = 0x3, byte0/1 enable
1511 U8 u1EnB0B1 = (u1OnOff == ENABLE)? 0x3: 0x0;
1512
1513 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2,
1514 P_Fld(u1EnB0B1, MISC_STBCAL2_STB_DBG_EN) |
1515 P_Fld(u1OnOff, MISC_STBCAL2_STB_PIDLYCG_IG) |
1516 P_Fld(u1OnOff, MISC_STBCAL2_STB_UIDLYCG_IG) |
1517 P_Fld(u1OnOff, MISC_STBCAL2_STB_GERRSTOP) |
1518 P_Fld(0, MISC_STBCAL2_STB_DBG_CG_AO) |
1519 P_Fld(0, MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT));
1520 #endif
1521
1522 #if ENABLE_RX_FIFO_MISMATCH_DEBUG
1523 vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0);
1524 vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1);
1525 #endif
1526 }
1527
1528 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
1529 #if (__ETT__ || CPU_RW_TEST_AFTER_K)
1530 #if 0 // Please use memeset to initail value, due to different CHANNEL_NUM
1531 U16 u2MaxGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1532 U16 u2MinGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1533 #endif
DramcPrintHWGatingStatus(DRAMC_CTX_T * p,U8 u1Channel)1534 void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel)
1535 {
1536 #ifdef HW_GATING
1537 U8 u1RankIdx, u1RankMax, u1ChannelBak;
1538 U8 u1Dqs_pi[DQS_BIT_NUMBER]={0}, u1Dqs_ui[DQS_BIT_NUMBER]={0}, u1Dqs_ui_P1[DQS_BIT_NUMBER]={0};
1539 U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak;
1540 U32 backup_rank;
1541
1542 u1ChannelBak = p->channel;
1543 vSetPHY2ChannelMapping(p, u1Channel);
1544 backup_rank = u1GetRank(p);
1545
1546 if (p->support_rank_num == RANK_DUAL)
1547 u1RankMax = RANK_MAX;
1548 else
1549 u1RankMax = RANK_1;
1550
1551 MANUDLLFRZ_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), DLLFRZ_CTRL_MANUDLLFRZ);
1552 STBSTATE_OPT_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), MISC_STBCAL_STBSTATE_OPT);
1553
1554 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), 1, DLLFRZ_CTRL_MANUDLLFRZ);
1555 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_STBSTATE_OPT);
1556
1557 for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
1558 {
1559 vSetRank(p, u1RankIdx);
1560 msg("[DramcHWGatingStatus] Channel=%d, Rank=%d\n", p->channel, u1RankIdx);
1561
1562 u1Dqs_pi[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
1563 GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0);
1564 u1Dqs_ui[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
1565 GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0);
1566 u1Dqs_ui_P1[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
1567 GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0);;
1568
1569 u1Dqs_pi[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
1570 GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0);
1571 u1Dqs_ui[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
1572 GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0);
1573 u1Dqs_ui_P1[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
1574 GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0);;
1575
1576 msg("Byte0(ui, pi) =(%d, %d)\n Byte1(ui, pi) =(%d, %d)\n",
1577 u1Dqs_ui[0], u1Dqs_pi[0], u1Dqs_ui[1], u1Dqs_pi[1]);
1578 msg("UI_Phase1 (DQS0~3) =(%d, %d, %d, %d)\n\n",
1579 u1Dqs_ui_P1[0], u1Dqs_ui_P1[1], u1Dqs_ui_P1[2], u1Dqs_ui_P1[3]);
1580 }
1581
1582 vSetRank(p, backup_rank);
1583 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), STBSTATE_OPT_bak, MISC_STBCAL_STBSTATE_OPT);
1584 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), MANUDLLFRZ_bak, DLLFRZ_CTRL_MANUDLLFRZ);
1585
1586 p->channel = u1ChannelBak;
1587 vSetPHY2ChannelMapping(p, u1ChannelBak);
1588 #endif
1589 }
1590
DramcHWGatingTrackingRecord(DRAMC_CTX_T * p,U8 u1Channel)1591 void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
1592 {
1593 #ifdef HW_GATING
1594 #if __A60868_TO_BE_PORTING__
1595 U8 u1RankIdx, u1RankMax, u1Info_NUM, u1Info_Max_MUM = 16;
1596 U8 u1ChannelBak, u1RankBak;
1597
1598 U8 u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI, u1DBG_Dqs0_PI;
1599 U8 u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI, u1DBG_Dqs1_PI;
1600 U16 u4DBG_Dqs0_Info, u4DBG_Dqs1_Info;
1601 U32 u4DBG_Dqs01_Info;
1602
1603 U32 u4Dqs0_MAX_MIN_DLY, u4Dqs1_MAX_MIN_DLY;
1604 U16 u2Dqs0_UI_MAX_DLY, u2Dqs0_PI_MAX_DLY, u2Dqs0_UI_MIN_DLY, u2Dqs0_PI_MIN_DLY;
1605 U16 u2Dqs1_UI_MAX_DLY, u2Dqs1_PI_MAX_DLY, u2Dqs1_UI_MIN_DLY, u2Dqs1_PI_MIN_DLY;
1606 U8 u1ShuffleLevel;
1607
1608 u1ChannelBak = p->channel;
1609 vSetPHY2ChannelMapping(p, u1Channel);
1610 u1RankBak = u1GetRank(p);
1611
1612 if (p->support_rank_num == RANK_DUAL)
1613 u1RankMax = RANK_MAX;
1614 else
1615 u1RankMax = RANK_1;
1616
1617 //Run Time HW Gating Debug Information
1618 //for(u1RankIdx=0; u1RankIdx<u1RankMax; u1RankIdx++)
1619 for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
1620 {
1621 vSetRank(p, u1RankIdx);
1622
1623 u1ShuffleLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL);
1624
1625 msg3("\n[HWGatingTrackingRecord] Channel=%d, Rank=%d, SHU_LEVEL=%d\n", p->channel, u1RankIdx, u1ShuffleLevel);
1626
1627 msg3("Run Time HW Gating Debug Information :\n");
1628 msg3(" B0=(DFS,Lead,Lag,4T, UI, PI), B1=(DFS,Lead,Lag,4T, UI, PI)\n");
1629
1630 for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++)
1631 {
1632 //DFS_ST(Shuffle Level): bit[15:14]
1633 //Shift_R(Lead): bit[13]
1634 //Shift_L(Lag) : bit[12]
1635 //UI_DLY : bit[11:06]
1636 //PI_DLY : bit[05:00]
1637 u4DBG_Dqs01_Info = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B01_STB_DBG_INFO_00 + 0x4 * u1Info_NUM));
1638 u4DBG_Dqs0_Info = (u4DBG_Dqs01_Info >> 0) & 0xffff;
1639 u4DBG_Dqs1_Info = (u4DBG_Dqs01_Info >> 16) & 0xffff;
1640
1641 u1DBG_Dqs0_DFS = (u4DBG_Dqs0_Info >> 14) & 0x03;
1642 u1DBG_Dqs0_Lead = (u4DBG_Dqs0_Info >> 13) & 0x01;
1643 u1DBG_Dqs0_Lag = (u4DBG_Dqs0_Info >> 12) & 0x01;
1644 u1DBG_Dqs0_UI = (u4DBG_Dqs0_Info >> 6) & 0x3f;
1645 u1DBG_Dqs0_PI = (u4DBG_Dqs0_Info >> 0) & 0x3f;
1646
1647 u1DBG_Dqs1_DFS = (u4DBG_Dqs1_Info >> 14) & 0x03;
1648 u1DBG_Dqs1_Lead = (u4DBG_Dqs1_Info >> 13) & 0x01;
1649 u1DBG_Dqs1_Lag = (u4DBG_Dqs1_Info >> 12) & 0x01;
1650 u1DBG_Dqs1_UI = (u4DBG_Dqs1_Info >> 6) & 0x3f;
1651 u1DBG_Dqs1_PI = (u4DBG_Dqs1_Info >> 0) & 0x3f;
1652
1653 if (u1Info_NUM < 10)
1654 {
1655 msg3("Info= %d ", u1Info_NUM);
1656 }
1657 else
1658 {
1659 msg3("Info=%d ", u1Info_NUM);
1660 }
1661
1662 msg3("B0=( %d, %d, %d, %d, %d, %d), B1=( %d, %d, %d, %d, %d, %d)\n",
1663 u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI / 8, u1DBG_Dqs0_UI % 8, u1DBG_Dqs0_PI,
1664 u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI);
1665 }
1666
1667 //Run Time HW Gating Max and Min Value Record
1668 //Run Time HW Gating MAX_DLY UI : bit[27:22]
1669 //Run Time HW Gating MAX_DLY PI : bit[21:16]
1670 //Run Time HW Gating MIN_DLY UI : bit[11:06]
1671 //Run Time HW Gating MIN_DLY PI : bit[05:00]
1672 u4Dqs0_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY));
1673 u2Dqs0_UI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 22) & 0x3f;
1674 u2Dqs0_PI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 16) & 0x3f;
1675 u2Dqs0_UI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 6) & 0x3f;
1676 u2Dqs0_PI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 0) & 0x3f;
1677
1678 u4Dqs1_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B1_STB_MAX_MIN_DLY));
1679 u2Dqs1_UI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 22) & 0x3f;
1680 u2Dqs1_PI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 16) & 0x3f;
1681 u2Dqs1_UI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 6) & 0x3f;
1682 u2Dqs1_PI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 0) & 0x3f;
1683
1684 msg3("B0 = MAX(4T, UI, PI) MIN(4T, UI, PI), B1 = MAX(4T, UI, PI) MIN(4T, UI, PI)\n");
1685 msg3("B0 = MAX( %d, %d, %d) MIN( %d, %d, %d), B1 = MAX( %d, %d, %d) MIN( %d, %d, %d)\n",
1686 u2Dqs0_UI_MAX_DLY / 8, u2Dqs0_UI_MAX_DLY % 8, u2Dqs0_PI_MAX_DLY,
1687 u2Dqs0_UI_MIN_DLY / 8, u2Dqs0_UI_MIN_DLY % 8, u2Dqs0_PI_MIN_DLY,
1688 u2Dqs1_UI_MAX_DLY / 8, u2Dqs1_UI_MAX_DLY % 8, u2Dqs1_PI_MAX_DLY,
1689 u2Dqs1_UI_MIN_DLY / 8, u2Dqs1_UI_MIN_DLY % 8, u2Dqs1_PI_MIN_DLY);
1690 }
1691 vSetRank(p, u1RankBak);
1692 p->channel = u1ChannelBak;
1693 vSetPHY2ChannelMapping(p, u1ChannelBak);
1694 #endif
1695 #endif
1696 }
1697
1698 ///TODO: wait for porting +++
1699 #if __A60868_TO_BE_PORTING__
1700
DramcPrintRXFIFODebugStatus(DRAMC_CTX_T * p)1701 void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p)
1702 {
1703 #if RX_PICG_NEW_MODE
1704 //RX FIFO debug feature, MP setting should enable debug function for Gating error information
1705 //APHY control new mode
1706 U32 u1ChannelBak, u4value;
1707 U8 u1ChannelIdx;
1708
1709 u1ChannelBak = p->channel;
1710
1711 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1712 {
1713 p->channel = u1ChannelIdx;
1714
1715 u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); //DDRPHY NAO bit24~27
1716 if (u4value)
1717 {
1718 msg("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value);
1719 }
1720 }
1721 p->channel = u1ChannelBak;
1722 vSetPHY2ChannelMapping(p, u1ChannelBak);
1723 #endif
1724 }
1725 #endif //#if __ETT__
1726 #endif
1727
1728 #endif /// __A60868_TO_BE_PORTING__
1729 ///TODO: wait for porting +++
1730