1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef _PI_API_H 4 #define _PI_API_H 5 6 /***********************************************************************/ 7 /* Includes */ 8 /***********************************************************************/ 9 10 /***********************************************************************/ 11 /* Constant Define */ 12 /***********************************************************************/ 13 14 #include "dramc_typedefs.h" 15 //#include <soc/addressmap.h> 16 #include <soc/dramc_soc.h> 17 #include <soc/dramc_param.h> 18 19 #define SW_CHANGE_FOR_SIMULATION 0 20 #ifndef FOR_DV_SIMULATION_USED 21 #define FOR_DV_SIMULATION_USED (FALSE) 22 #endif 23 #define DV_SIMULATION_LP4 1 24 #define BYPASS_CALIBRATION 0 25 #define __ETT__ 0 26 #define FT_DSIM_USED 0 27 #define __FLASH_TOOL_DA__ 0 28 #define CFG_ENABLE_DCACHE 0 29 #define CFG_DRAM_CALIB_OPTIMIZATION 1 30 #define GATING_AUTO_K_ENABLE 0 31 #define CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 0 32 #define CFG_DRAM_LOG_TO_STORAGE 0 33 #define CBT_OLDMODE_ENABLE 0 34 #define CBT_AUTO_K_ENABLE 0 35 #define LJPLL_FREQ_DEBUG_LOG 0 36 #define DRAM_AUXADC_CONFIG 0 37 //Bring Up Selection : Do Not open it when normal operation 38 //#define SLT 39 //#define SLT_2400_EXIT_PRELOADER 40 //#define FIRST_BRING_UP 41 //#define DUMP_INIT_RG_LOG_TO_DE //dump init RG settings to DE 42 43 #define ENABLE (1) 44 #define DISABLE (0) 45 #define ON (1) 46 #define OFF (0) 47 #define AUTOK_ON (1) 48 #define AUTOK_OFF (0) 49 #define DCM_ON (1) 50 #define DCM_OFF (0) 51 #define NORMAL_K (1) 52 #define EYESCAN_K (0) 53 54 55 56 #ifndef QT_GUI_Tool 57 #define QT_GUI_Tool 0 58 #define HAPS_FPFG_A60868 0 59 #endif 60 61 62 #define fcA60868 1 63 #define fcPetrus 2 64 #define fcIPM 3 65 #define fcMargaux 4 66 #define fcMouton 5 67 #define fcColgin 6 68 #define fcPalmer 7 69 #define fc8195 8 70 #define fcFOR_CHIP_ID fc8195 71 72 #define __A60868_TO_BE_PORTING__ 0 73 #define __Petrus_TO_BE_PORTING__ 0 74 75 #define VENDOR_SAMSUNG 1 76 #define VENDOR_HYNIX 6 77 #define REVISION_ID_MAGIC 0x9501 78 79 80 #define __LP5_COMBO__ (FALSE) 81 #define FEATURE_RDDQC_K_DMI (FALSE) 82 83 #if FOR_DV_SIMULATION_USED 84 #undef __ETT__ 85 #else 86 //#define __ETT__ 1 /* If you want to disable ETT , please mark all line */ 87 #endif 88 89 #if __ETT__ 90 #define __FLASH_TOOL_DA__ 0 91 #endif 92 93 #if (FEATURE_RDDQC_K_DMI == TRUE) 94 #define RDDQC_ADD_DMI_NUM 2 95 #else 96 #define RDDQC_ADD_DMI_NUM 0 97 #endif 98 99 #if FOR_DV_SIMULATION_USED 100 #define CHANNEL_NUM 2 101 #else 102 #define CHANNEL_NUM 4 103 #endif 104 #define DPM_CH_NUM 2 105 106 107 #define ENABLE_LP4_ZQ_CAL 1 108 #if ENABLE_LP4_ZQ_CAL 109 #define ZQ_SWCMD_MODE 1 110 #define ZQ_RTSWCMD_MODE 0 111 #define ZQ_SCSM_MODE 0 112 #endif 113 114 #define CODE_SIZE_REDUCE 0 115 #define CALIBRATION_SPEED_UP_DEBUG 0 116 #define VENDER_JV_LOG 0 117 118 119 #define DUAL_FREQ_K 1 120 #define SCRAMBLE_EN 1 121 #if 1 //[FOR_CHROMEOS] 122 #define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem. 123 #else 124 #define ENABLE_EYESCAN_GRAPH 1 125 #endif 126 #define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U 127 #define EYESCAN_GRAPH_RX_VREF_STEP 2 128 #define EYESCAN_RX_VREF_RANGE_END 128 129 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10 130 #if (fcFOR_CHIP_ID == fcA60868) 131 #define ENABLE_EYESCAN_CBT 0 132 #define ENABLE_EYESCAN_RX 0 133 #define ENABLE_EYESCAN_TX 0 134 #define ENABLE_VREFSCAN 0 135 #endif 136 137 #define CHECK_HQA_CRITERIA 0 138 #define REDUCE_LOG_FOR_PRELOADER 1 139 #define APPLY_LP4_POWER_INIT_SEQUENCE 1 140 #define ENABLE_READ_DBI 0 141 #define ENABLE_WRITE_DBI 1 142 #define ENABLE_WRITE_DBI_Protect 0 143 #define ENABLE_TX_WDQS 1 144 #define ENABLE_WDQS_MODE_2 0 145 #define ENABLE_DRS 0 146 #define ENABLE_TX_TRACKING 1 147 #define ENABLE_K_WITH_WORST_SI_UI_SHIFT 1 148 #define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1 149 #define DUMP_TA2_WINDOW_SIZE_RX_TX 0 150 #if ENABLE_TX_TRACKING 151 #define ENABLE_SW_TX_TRACKING 0 152 //can only choose 1 to set as 1 in the following 3 define 153 #define DQSOSC_SWCMD 1 154 #define DQSOSC_RTSWCMD 0 155 #define DQSOSC_SCSM 0 156 #endif 157 #define ENABLE_PA_IMPRO_FOR_TX_TRACKING 1 158 #define ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK 1 159 #define ENABLE_RX_TRACKING 0 160 #if ENABLE_RX_TRACKING 161 #define RX_DVS_NOT_SHU_WA 1 162 #endif 163 #define ENABLE_OPEN_LOOP_MODE_OPTION 1 164 #define ENABLE_TMRRI_NEW_MODE 1 165 #define ENABLE_8PHASE_CALIBRATION 1 166 #define ENABLE_DUTY_SCAN_V2 1 167 #define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 168 #define APPLY_DQDQM_DUTY_CALIBRATION 1 169 #define IMPEDANCE_TRACKING_ENABLE 170 #ifdef IMPEDANCE_TRACKING_ENABLE 171 #define IMPEDANCE_HW_CALIBRATION 0 172 #else 173 #define IMPEDANCE_HW_CALIBRATION 0 174 #endif 175 #define IMPEDANCE_HW_SAVING 176 #define IMP_DEBUG_ENABLE 177 #define ENABLE_MIOCK_JMETER 178 #define MIOCK_JMETER_CNT_WA 1 179 #define ENABLE_RUNTIME_MRW_FOR_LP5 1 180 #define ENABLE_RODT_TRACKING 1 181 #define GATING_ADJUST_TXDLY_FOR_TRACKING 1 182 #define TDQSCK_PRECALCULATION_FOR_DVFS 1 183 #define HW_GATING 184 #define ENABLE_RX_FIFO_MISMATCH_DEBUG 1 185 #define VERIFY_CKE_PWR_DOWN_FLOW 0 186 #define CBT_MOVE_CA_INSTEAD_OF_CLK 1 187 #define MRW_CHECK_ONLY 0 188 #define MRW_BACKUP 0 189 #define ENABLE_SAMSUNG_NT_ODT 0 190 #if CODE_SIZE_REDUCE 191 #define DRAMC_MODEREG_CHECK 0 192 #else 193 #define DRAMC_MODEREG_CHECK 1 194 #endif 195 #define DVT_READ_LATENCY_MONITOR 0 196 #define DUMP_ALLSUH_RG 0 197 #define PIN_CHECK_TOOL 0 198 #define ENABLE_DATLAT_BY_FORMULA 1 199 #define ENABLE_RX_AUTOK_MISS_FIRSTPASS_WA 1 200 201 //Debug option 202 #define GATING_ONLY_FOR_DEBUG 0 203 #define ENABLE_RX_AUTOK_DEBUG_MODE 0 204 #define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 205 #if CODE_SIZE_REDUCE || FOR_DV_SIMULATION_USED 206 #define CPU_RW_TEST_AFTER_K 0 207 #define TA2_RW_TEST_AFTER_K 0 208 #else 209 #define CPU_RW_TEST_AFTER_K 1 210 #define TA2_RW_TEST_AFTER_K 1 211 #endif 212 213 #define PINMUX_AUTO_TEST_PER_BIT_CA 0 214 #define PINMUX_AUTO_TEST_PER_BIT_RX 0 215 #define PINMUX_AUTO_TEST_PER_BIT_TX 0 216 217 #define CA_PER_BIT_DELAY_CELL 1 218 #if PINMUX_AUTO_TEST_PER_BIT_CA 219 #undef CA_PER_BIT_DELAY_CELL 220 #define CA_PER_BIT_DELAY_CELL 0 221 #endif 222 223 224 #define GATING_LEADLAG_LOW_LEVEL_CHECK 0 225 226 #if CODE_SIZE_REDUCE 227 #define GATING_AUTO_K_SUPPORT 0 228 #else 229 #define GATING_AUTO_K_SUPPORT 1 230 #endif 231 #if GATING_AUTO_K_ENABLE 232 #define ENABLE_GATING_AUTOK_WA 1 233 #else 234 #define ENABLE_GATING_AUTOK_WA 0 235 #endif 236 237 #define DVT_TEST_RX_FIFO_MISMATCH_IRQ_CLEAN 0 238 239 #define DPM_CONTROL_AFTERK 240 #if __ETT__ 241 #define ENABLE_DBG_2_0_IRQ 242 #endif 243 244 #define ETT_LOAD_DPM 1 245 246 //////////////////////////////////// FIXME start ///////////////////////// 247 #define CMD_CKE_WORKAROUND_FIX 0 248 #define DQS_DUTY_SLT_CONDITION_TEST 0 249 #define DV_SIMULATION_BEFORE_K 0 250 #define DV_SIMULATION_DATLAT 0 251 #define DV_SIMULATION_DBI_ON 0 252 #define DV_SIMULATION_DFS 0 253 #define DV_SIMULATION_GATING 0 254 #define ENABLE_APB_MASK_WRITE 0 255 #define ENABLE_DVFS_BYPASS_MR13_FSP 0 256 #define ENABLE_RODT_TRACKING_SAVE_MCK 0 257 #define ETT_NO_DRAM 0 258 #define EYESCAN_LOG 0 259 #define FSP1_CLKCA_TERM 1 260 #define CBT_FSP1_MATCH_FSP0_UNTERM_WA 1 261 #define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED 262 #define FT_DSIM_USED 0 263 #define GATING_ONLY_FOR_DEBUG 0 264 #define MEASURE_DRAM_POWER_INDEX 0 265 #define REG_ACCESS_PORTING_DGB 0 266 #define RX_PIPE_BYPASS_ENABLE 0 267 #define SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER 0 268 #define SUPPORT_PICG_MONITOR 0 269 #define SUPPORT_REQ_QUEUE_BLOCK_ALE 0 270 #define SUPPORT_REQ_QUEUE_READ_LATERNCY_MONITOR 0 271 #define REFRESH_OVERHEAD_REDUCTION 1 272 #define XRTRTR_NEW_CROSS_RK_MODE 1 273 #define XRTWTW_NEW_CROSS_RK_MODE 1 274 #define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 275 #define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0 276 #define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 277 278 #define TEMP_SENSOR_ENABLE 279 #define ENABLE_REFRESH_RATE_DEBOUNCE 1 280 #define ENABLE_PER_BANK_REFRESH 1 281 #define PER_BANK_REFRESH_USE_MODE 1 282 #define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1 283 #define DRAMC_MODIFIED_REFRESH_MODE 1 284 #define DRAMC_CKE_DEBOUNCE 1 285 #define XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY 286 287 #define SAMSUNG_LP4_NWR_WORKAROUND 1 288 #define AC_TIMING_DERATE_ENABLE 1 289 #define ENABLE_EARLY_BG_CMD 0 290 291 //////////////////////////////////// DVFS ////////////////////////////// 292 #define ENABLE_DVS 1 293 #define DRAMC_DFS_MODE 1 294 #define ENABLE_RTMRW_DEBUG_LOG 0 295 #define ENABLE_TX_REBASE_ODT_WA 0 296 #define ENABLE_DDR800_SOPEN_DSC_WA 1 297 #if ENABLE_TX_WDQS 298 #define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0 299 #endif 300 #define ENABLE_DFS_DEBUG_MODE 0 301 #define DFS_NOQUEUE_FLUSH_ENABLE 1 302 #define DFS_NOQUEUE_FLUSH_LATENCY_CNT 0 303 #define ENABLE_DFS_NOQUEUE_FLUSH_DBG 0 304 #define ENABLE_CONFIG_MCK_4TO1_MUX 0 305 #define ENABLE_TPBR2PBR_REFRESH_TIMING 1 306 #define ENABLE_DFS_TIMING_ENLARGE 0 307 #define ENABLE_DFS_208M_CLOCK 0 308 #define ENABLE_DFS_HW_SAVE_MASK 0 309 #define REPLACE_DFS_RG_MODE 1 310 #define ENABLE_LP4Y_DFS 0 311 #if ENABLE_LP4Y_DFS 312 #define LP4Y_BACKUP_SOLUTION 0 313 #define ENABLE_LP4Y_WA 1 314 #define ENABLE_DFS_RUNTIME_MRW 1 315 #else 316 #define LP4Y_BACKUP_SOLUTION 0 317 #define ENABLE_LP4Y_WA 0 318 #define ENABLE_DFS_RUNTIME_MRW 0 319 #endif 320 #define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION 321 #define ENABLE_RANK_NUMBER_AUTO_DETECTION 1 322 323 #define DDR_HW_AUTOK_POLLING_CNT 100000 324 325 //////////////////////////////////// FIXME end///////////////////////// 326 327 #if (fcFOR_CHIP_ID == fcA60868) 328 #define WORKAROUND_LP5_HEFF 1 329 #undef ENABLE_RUNTIME_MRW_FOR_LP5 330 #define ENABLE_RUNTIME_MRW_FOR_LP5 0 331 #endif 332 333 #if ENABLE_RODT_TRACKING 334 #define GATING_RODT_LATANCY_EN 0 335 #else 336 #define GATING_RODT_LATANCY_EN 1 337 #endif 338 339 #define CHECK_GOLDEN_SETTING (FALSE) 340 #define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 341 #define LP5_GOLDEN_SETTING_CHECKER (FALSE) 342 //#define CMD_PICG_NEW_MODE 1 343 //#define ENABLE_RX_DCM_DPHY 1 344 //#define CLK_FREE_FUN_FOR_DRAMC_PSEL 345 //#define HW_SAVE_FOR_SR 346 347 #if APPLY_LOWPOWER_GOLDEN_SETTINGS 348 #define TX_PICG_NEW_MODE 1 349 #define RX_PICG_NEW_MODE 1 350 #else 351 #define TX_PICG_NEW_MODE 0 352 #define RX_PICG_NEW_MODE 0 353 #endif 354 355 #define DDR_RESERVE_NEW_MODE 1 356 357 #if QT_GUI_Tool || !FOR_DV_SIMULATION_USED 358 #define DV_SIMULATION_INIT_C 1 359 #define SIMULATION_LP4_ZQ 1 360 #define SIMULATION_SW_IMPED 1 361 #define SIMULATION_MIOCK_JMETER 0 362 #define SIMULATION_8PHASE 0 363 #define SIMULATION_RX_INPUT_BUF 0 364 #define SIMUILATION_CBT 1 365 #define SIMULATION_WRITE_LEVELING 1 366 #define SIMULATION_DUTY_CYC_MONITOR 0 367 #define SIMULATION_GATING 1 368 #define SIMULATION_DATLAT 1 369 #define SIMULATION_RX_RDDQC 1 370 #define SIMULATION_RX_PERBIT 1 371 #define SIMULATION_TX_PERBIT 1 372 #define SIMULATION_RX_DVS 0 373 #define SIMULATION_RUNTIME_CONFIG 0 374 #else 375 #define DV_SIMULATION_INIT_C 1 376 #define SIMULATION_LP4_ZQ 1 377 #define SIMULATION_SW_IMPED 1 378 #define SIMULATION_MIOCK_JMETER 0 379 #define SIMULATION_8PHASE 0 380 #define SIMULATION_RX_INPUT_BUF 0 381 #define SIMUILATION_CBT 1 382 #define SIMULATION_WRITE_LEVELING 1 383 #define SIMULATION_DUTY_CYC_MONITOR 0 384 #define SIMULATION_GATING 1 385 #define SIMULATION_DATLAT 1 386 #define SIMULATION_RX_RDDQC 1 387 #define SIMULATION_RX_PERBIT 1 388 #define SIMULATION_TX_PERBIT 1 389 #define SIMULATION_RX_DVS 0 390 #define SIMULATION_RUNTIME_CONFIG 1 391 #endif 392 393 #define DVS_CAL_KEEP_VREF 0xf 394 395 //#define DDR_INIT_TIME_PROFILING 396 #define DDR_INIT_TIME_PROFILING_TEST_CNT 1 397 398 #if __FLASH_TOOL_DA__ 399 #undef PIN_CHECK_TOOL 400 #define PIN_CHECK_TOOL 0 401 #endif 402 //============================================================================= 403 // common 404 #define DQS_BYTE_NUMBER 2 405 #define DQS_BIT_NUMBER 8 406 #define DQ_DATA_WIDTH 16 407 #define DQM_BYTE_NUM 2 408 #define TIME_OUT_CNT 100 409 #define HW_REG_SHUFFLE_MAX 4 410 411 typedef enum 412 { 413 BYTE_0 = 0, 414 BYTE_1 = 1, 415 ALL_BYTES 416 } BYTES_T; 417 418 419 #define LP5_DDR4266_RDBI_WORKAROUND 0 420 #define CBT_O1_PINMUX_WORKAROUND 0 421 #define WLEV_O1_PINMUX_WORKAROUND 0 422 #define WCK_LEVELING_FM_WORKAROUND 0 423 424 425 #define ENABLE_RX_INPUT_BUFF_OFF_K 1 426 427 428 #define DQS_GW_COARSE_STEP 1 429 #define DQS_GW_FINE_START 0 430 #define DQS_GW_FINE_END 32 431 #define DQS_GW_FINE_STEP 4 432 433 #define DQS_GW_UI_PER_MCK 16 434 #define DQS_GW_PI_PER_UI 32 435 436 437 #define DATLAT_TAP_NUMBER 32 438 439 440 #define MAX_RX_DQSDLY_TAPS 511 441 #define MAX_RX_DQDLY_TAPS 252 442 #define RX_VREF_NOT_SPECIFY 0xff 443 #define RX_VREF_DUAL_RANK_K_FREQ 1866 444 #define RX_VREF_RANGE_BEGIN 0 445 #define RX_VREF_RANGE_BEGIN_ODT_OFF 32 446 #define RX_VREF_RANGE_BEGIN_ODT_ON 24 447 #define RX_VREF_RANGE_END 128 448 #define RX_VREF_RANGE_STEP 1 449 #define RX_PASS_WIN_CRITERIA 30 450 #define RDDQC_PINMUX_WORKAROUND 1 451 452 453 #if CODE_SIZE_REDUCE 454 #define TX_AUTO_K_SUPPORT 0 455 #else 456 #define TX_AUTO_K_SUPPORT 1 457 #endif 458 #if TX_AUTO_K_SUPPORT 459 #define TX_AUTO_K_DEBUG_ENABLE 0 460 #define TX_AUTO_K_WORKAROUND 1 461 #define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1 462 #endif 463 #define MAX_TX_DQDLY_TAPS 31 464 #define MAX_TX_DQSDLY_TAPS 31 465 #define TX_OE_EXTEND 0 466 #define TX_DQ_OE_SHIFT_LP5 5 467 #if TX_OE_EXTEND 468 #define TX_DQ_OE_SHIFT_LP4 4 469 #else 470 #define TX_DQ_OE_SHIFT_LP4 3 471 #endif 472 #define TX_DQ_OE_SHIFT_LP3 2 473 #define TX_K_DQM_WITH_WDBI 1 474 #define TX_OE_CALIBATION (!TX_OE_EXTEND) 475 476 #define TX_RETRY_ENABLE 0 477 #if TX_RETRY_ENABLE 478 #define TX_RETRY_CONTROL_BY_SPM 1 479 #define SW_TX_RETRY_ENABLE 0 480 #else 481 #define TX_RETRY_CONTROL_BY_SPM 0 482 #endif 483 484 485 #define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 486 #define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1 487 #define DramcHWDQSGatingTracking_FIFO_MODE 1 488 #define DONT_MOVE_CLK_DELAY 489 490 #define LP4_SHU0_FREQ (1866) 491 #define LP4_SHU8_FREQ (1600) 492 #define LP4_SHU9_FREQ (1600) 493 #define LP4_SHU6_FREQ (1200) 494 #define LP4_SHU5_FREQ (1200) 495 #define LP4_SHU4_FREQ (800) 496 #define LP4_SHU3_FREQ (800) 497 #define LP4_SHU2_FREQ (600) 498 #define LP4_SHU1_FREQ (600) 499 #define LP4_SHU7_FREQ (400) 500 #define LP4_HIGHEST_FREQ LP4_SHU0_FREQ 501 502 #define LP4_SHU0_FREQSEL (LP4_DDR3733) 503 #define LP4_SHU8_FREQSEL (LP4_DDR3200) 504 #define LP4_SHU9_FREQSEL (LP4_DDR3200) 505 #define LP4_SHU6_FREQSEL (LP4_DDR2400) 506 #define LP4_SHU5_FREQSEL (LP4_DDR2400) 507 #define LP4_SHU4_FREQSEL (LP4_DDR1600) 508 #define LP4_SHU3_FREQSEL (LP4_DDR1600) 509 #define LP4_SHU2_FREQSEL (LP4_DDR1200) 510 #define LP4_SHU1_FREQSEL (LP4_DDR1200) 511 #define LP4_SHU7_FREQSEL (LP4_DDR800) 512 513 #if FOR_DV_SIMULATION_USED 514 #define DEFAULT_TEST2_1_CAL 0x55000000 515 #define DEFAULT_TEST2_2_CAL 0xaa000020 516 #else 517 #define DEFAULT_TEST2_1_CAL 0x55000000 518 #define DEFAULT_TEST2_2_CAL 0xaa000100 519 #endif 520 521 522 #if CODE_SIZE_REDUCE 523 #define CBT_AUTO_K_SUPPORT 0 524 #define CBT_OLDMODE_SUPPORT 0 525 #else 526 #define CBT_AUTO_K_SUPPORT 1 527 #define CBT_OLDMODE_SUPPORT 1 528 #endif 529 #define CATRAINING_NUM_LP4 6 530 #define CATRAINING_NUM_LP5 7 531 #define CATRAINING_NUM CATRAINING_NUM_LP5 532 #define LP4_MRFSP_TERM_FREQ 1333 533 #define LP5_MRFSP_TERM_FREQ 1866 534 535 536 #define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION) 537 #define PRINT_CALIBRATION_SUMMARY_DETAIL 1 538 #define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0 539 540 #if 1 541 #define ETT_PRINT_FORMAT 542 #endif 543 544 #if !CODE_SIZE_REDUCE 545 //#define FOR_HQA_TEST_USED 546 //#define FOR_HQA_REPORT_USED 547 #endif 548 //#define DEVIATION // for special test used 549 550 //Run Time Config 551 //#define DUMMY_READ_FOR_TRACKING 552 #define ZQCS_ENABLE_LP4 553 #if ENABLE_LP4Y_DFS 554 #undef ZQCS_ENABLE_LP4 555 #endif 556 #ifndef ZQCS_ENABLE_LP4 557 #define ENABLE_SW_RUN_TIME_ZQ_WA 558 #endif 559 560 //============================ For Future DVT Definition ================================= 561 562 #define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1 563 #define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1 564 #define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1 565 #define RDSEL_TRACKING_EN 1 566 #define RDSEL_TRACKING_TH 2133 567 #define ENABLE_DFS_SSC_WA 0 568 #define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1 569 #define ENABLE_DDR400_OPEN_LOOP_MODE_OPTION 0 570 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION 571 #define OPEN_LOOP_MODE_CLK_TOGGLE_WA 1 572 #else 573 #define OPEN_LOOP_MODE_CLK_TOGGLE_WA 0 574 #endif 575 576 //============================================================================= 577 //#define DDR_BASE 0x40000000ULL //for DV sim and ett_test.c 578 /***********************************************************************/ 579 /* Defines */ 580 /***********************************************************************/ 581 #define CBT_LOW_FREQ 0 582 #define CBT_HIGH_FREQ 1 583 #define CBT_UNKNOWN_FREQ 0xFF 584 585 586 #if !__ETT__ 587 588 #if (FOR_DV_SIMULATION_USED==0) && !defined(SLT) 589 590 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION CFG_DRAM_CALIB_OPTIMIZATION 591 #else 592 593 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 594 #endif 595 #define EMMC_READY CFG_DRAM_CALIB_OPTIMIZATION 596 #define BYPASS_VREF_CAL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 597 #define BYPASS_CBT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 598 #define BYPASS_DATLAT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 599 #define BYPASS_WRITELEVELING (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 600 #define BYPASS_RDDQC (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 601 #define BYPASS_RXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 602 #define BYPASS_TXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 603 #define BYPASS_TXOE (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 604 #define BYPASS_GatingCal (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 605 #define BYPASS_CA_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 606 //#define BYPASS_TX_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 607 #else 608 // ETT 609 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 610 #define EMMC_READY 0 611 #define BYPASS_VREF_CAL 1 612 #define BYPASS_CBT 1 613 #define BYPASS_DATLAT 1 614 #define BYPASS_WRITELEVELING 1 615 #define BYPASS_RDDQC 1 616 #define BYPASS_RXWINDOW 1 617 #define BYPASS_TXWINDOW 1 618 #define BYPASS_TXOE 1 619 #define BYPASS_GatingCal 1 620 #define BYPASS_CA_PER_BIT_DELAY_CELL CA_PER_BIT_DELAY_CELL 621 //#define BYPASS_TX_PER_BIT_DELAY_CELL 0 622 #endif 623 624 #define ENABLE_PINMUX_FOR_RANK_SWAP 0 625 626 //======================== FIRST_BRING_UP Init Definition ===================== 627 #ifdef FIRST_BRING_UP 628 629 //#define USE_CLK26M 630 631 #undef DUAL_FREQ_K 632 #define DUAL_FREQ_K 0 633 634 #undef TDQSCK_PRECALCULATION_FOR_DVFS 635 #define TDQSCK_PRECALCULATION_FOR_DVFS 0 636 637 //#undef CHANNEL_NUM 638 //#define CHANNEL_NUM 4 639 640 #undef REPLACE_DFS_RG_MODE 641 #define REPLACE_DFS_RG_MODE 1 642 643 #undef ENABLE_DUTY_SCAN_V2 644 #define ENABLE_DUTY_SCAN_V2 0 645 646 #undef ENABLE_DRS 647 #define ENABLE_DRS 0 648 649 #undef ENABLE_CA_TRAINING 650 #define ENABLE_CA_TRAINING 1 651 #undef ENABLE_WRITE_LEVELING 652 #define ENABLE_WRITE_LEVELING 1 653 654 //#undef REDUCE_LOG_FOR_PRELOADER 655 //#define REDUCE_LOG_FOR_PRELOADER 0 656 657 #undef ENABLE_RX_INPUT_BUFF_OFF_K 658 #define ENABLE_RX_INPUT_BUFF_OFF_K 0 659 660 #undef REDUCE_CALIBRATION_OLYMPUS_ONLY 661 #define REDUCE_CALIBRATION_OLYMPUS_ONLY 0 662 663 #undef APPLY_LOWPOWER_GOLDEN_SETTINGS 664 #define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 665 666 //#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3 667 668 #undef TX_K_DQM_WITH_WDBI 669 #define TX_K_DQM_WITH_WDBI 0 670 671 #undef ENABLE_EYESCAN_GRAPH 672 #define ENABLE_EYESCAN_GRAPH 0 673 674 #undef ENABLE_TX_TRACKING 675 #undef ENABLE_SW_TX_TRACKING 676 #define ENABLE_TX_TRACKING 0 677 #define ENABLE_SW_TX_TRACKING 0 678 679 #undef ENABLE_RX_TRACKING 680 #define ENABLE_RX_TRACKING 0 681 682 #undef RDSEL_TRACKING_EN 683 #define RDSEL_TRACKING_EN 0 684 685 #undef GATING_ADJUST_TXDLY_FOR_TRACKING 686 #define GATING_ADJUST_TXDLY_FOR_TRACKING 0 687 688 #undef ENABLE_PER_BANK_REFRESH 689 #define ENABLE_PER_BANK_REFRESH 1 690 691 #undef ENABLE_TPBR2PBR_REFRESH_TIMING 692 #define ENABLE_TPBR2PBR_REFRESH_TIMING 1 693 694 #undef REFRESH_OVERHEAD_REDUCTION 695 #define REFRESH_OVERHEAD_REDUCTION 1 696 697 #undef AC_TIMING_DERATE_ENABLE 698 #define AC_TIMING_DERATE_ENABLE 1 699 700 #undef XRTWTW_NEW_CROSS_RK_MODE 701 #define XRTWTW_NEW_CROSS_RK_MODE 1 702 #undef XRTRTR_NEW_CROSS_RK_MODE 703 #define XRTRTR_NEW_CROSS_RK_MODE 1 704 705 #undef ENABLE_DVFS_BYPASS_MR13_FSP 706 #define ENABLE_DVFS_BYPASS_MR13_FSP 0 707 708 #undef HW_GATING 709 #undef DUMMY_READ_FOR_TRACKING 710 #undef ZQCS_ENABLE_LP4 711 //#define ZQCS_ENABLE_LP4 712 713 #undef TEMP_SENSOR_ENABLE 714 #define TEMP_SENSOR_ENABLE 715 #undef IMPEDANCE_TRACKING_ENABLE 716 //#define IMPEDANCE_TRACKING_ENABLE 717 #undef IMPEDANCE_HW_CALIBRATION 718 #define IMPEDANCE_HW_CALIBRATION 0 719 #undef ENABLE_SW_RUN_TIME_ZQ_WA 720 721 //#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY 722 723 #undef APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 724 #define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 725 726 #undef DFS_NOQUEUE_FLUSH_ENABLE 727 #define DFS_NOQUEUE_FLUSH_ENABLE 0 728 729 730 #undef TX_PICG_NEW_MODE 731 #undef RX_PICG_NEW_MODE 732 #if APPLY_LOWPOWER_GOLDEN_SETTINGS 733 #define TX_PICG_NEW_MODE 1 734 #define RX_PICG_NEW_MODE 1 735 #else 736 #define TX_PICG_NEW_MODE 0 737 #define RX_PICG_NEW_MODE 0 738 #endif 739 740 741 #if 0 742 #undef XRTW2W_PERFORM_ENHANCE_TX 743 #undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY 744 #ifdef XRTR2W_PERFORM_ENHANCE_RODTEN 745 #undef XRTR2W_PERFORM_ENHANCE_RODTEN 746 #endif 747 #endif 748 #endif 749 750 //======================== RSHMOO Definition ===================================== 751 #define RUNTIME_SHMOO_RELEATED_FUNCTION CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 752 #define RUNTIME_SHMOO_RG_BACKUP_NUM (100) 753 #define RUNTIME_SHMOO_TX 0 754 #define RUNTIME_SHMOO_RX 0 755 756 #if RUNTIME_SHMOO_RELEATED_FUNCTION 757 #undef TX_OE_EXTEND 758 #define TX_OE_EXTEND 1 759 #undef TX_DQ_OE_SHIFT_LP4 760 #define TX_DQ_OE_SHIFT_LP4 4 761 #undef TX_OE_CALIBATION 762 #define TX_OE_CALIBATION (!TX_OE_EXTEND) 763 #undef ENABLE_RX_TRACKING_LP4 764 #define ENABLE_RX_TRACKING_LP4 0 765 #undef ENABLE_TX_TRACKING 766 #undef ENABLE_SW_TX_TRACKING 767 #define ENABLE_TX_TRACKING 0 768 #define ENABLE_SW_TX_TRACKING 0 769 770 771 //#define SUPPORT_CLK_TERM 772 773 #define RUNTIME_SHMOO_FAST_K 1 774 775 #define RUNTIME_SHMOO_TEST_CHANNEL 0 776 #define RUNTIME_SHMOO_TEST_RANK 0 777 #define RUNTIME_SHMOO_TEST_BYTE 0 778 779 #define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 780 #define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 781 #define RUNTIME_SHMOO_TEST_PI_DELAY_STEP 1 782 783 #define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 784 #define RUNTIME_SHMOO_RX_TEST_MARGIN 2 785 786 #define RUNTIME_SHMOO_TEST_VREF_START 0 787 #define RUNTIME_SHMOO_TEST_VREF_END 81 788 #define RUNTIME_SHMOO_TEST_VREF_STEP 1 789 #endif 790 //============================================================================= 791 792 793 typedef enum 794 { 795 CLK_MUX_208M = 0, 796 CLK_MUX_104M, 797 CLK_MUX_52M, 798 } CLK_MUX_T; 799 800 typedef enum 801 { 802 BEF_DFS_MODE = 0, 803 AFT_DFS_MODE, 804 CHG_CLK_MODE, 805 } DFS_DBG_T; 806 807 typedef enum 808 { 809 SHUFFLE_HW_MODE = 0, 810 SPM_DEBUG_MODE, 811 RG_DEBUG_MODE, 812 } DFS_IP_CLOCK_T; 813 814 typedef enum 815 { 816 DutyScan_Calibration_K_CLK= 0, 817 DutyScan_Calibration_K_DQS, 818 DutyScan_Calibration_K_DQ, 819 DutyScan_Calibration_K_DQM, 820 DutyScan_Calibration_K_WCK 821 } DUTYSCAN_CALIBRATION_FLOW_K_T; 822 823 typedef enum 824 { 825 DQS_8PH_DEGREE_0 = 0, 826 DQS_8PH_DEGREE_180, 827 DQS_8PH_DEGREE_45, 828 DQS_8PH_DEGREE_MAX, 829 } DQS_8_PHASE_T; 830 831 typedef enum 832 { 833 CYCLE_05T = 2, 834 CYCLE_1T, 835 } DQSIEN_CYCLE_T; 836 837 typedef enum 838 { 839 DRVP = 0, 840 DRVN, 841 ODTP, 842 ODTN, 843 IMP_DRV_MAX 844 } DRAM_IMP_DRV_T; 845 846 typedef enum 847 { 848 IMP_LOW_FREQ = 0, 849 IMP_HIGH_FREQ, 850 IMP_NT_ODTN, 851 IMP_VREF_MAX 852 } DRAMC_IMP_T; 853 854 typedef enum 855 { 856 GET_MDL_USED = 0, 857 NORMAL_USED, 858 SLT_USED 859 } DRAM_INIT_USED_T; 860 861 typedef enum 862 { 863 PATTERN_RDDQC, 864 PATTERN_TEST_ENGINE, 865 } RX_PATTERN_OPTION_T; 866 867 typedef enum 868 { 869 DRAM_OK = 0, 870 DRAM_FAIL, 871 DRAM_FAST_K, 872 DRAM_NO_K, 873 } DRAM_STATUS_T; 874 875 typedef enum 876 { 877 VREF_RANGE_0= 0, 878 VREF_RANGE_1, 879 VREF_RANGE_MAX 880 }DRAM_VREF_RANGE_T; 881 #define VREF_VOLTAGE_TABLE_NUM_LP4 51 882 #define VREF_VOLTAGE_TABLE_NUM_LP5 128 883 884 typedef enum 885 { 886 CKE_FIXOFF = 0, 887 CKE_FIXON, 888 CKE_DYNAMIC 889 } CKE_FIX_OPTION; 890 891 typedef enum 892 { 893 TO_ONE_CHANNEL = 0, 894 TO_ALL_CHANNEL, 895 TO_ALL_RANK 896 } CHANNEL_RANK_SEL_T; 897 898 typedef enum { 899 CMDOE_DIS_TO_ONE_CHANNEL = 0, 900 CMDOE_DIS_TO_ALL_CHANNEL, 901 } CMDOE_DIS_CHANNEL; 902 903 typedef enum 904 { 905 LP5_DDR6400 = 0, 906 LP5_DDR6000, 907 LP5_DDR5500, 908 LP5_DDR4800, 909 LP5_DDR4266, 910 LP5_DDR3733, 911 LP5_DDR3200, 912 LP5_DDR2400, 913 LP5_DDR1600, 914 LP5_DDR1200, 915 LP5_DDR800, 916 917 LP4_DDR4266, 918 LP4_DDR3733, 919 LP4_DDR3200, 920 LP4_DDR2667, 921 LP4_DDR2400, 922 LP4_DDR2280, 923 LP4_DDR1866, 924 LP4_DDR1600, 925 LP4_DDR1200, 926 LP4_DDR800, 927 LP4_DDR400, 928 929 PLL_FREQ_SEL_MAX 930 } DRAM_PLL_FREQ_SEL_T; 931 932 typedef enum 933 { 934 MCK_TO_4UI_SHIFT = 2, 935 MCK_TO_8UI_SHIFT = 3, 936 MCK_TO_16UI_SHIFT = 4 937 } MCK_TO_UI_SHIFT_T; 938 939 typedef enum 940 { 941 AUTOK_CA, 942 AUTOK_CS, 943 AUTOK_DQS 944 } ATUOK_MODE_T; 945 946 typedef enum 947 { 948 AUTOK_RESPI_1 = 0, 949 AUTOK_RESPI_2 = 1, 950 AUTOK_RESPI_4 = 2, 951 AUTOK_RESPI_8 = 3 952 } AUTOK_PI_RESOLUTION; 953 954 typedef enum 955 { 956 DRAM_DFS_REG_SHU0 = 0, 957 DRAM_DFS_REG_SHU1, 958 DRAM_DFS_REG_MAX 959 } DRAM_DFS_REG_SHU_T; 960 961 typedef enum 962 { 963 SRAM_SHU0 = 0, 964 SRAM_SHU1, 965 SRAM_SHU2, 966 SRAM_SHU3, 967 SRAM_SHU4, 968 SRAM_SHU5, 969 SRAM_SHU6, 970 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION 971 SRAM_SHU7, 972 #endif 973 DRAM_DFS_SRAM_MAX 974 } DRAM_DFS_SRAM_SHU_T; 975 976 typedef enum 977 { 978 SHUFFLE_RG = 0, 979 NONSHUFFLE_RG, 980 BOTH_SHU_NONSHU_RG, 981 } RG_SHU_TYPE_T; 982 983 typedef enum 984 { 985 DIV16_MODE = 0, 986 DIV8_MODE, 987 DIV4_MODE, 988 UNKNOWN_MODE, 989 } DIV_MODE_T; 990 991 typedef enum 992 { 993 DUTY_DEFAULT = 0, 994 DUTY_NEED_K, 995 DUTY_LAST_K 996 } DUTY_CALIBRATION_T; 997 998 999 typedef enum 1000 { 1001 VREF_CALI_OFF = 0, 1002 VREF_CALI_ON, 1003 } VREF_CALIBRATION_ENABLE_T; 1004 1005 typedef enum 1006 { 1007 DDR800_CLOSE_LOOP = 0, 1008 OPEN_LOOP_MODE, 1009 SEMI_OPEN_LOOP_MODE, 1010 CLOSE_LOOP_MODE, 1011 } DDR800_MODE_T; 1012 1013 typedef enum 1014 { 1015 DRAM_CALIBRATION_SW_IMPEDANCE= 0, 1016 DRAM_CALIBRATION_DUTY_SCAN, 1017 DRAM_CALIBRATION_ZQ, 1018 DRAM_CALIBRATION_JITTER_METER, 1019 DRAM_CALIBRATION_CA_TRAIN , 1020 DRAM_CALIBRATION_WRITE_LEVEL, 1021 DRAM_CALIBRATION_GATING, 1022 DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC, 1023 DRAM_CALIBRATION_RX_RDDQC, 1024 DRAM_CALIBRATION_TX_PERBIT, 1025 DRAM_CALIBRATION_DATLAT, 1026 DRAM_CALIBRATION_RX_PERBIT, 1027 DRAM_CALIBRATION_TX_OE, 1028 DRAM_CALIBRATION_MAX 1029 } DRAM_CALIBRATION_STATUS_T; 1030 1031 typedef struct _DRAM_DFS_FREQUENCY_TABLE_T 1032 { 1033 DRAM_PLL_FREQ_SEL_T freq_sel; 1034 DIV_MODE_T divmode; 1035 DRAM_DFS_SRAM_SHU_T SRAMIdx; 1036 DUTY_CALIBRATION_T duty_calibration_mode; 1037 VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; 1038 DDR800_MODE_T ddr_loop_mode; 1039 } DRAM_DFS_FREQUENCY_TABLE_T; 1040 1041 #if 0 //[FOR_CHROMEOS]define in src\soc\mediatek\mt8195\include\soc\dramc_soc.h 1042 typedef enum 1043 { 1044 CHANNEL_A = 0, 1045 CHANNEL_B, 1046 #if (CHANNEL_NUM > 2) 1047 CHANNEL_C, 1048 CHANNEL_D, 1049 #endif 1050 CHANNEL_MAX 1051 } DRAM_CHANNEL_T; 1052 1053 typedef enum 1054 { 1055 RANK_0 = 0, 1056 RANK_1, 1057 RANK_MAX 1058 } DRAM_RANK_T; 1059 1060 1061 typedef enum 1062 { 1063 CBT_NORMAL_MODE = 0, 1064 CBT_BYTE_MODE1 1065 } DRAM_CBT_MODE_T, dram_cbt_mode; 1066 1067 #endif 1068 typedef enum 1069 { 1070 CHANNEL_SINGLE = 1, 1071 CHANNEL_DUAL, 1072 #if (CHANNEL_NUM > 2) 1073 CHANNEL_THIRD, 1074 CHANNEL_FOURTH 1075 #endif 1076 } DRAM_CHANNEL_NUMBER_T; 1077 1078 typedef enum 1079 { 1080 RANK_SINGLE = 1, 1081 RANK_DUAL 1082 } DRAM_RANK_NUMBER_T; 1083 1084 1085 typedef enum 1086 { 1087 TYPE_DDR1 = 1, 1088 TYPE_LPDDR2, 1089 TYPE_LPDDR3, 1090 TYPE_PCDDR3, 1091 TYPE_LPDDR4, 1092 TYPE_LPDDR4X, 1093 TYPE_LPDDR4P, 1094 TYPE_LPDDR5 1095 } DRAM_DRAM_TYPE_T; 1096 1097 typedef enum 1098 { 1099 PINMUX_EMCP = 0, 1100 PINMUX_DSC, 1101 PINMUX_MCP, 1102 PINMUX_DSC_REV, 1103 PINMUX_MAX 1104 } DRAM_PINMUX; 1105 1106 1107 typedef enum 1108 { 1109 FSP_0 = 0, 1110 FSP_1, 1111 FSP_2, 1112 FSP_MAX 1113 } DRAM_FAST_SWITH_POINT_T; 1114 1115 1116 typedef struct 1117 { 1118 u8 pat_v[8]; 1119 u8 pat_a[8]; 1120 u8 pat_dmv; 1121 u8 pat_dma; 1122 u8 pat_cs0; 1123 u8 pat_cs1; 1124 u8 ca_golden_sel; 1125 u8 invert_num; 1126 u8 pat_num; 1127 u8 ca_num; 1128 } new_cbt_pat_cfg_t; 1129 1130 typedef enum 1131 { 1132 TRAINING_MODE1 = 0, 1133 TRAINING_MODE2 1134 } lp5_training_mode_t; 1135 1136 typedef enum 1137 { 1138 CBT_PHASE_RISING = 0, 1139 CBT_PHASE_FALLING 1140 } lp5_cbt_phase_t; 1141 1142 1143 typedef enum 1144 { 1145 CBT_R0_R1_NORMAL = 0, 1146 CBT_R0_R1_BYTE, 1147 CBT_R0_NORMAL_R1_BYTE, 1148 CBT_R0_BYTE_R1_NORMAL 1149 } DRAM_CBT_MODE_EXTERN_T; 1150 1151 typedef enum 1152 { 1153 EYESCAN_TYPE_CBT = 0, 1154 EYESCAN_TYPE_RX, 1155 EYESCAN_TYPE_TX 1156 } DRAM_EYESCAN_TYPE_T; 1157 1158 typedef enum 1159 { 1160 ODT_OFF = 0, 1161 ODT_ON 1162 } DRAM_ODT_MODE_T; 1163 1164 typedef enum 1165 { 1166 DBI_OFF = 0, 1167 DBI_ON 1168 } DRAM_DBI_MODE_T; 1169 1170 typedef enum 1171 { 1172 DATA_WIDTH_16BIT = 16, 1173 DATA_WIDTH_32BIT = 32 1174 } DRAM_DATA_WIDTH_T; 1175 1176 typedef enum 1177 { 1178 TE_OP_WRITE_READ_CHECK = 0, 1179 TE_OP_READ_CHECK 1180 } DRAM_TE_OP_T; 1181 1182 typedef enum 1183 { 1184 TEST_ISI_PATTERN = 0, 1185 TEST_AUDIO_PATTERN = 1, 1186 TEST_XTALK_PATTERN = 2, 1187 TEST_WORST_SI_PATTERN, 1188 TEST_TA1_SIMPLE, 1189 TEST_TESTPAT4, 1190 TEST_TESTPAT4_3, 1191 TEST_MIX_PATTERN, 1192 TEST_DMA, 1193 TEST_SSOXTALK_PATTERN, 1194 } DRAM_TEST_PATTERN_T; 1195 1196 typedef enum 1197 { 1198 TE_NO_UI_SHIFT = 0, 1199 TE_UI_SHIFT 1200 } DRAM_TE_UI_SHIFT_T; 1201 1202 typedef enum 1203 { 1204 TX_DQ_DQS_MOVE_DQ_ONLY = 0, 1205 TX_DQ_DQS_MOVE_DQM_ONLY, 1206 TX_DQ_DQS_MOVE_DQ_DQM 1207 } DRAM_TX_PER_BIT_CALIBRATION_TYTE_T; 1208 1209 typedef enum 1210 { 1211 TX_DQM_WINDOW_SPEC_IN = 0xfe, 1212 TX_DQM_WINDOW_SPEC_OUT = 0xff 1213 } DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T; 1214 1215 1216 typedef enum 1217 { 1218 CKE_RANK_INDEPENDENT = 0, 1219 CKE_RANK_DEPENDENT 1220 } CKE_CTRL_MODE_T; 1221 1222 typedef enum 1223 { 1224 TA2_RKSEL_XRT = 3, 1225 TA2_RKSEL_HW = 4, 1226 } TA2_RKSEL_TYPE_T; 1227 1228 typedef enum 1229 { 1230 TA2_PAT_SWITCH_OFF = 0, 1231 TA2_PAT_SWITCH_ON, 1232 } TA2_PAT_SWITCH_TYPE_T; 1233 1234 typedef enum 1235 { 1236 PHYPLL_MODE = 0, 1237 CLRPLL_MODE, 1238 } PLL_MODE_T; 1239 1240 typedef enum 1241 { 1242 RUNTIME_SWCMD_CAS_FS = 0, 1243 RUNTIME_SWCMD_CAS_OFF, 1244 RUNTIME_SWCMD_WCK2DQI_START, 1245 RUNTIME_SWCMD_WCK2DQO_START, 1246 RUNTIME_SWCMD_MRW, 1247 RUNTIME_SWCMD_ZQCAL_START, 1248 RUNTIME_SWCMD_ZQCAL_LATCH 1249 } RUNTIME_SWCMD_SEL_T; 1250 1251 typedef enum 1252 { 1253 PI_BASED, 1254 DLY_BASED 1255 } WLEV_DELAY_BASED_T; 1256 1257 enum lpddr5_rpre_mode { 1258 LPDDR5_RPRE_4S_0T = 0, 1259 LPDDR5_RPRE_2S_2T, 1260 LPDDR5_RPRE_0S_4T, 1261 LPDDR5_RPRE_XS_4T, 1262 }; 1263 1264 enum rxdqs_autok_burst_len { 1265 RXDQS_BURST_LEN_8 = 0, 1266 RXDQS_BURST_LEN_16, 1267 RXDQS_BURST_LEN_32, 1268 }; 1269 1270 typedef enum 1271 { 1272 EYESCAN_FLAG_DISABLE= 0, 1273 EYESCAN_FLAG_ENABLE, 1274 EYESCAN_FLAG_ENABLE_BUT_NORMAL_K, 1275 } EYESCAN_FLAG_TYPE_T; 1276 1277 #ifdef FOR_HQA_REPORT_USED 1278 typedef enum 1279 { 1280 HQA_REPORT_FORMAT0 = 0, 1281 HQA_REPORT_FORMAT0_1, 1282 HQA_REPORT_FORMAT0_2, 1283 HQA_REPORT_FORMAT1, 1284 HQA_REPORT_FORMAT2, 1285 HQA_REPORT_FORMAT2_1, 1286 HQA_REPORT_FORMAT3, 1287 HQA_REPORT_FORMAT4, 1288 HQA_REPORT_FORMAT5, 1289 HQA_REPORT_FORMAT6 1290 } HQA_REPORT_FORMAT_T; 1291 #endif 1292 1293 #ifdef DEVIATION 1294 typedef enum 1295 { 1296 Deviation_CA = 0, 1297 Deviation_RX, 1298 Deviation_TX, 1299 Deviation_MAX 1300 } DRAM_DEVIATION_TYPE_T; 1301 #endif 1302 1303 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION 1304 #if RUNTIME_SHMOO_RELEATED_FUNCTION 1305 typedef struct _RUNTIME_SHMOO_SAVE_PARAMETER_T 1306 { 1307 U8 flag; 1308 U16 TX_PI_delay; 1309 U16 TX_Original_PI_delay; 1310 U16 TX_DQM_PI_delay; 1311 U16 TX_Original_DQM_PI_delay; 1312 S16 RX_delay[8]; 1313 S16 RX_Original_delay; 1314 U8 TX_Vref_Range; 1315 U8 TX_Vref_Value; 1316 U8 TX_Channel; 1317 U8 TX_Rank; 1318 U8 TX_Byte; 1319 U8 Scan_Direction; 1320 } RUNTIME_SHMOO_SAVE_PARAMETER_T; 1321 #endif 1322 1323 typedef struct _SAVE_TIME_FOR_CALIBRATION_T 1324 { 1325 //U8 femmc_Ready; 1326 1327 DRAM_RANK_NUMBER_T support_rank_num; 1328 1329 // Calibration or not 1330 //U8 Bypass_TXWINDOW; 1331 //U8 Bypass_RXWINDOW; 1332 //U8 Bypass_RDDQC; 1333 1334 // delay cell time 1335 U16 u2DelayCellTimex100; 1336 1337 // CLK & DQS duty 1338 S8 s1ClockDuty_clk_delay_cell[CHANNEL_NUM][RANK_MAX]; 1339 S8 s1DQSDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER]; 1340 S8 s1WCKDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER]; 1341 #if APPLY_DQDQM_DUTY_CALIBRATION 1342 S8 s1DQDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER]; 1343 S8 s1DQMDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER]; 1344 #endif 1345 // CBT 1346 U8 u1CBTVref_Save[CHANNEL_NUM][RANK_MAX]; 1347 S8 s1CBTCmdDelay_Save[CHANNEL_NUM][RANK_MAX]; 1348 U8 u1CBTCsDelay_Save[CHANNEL_NUM][RANK_MAX]; 1349 #if CA_PER_BIT_DELAY_CELL 1350 U8 u1CBTCA_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQS_BIT_NUMBER]; 1351 #endif 1352 1353 // Write leveling 1354 U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1355 1356 // Gating 1357 U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1358 U8 u1Gating_UI_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1359 U8 u1Gating_PI_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1360 U8 u1Gating_pass_count_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1361 1362 // TX perbit 1363 U8 u1TxWindowPerbitVref_Save[CHANNEL_NUM][RANK_MAX]; 1364 U16 u1TxCenter_min_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1365 U16 u1TxCenter_max_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1366 U16 u1Txwin_center_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; 1367 //U16 u1Txfirst_pass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1368 //U16 u1Txlast_pass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1369 //U8 u1TX_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1370 1371 // Datlat 1372 U8 u1RxDatlat_Save[CHANNEL_NUM][RANK_MAX]; 1373 1374 // RX perbit 1375 U8 u1RxWinPerbitVref_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1376 U16 u1RxWinPerbit_DQS[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1377 U16 u1RxWinPerbit_DQM[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1378 U16 u1RxWinPerbit_DQ[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; 1379 1380 //TX OE 1381 U8 u1TX_OE_DQ_MCK[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1382 U8 u1TX_OE_DQ_UI[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; 1383 1384 1385 #if RUNTIME_SHMOO_RELEATED_FUNCTION 1386 S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; 1387 U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; 1388 U8 u1SwImpedanceResule[2][4]; 1389 U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM]; 1390 1391 RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para; 1392 #endif 1393 }SAVE_TIME_FOR_CALIBRATION_T; 1394 #endif 1395 1396 #if MRW_CHECK_ONLY 1397 #define MR_NUM 64 1398 extern U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM]; 1399 #endif 1400 1401 //////////////////////////// 1402 typedef struct _DRAMC_CTX_T 1403 { 1404 DRAM_CHANNEL_NUMBER_T support_channel_num; 1405 DRAM_CHANNEL_T channel; 1406 DRAM_RANK_NUMBER_T support_rank_num; 1407 DRAM_RANK_T rank; 1408 DRAM_PLL_FREQ_SEL_T freq_sel; 1409 DRAM_DRAM_TYPE_T dram_type; 1410 DRAM_FAST_SWITH_POINT_T dram_fsp; 1411 DRAM_FAST_SWITH_POINT_T boot_fsp; 1412 DRAM_ODT_MODE_T odt_onoff; 1413 DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; 1414 DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; 1415 DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; 1416 DRAM_DATA_WIDTH_T data_width; 1417 U32 test2_1; 1418 U32 test2_2; 1419 DRAM_TEST_PATTERN_T test_pattern; 1420 U16 frequency; 1421 U16 freqGroup; 1422 U16 vendor_id; 1423 U16 revision_id; 1424 U16 density; 1425 U64 ranksize[RANK_MAX]; 1426 U16 u2DelayCellTimex100; 1427 //U8 enable_cbt_scan_vref; 1428 //U8 enable_rx_scan_vref; 1429 //U8 enable_tx_scan_vref; 1430 1431 #if PRINT_CALIBRATION_SUMMARY 1432 U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX]; 1433 U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; 1434 U32 SWImpCalResult; 1435 U32 SWImpCalExecute; 1436 #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 1437 U32 FastKResultFlag[2][RANK_MAX]; 1438 U32 FastKExecuteFlag[2][RANK_MAX]; 1439 #endif 1440 #endif 1441 1442 bool isWLevInitShift[CHANNEL_NUM]; 1443 1444 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION 1445 U8 femmc_Ready; 1446 // Calibration or not 1447 U8 Bypass_TXWINDOW; 1448 U8 Bypass_RXWINDOW; 1449 U8 Bypass_RDDQC; 1450 SAVE_TIME_FOR_CALIBRATION_T *pSavetimeData; 1451 #endif 1452 DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable; 1453 DRAM_DFS_REG_SHU_T ShuRGAccessIdx; 1454 lp5_training_mode_t lp5_training_mode; 1455 lp5_cbt_phase_t lp5_cbt_phase; 1456 u8 new_cbt_mode; 1457 U8 u1PLLMode; 1458 DRAM_DBI_MODE_T curDBIState; 1459 DRAM_FAST_SWITH_POINT_T support_fsp_num; 1460 DRAM_PINMUX DRAMPinmux; 1461 U8 u110GBEn[RANK_MAX]; 1462 bool isMaxFreq4266; 1463 } DRAMC_CTX_T; 1464 1465 typedef struct _DRAM_DVFS_TABLE_T 1466 { 1467 DRAM_PLL_FREQ_SEL_T freq_sel; 1468 DRAM_DFS_SRAM_SHU_T SRAMIdx; 1469 U32 u4Vcore; 1470 } DRAM_DVFS_TABLE_T; 1471 1472 typedef struct _PASS_WIN_DATA_T 1473 { 1474 S16 first_pass; 1475 S16 last_pass; 1476 S16 win_center; 1477 U16 win_size; 1478 U16 best_dqdly; 1479 } PASS_WIN_DATA_T; 1480 1481 typedef struct _FINAL_WIN_DATA_T { 1482 unsigned char final_vref; 1483 signed int final_ca_clk; 1484 unsigned char final_range; 1485 } FINAL_WIN_DATA_T; 1486 1487 typedef struct _REG_TRANSFER 1488 { 1489 U32 u4Addr; 1490 U32 u4Fld; 1491 } REG_TRANSFER_T; 1492 1493 typedef struct _DRAM_INFO_BY_MRR_T 1494 { 1495 U16 u2MR5VendorID; 1496 U16 u2MR6RevisionID; 1497 U64 u8MR8Density[RANK_MAX]; 1498 U32 u4RankNum; 1499 U8 u1DieNum[RANK_MAX]; 1500 } DRAM_INFO_BY_MRR_T; 1501 1502 typedef struct _JMETER_DELAYCELL_T 1503 { 1504 U32 Vcore; 1505 U16 delay_cell_ps; 1506 } JMETER_DELAYCELL_T; 1507 1508 #if PIN_CHECK_TOOL 1509 typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T 1510 { 1511 U16 TOTAL_ERR; 1512 U16 IMP_ERR_FLAG; 1513 U8 WL_ERR_FLAG; 1514 U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX]; 1515 U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4]; 1516 U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER]; 1517 U8 DRAM_PIN_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER]; 1518 U8 DQ_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER]; 1519 U8 DQ_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER]; 1520 U16 DQ_RX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 1521 U8 DQ_TX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 1522 } DEBUG_PIN_INF_FOR_FLASHTOOL_T; 1523 #endif 1524 1525 typedef struct _VCORE_DELAYCELL_T 1526 { 1527 U32 u2Vcore; 1528 U16 u2DelayCell; 1529 } VCORE_DELAYCELL_T; 1530 1531 typedef struct _JM_DLY_T 1532 { 1533 U16 u1JmDelay; 1534 U8 u1TransLevel; 1535 } JM_DLY_T; 1536 1537 1538 typedef struct _JMETER_T 1539 { 1540 JM_DLY_T JmtrInfo[3]; 1541 U8 u1TransCnt; 1542 } JMETER_T; 1543 1544 typedef enum 1545 { 1546 DMA_PREPARE_DATA_ONLY, 1547 DMA_CHECK_DATA_ACCESS_ONLY_AND_NO_WAIT, 1548 DMA_CHECK_COMAPRE_RESULT_ONLY, 1549 DMA_CHECK_DATA_ACCESS_AND_COMPARE, 1550 } DRAM_DMA_CHECK_RESULT_T; 1551 1552 #if defined(DDR_INIT_TIME_PROFILING) || ENABLE_APB_MASK_WRITE 1553 typedef struct _PROFILING_TIME_T 1554 { 1555 U32 u4TickHigh; 1556 U32 u4TickLow; 1557 } PROFILING_TIME_T; 1558 #endif 1559 1560 //For new register access 1561 #define SHIFT_TO_CHB_ADDR ((U32)CHANNEL_B << POS_BANK_NUM) 1562 #if (CHANNEL_NUM > 2) 1563 #define SHIFT_TO_CHC_ADDR ((U32)CHANNEL_C << POS_BANK_NUM) 1564 #define SHIFT_TO_CHD_ADDR ((U32)CHANNEL_D << POS_BANK_NUM) 1565 #endif 1566 #define DRAMC_REG_ADDR(offset) ((p->channel << POS_BANK_NUM) + (offset)) 1567 #define SYS_REG_ADDR(offset) (offset) 1568 1569 // Different from Pi_calibration.c due to Base address 1570 //#define mcSET_DRAMC_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (p->channel << POS_BANK_NUM) | (offset)) 1571 #define mcSET_SYS_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (offset)) 1572 #define mcSET_DRAMC_NAO_REG_ADDR(offset) (DRAMC_NAO_BASE_ADDRESS | (offset)) 1573 #define mcSET_DRAMC_AO_REG_ADDR(offset) (DRAMC_AO_BASE_ADDRESS | (offset)) 1574 //#define mcSET_DRAMC_AO_REG_ADDR_CHC(offset) ((DRAMC_AO_BASE_ADDRESS + ((U32)CHANNEL_C << POS_BANK_NUM)) | (offset)) 1575 #define mcSET_DDRPHY_REG_ADDR(offset) (DDRPHY_BASE_ADDR | (offset)) 1576 #define mcSET_DDRPHY_REG_ADDR_CHA(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_A << POS_BANK_NUM)) | (offset)) 1577 #define mcSET_DDRPHY_REG_ADDR_CHB(offset) ((DDRPHY_BASE_ADDR + SHIFT_TO_CHB_ADDR) | (offset)) 1578 //#define mcSET_DDRPHY_REG_ADDR_CHC(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_C << POS_BANK_NUM)) | (offset)) 1579 //#define mcSET_DDRPHY_REG_ADDR_CHD(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_D << POS_BANK_NUM)) | (offset)) 1580 1581 //-------------------------------------------------------------------------- 1582 // Dram Mode Registers Operation 1583 //-------------------------------------------------------------------------- 1584 #define MRWriteFldMulti(p, mr_idx, list, UpdateMode) \ 1585 { \ 1586 UINT16 upk = 1; \ 1587 U8 msk = (U8)(list); \ 1588 { \ 1589 upk = 0; \ 1590 DramcMRWriteFldMsk(p, mr_idx, (U8)(list), msk, UpdateMode); \ 1591 } \ 1592 } 1593 1594 #define JUST_TO_GLOBAL_VALUE (0) 1595 #define TO_MR (1) 1596 1597 1598 #define MR30_DCAU (Fld(4, 4)) 1599 #define MR30_DCAL (Fld(4, 0)) 1600 1601 1602 #define MR26_DCMU1 (Fld(1, 5)) 1603 #define MR26_DCMU0 (Fld(1, 4)) 1604 #define MR26_DCML1 (Fld(1, 3)) 1605 #define MR26_DCML0 (Fld(1, 2)) 1606 #define MR26_DCM_FLIP (Fld(1, 1)) 1607 #define MR26_DCM_START_STOP (Fld(1, 0)) 1608 1609 1610 #define MR13_FSP_OP (Fld(1, 7)) 1611 #define MR13_FSP_WR (Fld(1, 6)) 1612 #define MR13_DMD (Fld(1, 5)) 1613 #define MR13_PRO (Fld(1, 4)) 1614 #define MR13_VRCG (Fld(1, 3)) 1615 #define MR13_CBT (Fld(1, 0)) 1616 1617 #define MR16_FSP_WR_SHIFT (0) 1618 #define MR16_FSP_OP_SHIFT (2) 1619 #define MR16_FSP_CBT (4) 1620 #define MR16_VRCG (6) 1621 #define MR16_CBT_PHASE (7) 1622 1623 /***********************************************************************/ 1624 /* External declarations */ 1625 /***********************************************************************/ 1626 EXTERN DRAMC_CTX_T *psCurrDramCtx; 1627 #if QT_GUI_Tool 1628 EXTERN FILE *fp_A60868; 1629 EXTERN FILE *fp_A60868_RGDump; 1630 #endif 1631 /***********************************************************************/ 1632 /* Public Functions */ 1633 /***********************************************************************/ 1634 // basic function 1635 EXTERN U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type); 1636 EXTERN int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used); 1637 EXTERN void Dramc_DDR_Reserved_Mode_setting(void); 1638 EXTERN void Dramc_DDR_Reserved_Mode_AfterSR(void); 1639 EXTERN void Before_Init_DRAM_While_Reserve_Mode_fail(DRAM_DRAM_TYPE_T dram_type); 1640 1641 void vSetVcoreByFreq(DRAMC_CTX_T *p); 1642 U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value); 1643 U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p); 1644 void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level); 1645 void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p); 1646 void DFSInitForCalibration(DRAMC_CTX_T *p); 1647 void mdl_setting(DRAMC_CTX_T *p); 1648 void MPLLInit(void); 1649 void DramcCKEDebounce(DRAMC_CTX_T *p); 1650 void DramcModifiedRefreshMode(DRAMC_CTX_T *p); 1651 void XRTRTR_SHU_Setting(DRAMC_CTX_T * p); 1652 void TXPICGSetting(DRAMC_CTX_T * p); 1653 void XRTWTW_SHU_Setting(DRAMC_CTX_T * p); 1654 DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p); 1655 void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff); 1656 void Get_RX_DelayCell(DRAMC_CTX_T *p); 1657 void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p); 1658 void EnableDFSNoQueueFlush(DRAMC_CTX_T *p); 1659 void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn); 1660 void Enable_TxWDQS(DRAMC_CTX_T *p); 1661 void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p); 1662 void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq); 1663 void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p); 1664 void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN); 1665 void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p); 1666 U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value); 1667 U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate); 1668 1669 unsigned int dramc_set_vcore_voltage(unsigned int vcore); 1670 unsigned int dramc_get_vcore_voltage(void); 1671 unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram); 1672 unsigned int dramc_get_vdram_voltage(unsigned int ddr_type); 1673 unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq); 1674 unsigned int dramc_get_vddq_voltage(unsigned int ddr_type); 1675 unsigned int dramc_set_vmddr_voltage(unsigned int vmddr); 1676 unsigned int dramc_get_vmddr_voltage(void); 1677 unsigned int dramc_set_vio18_voltage(unsigned int vio18); 1678 unsigned int dramc_get_vio18_voltage(void); 1679 1680 void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p); 1681 1682 void DramcNewDutyCalibration(DRAMC_CTX_T *p); 1683 unsigned int mt_get_dram_type_from_hw_trap(void); 1684 U8 Get_MDL_Used_Flag(void); 1685 void Set_MDL_Used_Flag(U8 value); 1686 void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p); 1687 U8 u1GetMR4RefreshRate(DRAMC_CTX_T *p, DRAM_CHANNEL_T channel); 1688 void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq); 1689 void TX_Path_Algorithm(DRAMC_CTX_T *p); 1690 DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq); 1691 void DVFS_config(DRAMC_CTX_T *p); 1692 DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p); 1693 int divRoundClosest(const int n, const int d); 1694 void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level); 1695 void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level); 1696 void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p); 1697 void HwSaveForSR(DRAMC_CTX_T *p); 1698 void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p); 1699 void EnableCmdPicgEffImprove(DRAMC_CTX_T *p); 1700 void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter, U8* pu1UILarge_DQ, U8* pu1UISmall_DQ, U8* pu1PI, U8* pu1UILarge_DQOE, U8* pu1UISmall_DQOE); 1701 void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM); 1702 DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p); 1703 void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p); 1704 int doe_get_config(const char* feature); 1705 void vDramcACTimingOptimize(DRAMC_CTX_T *p); 1706 1707 const char* HQA_LOG_Parsing_Freq(void); 1708 void HQA_LOG_Print_Freq_String(DRAMC_CTX_T *p); 1709 void DramcDumpDebugInfo(DRAMC_CTX_T *p); 1710 void DramcModeReg_Check(DRAMC_CTX_T *p); 1711 1712 1713 #endif // _PI_API_H 1714