1 /* 2 * Copyright (c) 2014-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox.h 24 //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across MHW components. 25 //! 26 #ifndef _MHW_VDBOX_H_ 27 #define _MHW_VDBOX_H_ 28 29 #include "codec_def_encode_avc.h" 30 #include "codec_def_encode_jpeg.h" 31 #include "codec_def_encode_mpeg2.h" 32 #include "codec_def_encode_vp9.h" 33 #include "codec_def_decode_vp9.h" 34 #include "codec_def_decode_vc1.h" 35 #include "codec_def_decode_avc.h" 36 #include "codec_def_decode_hevc.h" 37 #include "mos_os.h" 38 #include "mhw_utilities.h" 39 40 #if (_DEBUG || _RELEASE_INTERNAL) 41 #define MHW_VDBOX_IS_VDBOX_SPECIFIED(keyval, vdid, shift, mask, useVD) \ 42 do \ 43 { \ 44 int32_t TmpVal = keyval; \ 45 while (TmpVal != 0) \ 46 { \ 47 if (((TmpVal) & (mask)) == (vdid)) \ 48 { \ 49 useVD = true; \ 50 break; \ 51 } \ 52 TmpVal >>= (shift); \ 53 }; \ 54 } while (0) 55 #endif 56 57 #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_SMALL 64 58 #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_LARGE 128 59 60 #define MHW_VDBOX_MFX_RAW_UV_PLANE_ALIGNMENT_GEN9 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x 61 #define MHW_VDBOX_MFX_UV_PLANE_ALIGNMENT_LEGACY 16 62 #define MHW_VDBOX_MFX_RECON_UV_PLANE_ALIGNMENT 16 63 #define MHW_VDBOX_HCP_RAW_UV_PLANE_ALIGNMENT 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x 64 #define MHW_VDBOX_HCP_RECON_UV_PLANE_ALIGNMENT 8 65 66 #define MHW_VDBOX_PAK_BITSTREAM_OVERFLOW_SIZE 400 67 #define MHW_VDBOX_PAK_SLICE_HEADER_OVERFLOW_SIZE 50 68 #define MHW_VDBOX_VDENC_DYNAMIC_SLICE_WA_COUNT 1500 69 70 // Rowstore Cache values 71 #define MHW_VDBOX_PICWIDTH_1K 1024 72 #define MHW_VDBOX_PICWIDTH_2K 2048 73 #define MHW_VDBOX_PICWIDTH_3K 3072 74 #define MHW_VDBOX_PICWIDTH_4K 4096 75 #define MHW_VDBOX_PICWIDTH_8K 8192 76 #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 77 #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 384 78 #define INTRAROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 512 79 #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 384 80 #define DEBLOCKINGROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 384 81 #define BSDMPCROWSTORE_BASEADDRESS 0 82 #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 83 #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 84 #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_GREATER_THAN_3K 256 85 #define MPRROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 86 #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 87 #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 88 #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 256 89 #define HEVCDATROWSTORE_BASEADDRESS 0 90 #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 64 91 #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_4K 128 92 #define HEVCSAOROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 320 93 #define VP9HVDROWSTORE_BASEADDRESS 0 94 #define VP9DFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 32 95 #define MHW_CACHELINE_SIZE 64 96 #define BYTES_PER_DWORD 4 97 #define NUM_PAK_DWS_PER_LCU 5 98 #define NUM_DWS_PER_CU 8 99 100 #define VP9DFROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 384 101 #define VP9DATROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 64 102 103 typedef enum _MHW_VDBOX_ADDRESS_SHIFT 104 { 105 MHW_VDBOX_SURFACE_STATE_SHIFT = 0, 106 MHW_VDBOX_MFX_GENERAL_STATE_SHIFT = 6, 107 MHW_VDBOX_HCP_GENERAL_STATE_SHIFT = 6, 108 MHW_VDBOX_HUC_GENERAL_STATE_SHIFT = 6, 109 MHW_VDBOX_MFX_UPPER_BOUND_STATE_SHIFT = 12, 110 MHW_VDBOX_STATE_BASE_ADDRESS_SHIFT = 12, 111 MHW_VDBOX_HCP_UPPER_BOUND_STATE_SHIFT = 12, 112 MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT = 12, 113 MHW_VDBOX_HUC_IMEM_STATE_SHIFT = 15, 114 MHW_VDBOX_HCP_DECODED_BUFFER_SHIFT = 12 115 } MHW_VDBOX_ADDRESS_SHIFT; 116 117 typedef enum _MHW_VDBOX_NODE_IND 118 { 119 MHW_VDBOX_NODE_1 = 0x0, 120 MHW_VDBOX_NODE_2 = 0x1, 121 MHW_VDBOX_NODE_MAX 122 } MHW_VDBOX_NODE_IND; 123 124 typedef struct _MHW_VDBOX_AVC_QM_PARAMS 125 { 126 uint8_t List4x4[6][16]; 127 uint8_t List8x8[2][64]; 128 } MHW_VDBOX_AVC_QM_PARAMS, *PMHW_VDBOX_AVC_QM_PARAMS; 129 130 typedef struct _MHW_VDBOX_HEVC_QM_PARAMS 131 { 132 uint8_t List4x4[6][16]; 133 uint8_t List8x8[6][64]; 134 uint8_t List16x16[6][64]; 135 uint8_t List32x32[2][64]; 136 uint8_t ListDC16x16[6]; 137 uint8_t ListDC32x32[2]; 138 } MHW_VDBOX_HEVC_QM_PARAMS, *PMHW_VDBOX_HEVC_QM_PARAMS; 139 140 typedef enum _HCP_SURFACE_FORMAT 141 { 142 HCP_SURFACE_FORMAT_YUY2 = 0x0, 143 HCP_SURFACE_FORMAT_RGBX8888 = 0x1, 144 HCP_SURFACE_FORMAT_AYUV4444 = 0x2, 145 HCP_SURFACE_FORMAT_P010_VARIANT = 0x3, 146 HCP_SURFACE_FORMAT_PLANAR_420_8 = 0x4, 147 HCP_SURFACE_FORMAT_UYVY = 0x5, 148 HCP_SURFACE_FORMAT_YVYU = 0x6, 149 HCP_SURFACE_FORMAT_VYUY = 0x7, 150 HCP_SURFACE_FORMAT_Y210 = 0x8, 151 HCP_SURFACE_FORMAT_Y216 = 0x8, 152 HCP_SURFACE_FORMAT_RGBA1010102 = 0x9, 153 HCP_SURFACE_FORMAT_Y410 = 0xA, 154 HCP_SURFACE_FORMAT_NV21 = 0xB, 155 HCP_SURFACE_FORMAT_Y416 = 0xC, 156 HCP_SURFACE_FORMAT_P010 = 0xD, 157 HCP_SURFACE_FORMAT_P016 = 0xE, 158 HCP_SURFACE_FORMAT_Y8 = 0xF, 159 HCP_SURFACE_FORMAT_Y16 = 0x10, 160 HCP_SURFACE_FORMAT_Y216_VARIANT = 0x11, 161 HCP_SURFACE_FORMAT_Y416_VARIANT = 0x12, 162 HCP_SURFACE_FORMAT_YUYV_VARIANT = 0x13, 163 HCP_SURFACE_FORMAT_AYUV4444_VARIANT = 0x14, 164 HCP_SURFACE_FORMAT_RESERVED = 0x15, 165 } HCP_SURFACE_FORMAT; 166 167 typedef enum _PIPE_WORK_MODE 168 { 169 MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY = 0, 170 MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_FE = 1, 171 MHW_VDBOX_HCP_PIPE_WORK_MODE_CODEC_BE = 2, 172 MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_REAL_TILE = 3, 173 }MHW_VDBOX_HCP_PIPE_WORK_MODE; 174 175 typedef enum _MULTI_ENGINE_MODE 176 { 177 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY = 0, 178 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_LEFT = 1, 179 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_RIGHT = 2, 180 MHW_VDBOX_HCP_MULTI_ENGINE_MODE_MIDDLE = 3, 181 }MHW_VDBOX_HCP_MULTI_ENGINE_MODE; 182 183 typedef enum 184 { 185 MHW_VDBOX_HCP_RT_FIRST_PHASE = 0, //!< First phase 186 MHW_VDBOX_HCP_RT_MIDDLE_PHASE = 1, //!< Middle phase 187 MHW_VDBOX_HCP_RT_LAST_PHASE = 2 //!< Last phase 188 } MHW_HCP_RT_PHASE_INDICATOR; 189 190 typedef enum _VDENC_PIPE_NUM_OF_PIPE 191 { 192 VDENC_PIPE_SINGLE_PIPE = 0, 193 VDENC_PIPE_TWO_PIPE = 1, 194 VDENC_PIPE_INVALID = 2, 195 VDENC_PIPE_FOUR_PIPE = 3, 196 }VDENC_PIPE_NUM_OF_PIPE; 197 198 typedef enum 199 { 200 HCP_CHROMA_FORMAT_MONOCHROME = 0, 201 HCP_CHROMA_FORMAT_YUV420 = 1, 202 HCP_CHROMA_FORMAT_YUV422 = 2, 203 HCP_CHROMA_FORMAT_YUV444 = 3 204 } HCP_CHROMA_FORMAT_IDC; 205 206 // Media memory compression trigger 207 typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_EN 208 { 209 MHW_MEDIA_MEMCOMP_DISABLED = 0x0, 210 MHW_MEDIA_MEMCOMP_ENABLED = 0x1 211 } MHW_MEDIA_MEMORY_COMPRESSION_EN; 212 213 // Media memory compression mode 214 typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_MODE 215 { 216 MHW_MEDIA_MEMCOMP_MODE_HORIZONTAL = 0x0, 217 MHW_MEDIA_MEMCOMP_MODE_VERTICAL = 0x1, 218 } MHW_MEDIA_MEMORY_COMPRESSION_MODE; 219 220 //! 221 //! \enum ROWSTORE_SCRATCH_BUFFER_CACHE 222 //! \brief Rowstore scratch buffer cache select 223 //! 224 enum ROWSTORE_SCRATCH_BUFFER_CACHE 225 { 226 BUFFER_TO_LLC = 0x0, 227 BUFFER_TO_INTERNALMEDIASTORAGE = 0x1 228 }; 229 230 struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS 231 { 232 uint32_t Mode = 0; 233 bool bStreamOutEnabled = false; 234 bool bStreamOutEnabledExtEnabled = false; 235 bool bShortFormatInUse = false; 236 bool bVC1OddFrameHeight = false; 237 bool pakFrmLvlStrmoutEnable = false; 238 bool pakPiplnStrmoutEnabled = false; 239 240 bool bDeblockerStreamOutEnable = false; 241 bool bPostDeblockOutEnable = false; 242 bool bPreDeblockOutEnable = false; 243 bool bDynamicSliceEnable = false; 244 bool bSaoFirstPass = false; 245 bool bRdoqEnable = false; 246 bool bDynamicScalingEnabled = false; 247 248 // VDEnc specific 249 bool bVdencEnabled = false; 250 bool bVdencStreamInEnable = false; 251 uint8_t ucVdencBitDepthMinus8 = 0; 252 bool bPakThresholdCheckEnable = false; 253 bool bVdencPakObjCmdStreamOutEnable = false; 254 bool bBatchBufferInUse = false; 255 bool bTlbPrefetchEnable = 0; 256 PMHW_BATCH_BUFFER pBatchBuffer = nullptr; 257 uint32_t ChromaType = 0; 258 MOS_FORMAT Format = {}; 259 bool isIFrame = false; 260 bool bIBCEnabled = false; 261 262 // HuC specific 263 uint32_t dwMediaSoftResetCounterValue = 0; 264 bool bAdvancedRateControlEnable = false; 265 bool bStreamObjectUsed = false; 266 // No need to set protection settings 267 bool disableProtectionSetting = false; 268 bool bFrameStatisticsStreamOutEnable = false; 269 270 MHW_VDBOX_HCP_PIPE_WORK_MODE PipeWorkMode = MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY; 271 MHW_VDBOX_HCP_MULTI_ENGINE_MODE MultiEngineMode = MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY; 272 ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMSMHW_VDBOX_PIPE_MODE_SELECT_PARAMS273 virtual ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMS() {} 274 }; 275 using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * ; 276 277 typedef struct _MHW_VDBOX_SURFACE_PARAMS 278 { 279 uint32_t Mode; 280 PMOS_SURFACE psSurface; // 2D surface parameters 281 uint8_t ucVDirection; 282 uint8_t ChromaType; 283 uint8_t ucSurfaceStateId; 284 uint8_t ucBitDepthLumaMinus8; 285 uint8_t ucBitDepthChromaMinus8; 286 uint32_t dwUVPlaneAlignment; 287 bool bDisplayFormatSwizzle; 288 bool bSrc8Pak10Mode; 289 bool bColorSpaceSelection; 290 bool bVdencDynamicScaling; 291 uint32_t dwActualWidth; 292 uint32_t dwActualHeight; 293 uint32_t dwReconSurfHeight; 294 MOS_MEMCOMP_STATE mmcState; 295 uint8_t mmcSkipMask; 296 uint32_t dwCompressionFormat; 297 uint8_t refsMmcEnable; 298 uint8_t refsMmcType; 299 } MHW_VDBOX_SURFACE_PARAMS, *PMHW_VDBOX_SURFACE_PARAMS; 300 301 struct MHW_VDBOX_PIPE_BUF_ADDR_PARAMS 302 { 303 uint32_t Mode = 0; 304 PMOS_SURFACE psPreDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface 305 MOS_MEMCOMP_STATE PreDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; 306 PMOS_SURFACE psPostDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface 307 MOS_MEMCOMP_STATE PostDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; 308 PMOS_SURFACE psRawSurface = nullptr; // Pointer to MOS_SURFACE of raw surface 309 MOS_MEMCOMP_STATE RawSurfMmcState = MOS_MEMCOMP_DISABLED; 310 PMOS_SURFACE ps4xDsSurface = nullptr; 311 MOS_MEMCOMP_STATE Ps4xDsSurfMmcState = MOS_MEMCOMP_DISABLED; 312 PMOS_SURFACE ps8xDsSurface = nullptr; 313 MOS_MEMCOMP_STATE Ps8xDsSurfMmcState = MOS_MEMCOMP_DISABLED; 314 PMOS_RESOURCE presDataBuffer = nullptr; // Handle of residual difference surface 315 PMOS_RESOURCE presReferences[CODEC_MAX_NUM_REF_FRAME] = {}; 316 PMOS_RESOURCE presMfdIntraRowStoreScratchBuffer = nullptr; // Handle of MFD Intra Row Store Scratch data surface 317 PMOS_RESOURCE presMfdDeblockingFilterRowStoreScratchBuffer = nullptr; // Handle of MFD Deblocking Filter Row Store Scratch data surface 318 PMOS_RESOURCE presStreamOutBuffer = nullptr; 319 MOS_MEMCOMP_STATE StreamOutBufMmcState = MOS_MEMCOMP_DISABLED; 320 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer1 = nullptr; 321 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer2 = nullptr; 322 PMOS_RESOURCE presSliceSizeStreamOutBuffer = nullptr; 323 PMOS_SURFACE psFwdRefSurface0 = nullptr; 324 PMOS_SURFACE psFwdRefSurface1 = nullptr; 325 PMOS_SURFACE psFwdRefSurface2 = nullptr; 326 bool bDynamicScalingEnable = false; 327 328 PMOS_RESOURCE presVdencIntraRowStoreScratchBuffer = nullptr; // For VDEnc, Handle of VDEnc Intra Row Store Scratch data surface 329 PMOS_RESOURCE presVdencTileRowStoreBuffer = nullptr; 330 PMOS_RESOURCE presVdencStreamOutBuffer = nullptr; 331 PMOS_RESOURCE presVdencCuObjStreamOutBuffer = nullptr; 332 PMOS_RESOURCE presVdencPakObjCmdStreamOutBuffer = nullptr; 333 PMOS_RESOURCE presVdencStreamInBuffer = nullptr; 334 PMOS_RESOURCE presVdencReferences[CODEC_MAX_NUM_REF_FRAME] = {}; 335 PMOS_RESOURCE presVdenc4xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; 336 PMOS_RESOURCE presVdenc8xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; 337 338 PMOS_RESOURCE presVdencColocatedMVWriteBuffer = nullptr; // For AVC only 339 PMOS_RESOURCE presVdencColocatedMVReadBuffer = nullptr; // For AVC only 340 PMOS_RESOURCE presDeblockingFilterTileRowStoreScratchBuffer = nullptr; // For HEVC, VP9 341 PMOS_RESOURCE presDeblockingFilterColumnRowStoreScratchBuffer = nullptr; // For HEVC, VP9 342 PMOS_RESOURCE presMetadataLineBuffer = nullptr; // For HEVC, VP9 343 PMOS_RESOURCE presMetadataTileLineBuffer = nullptr; // For HEVC, VP9 344 PMOS_RESOURCE presMetadataTileColumnBuffer = nullptr; // For HEVC, VP9 345 PMOS_RESOURCE presSaoLineBuffer = nullptr; // For HEVC only 346 PMOS_RESOURCE presSaoTileLineBuffer = nullptr; // For HEVC only 347 PMOS_RESOURCE presSaoTileColumnBuffer = nullptr; // For HEVC only 348 PMOS_RESOURCE presCurMvTempBuffer = nullptr; // For HEVC, VP9 349 PMOS_RESOURCE presColMvTempBuffer[CODEC_MAX_NUM_REF_FRAME] = {}; // For HEVC, VP9 350 PMOS_RESOURCE presLcuBaseAddressBuffer = nullptr; // For HEVC only 351 PMOS_RESOURCE presLcuILDBStreamOutBuffer = nullptr; // For HEVC only 352 PMOS_RESOURCE presVp9ProbBuffer = nullptr; // For VP9 only 353 PMOS_RESOURCE presVp9SegmentIdBuffer = nullptr; // For VP9 only 354 PMOS_RESOURCE presHvdLineRowStoreBuffer = nullptr; // For VP9 only 355 PMOS_RESOURCE presHvdTileRowStoreBuffer = nullptr; // For VP9 only 356 PMOS_RESOURCE presSaoStreamOutBuffer = nullptr; // For HEVC only 357 PMOS_RESOURCE presSaoRowStoreBuffer = nullptr; // For HEVC only 358 PMOS_SURFACE presP010RTSurface = nullptr; // For HEVC only 359 PMOS_RESOURCE presFrameStatStreamOutBuffer = nullptr; 360 PMOS_RESOURCE presSseSrcPixelRowStoreBuffer = nullptr; 361 PMOS_RESOURCE presSegmentMapStreamIn = nullptr; 362 PMOS_RESOURCE presSegmentMapStreamOut = nullptr; 363 PMOS_RESOURCE presPakCuLevelStreamoutBuffer = nullptr; 364 PMHW_VDBOX_SURFACE_PARAMS pRawSurfParam = nullptr; 365 PMHW_VDBOX_SURFACE_PARAMS pDecodedReconParam = nullptr; 366 bool bVdencEnabled = false; 367 bool bRawIs10Bit = false; 368 bool bDecodecReconIs10Bit = false; 369 uint32_t dwNumRefIdxL0ActiveMinus1 = 0; 370 uint32_t dwNumRefIdxL1ActiveMinus1 = 0; 371 uint32_t dwLcuStreamOutOffset = 0; 372 uint32_t dwFrameStatStreamOutOffset = 0; 373 uint32_t dwVdencStatsStreamOutOffset = 0; 374 bool oneOnOneMapping = false; // Flag for indicating using 1:1 ref index mapping for vdenc 375 bool isLowDelayB = true; // Flag to indicate if it is LDB 376 bool isIFrame = false; // Flag to indicate if it is I frame 377 bool isPFrame = false; // Flag to indicate if it is P frame 378 bool bIBCEnabled = false; 379 uint8_t IBCRefIdxMask = 0; 380 bool bMmcEnabled = false; 381 PMOS_RESOURCE presVdencCumulativeCuCountStreamoutSurface = nullptr; ~MHW_VDBOX_PIPE_BUF_ADDR_PARAMSMHW_VDBOX_PIPE_BUF_ADDR_PARAMS382 virtual ~MHW_VDBOX_PIPE_BUF_ADDR_PARAMS() {} 383 }; 384 using PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS = MHW_VDBOX_PIPE_BUF_ADDR_PARAMS * ; 385 386 typedef struct _MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS 387 { 388 uint32_t Mode; 389 PMOS_RESOURCE presDataBuffer; 390 uint32_t dwDataSize; 391 uint32_t dwDataOffset; 392 PMOS_RESOURCE presMvObjectBuffer; 393 uint32_t dwMvObjectSize; 394 uint32_t dwMvObjectOffset; 395 PMOS_RESOURCE presPakBaseObjectBuffer; 396 uint32_t dwPakBaseObjectSize; 397 uint32_t dwPakBaseObjectOffset; 398 PMOS_RESOURCE presPakTileSizeStasBuffer; 399 uint32_t dwPakTileSizeStasBufferSize; 400 uint32_t dwPakTileSizeRecordOffset; 401 // used by VP9 402 PMOS_RESOURCE presCompressedHeaderBuffer; 403 uint32_t dwCompressedHeaderSize; 404 PMOS_RESOURCE presProbabilityDeltaBuffer; 405 uint32_t dwProbabilityDeltaSize; 406 PMOS_RESOURCE presProbabilityCounterBuffer; 407 uint32_t dwProbabilityCounterOffset; 408 uint32_t dwProbabilityCounterSize; 409 PMOS_RESOURCE presTileRecordBuffer; 410 uint32_t dwTileRecordSize; 411 PMOS_RESOURCE presCuStatsBuffer; 412 uint32_t dwCuStatsSize; 413 414 PMOS_RESOURCE presStreamOutObjectBuffer; 415 uint32_t dwStreamOutObjectSize; 416 uint32_t dwStreamOutObjectOffset; 417 } MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS, *PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS; 418 419 struct MHW_VDBOX_AVC_IMG_PARAMS 420 { 421 // Decoding Params 422 PCODEC_AVC_PIC_PARAMS pAvcPicParams = nullptr; 423 PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams = nullptr; 424 uint8_t ucActiveFrameCnt = 0; 425 // Encoding Params 426 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams = nullptr; 427 PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams = nullptr; 428 PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams = nullptr; 429 PCODEC_REF_LIST *ppRefList = nullptr; 430 CODEC_PIC_ID *pPicIdx = nullptr; 431 uint32_t dwTqEnabled = 0; 432 uint32_t dwTqRounding = 0; 433 uint32_t dwMaxVmvR = 0; 434 uint16_t wPicWidthInMb = 0; 435 uint16_t wPicHeightInMb = 0; 436 uint16_t wSlcHeightInMb = 0; 437 uint8_t ucKernelMode = 0; // normal, performance, quality. 438 439 //FEI multiple passes PAK ---max frame size 440 uint16_t currPass = 0; 441 uint8_t *pDeltaQp = nullptr; 442 uint32_t dwMaxFrameSize = 0; 443 444 bool bIPCMPass = false; 445 // VDEnc specific 446 bool bVdencEnabled = false; 447 bool bVDEncPerfModeEnabled = false; 448 bool bVdencStreamInEnabled = false; 449 bool bVdencBRCEnabled = false; 450 bool bSliceSizeStreamOutEnabled = false; 451 bool bCrePrefetchEnable = false; 452 bool bPerMBStreamOut = false; 453 bool bRollingIRestrictFracCand = false; 454 455 uint32_t dwMbSlcThresholdValue = 0; // For VDENC dynamic slice size control 456 uint32_t dwVdencSliceMinusBytes = 0; 457 uint8_t *pVDEncModeCost = nullptr; 458 uint8_t *pVDEncMvCost = nullptr; 459 uint8_t *pVDEncHmeMvCost = nullptr; 460 uint32_t biWeight = 0; ~MHW_VDBOX_AVC_IMG_PARAMSMHW_VDBOX_AVC_IMG_PARAMS461 virtual ~MHW_VDBOX_AVC_IMG_PARAMS(){} 462 }; 463 using PMHW_VDBOX_AVC_IMG_PARAMS = MHW_VDBOX_AVC_IMG_PARAMS * ; 464 465 typedef struct _MHW_VDBOX_QM_PARAMS 466 { 467 uint32_t Standard; 468 uint32_t Mode; 469 PMHW_VDBOX_AVC_QM_PARAMS pAvcIqMatrix; 470 CodecMpeg2IqMatrix *pMpeg2IqMatrix; 471 CodecJpegQuantMatrix *pJpegQuantMatrix; 472 uint32_t JpegQMTableSelector; 473 bool bJpegQMRotation; 474 PMHW_VDBOX_HEVC_QM_PARAMS pHevcIqMatrix; 475 } MHW_VDBOX_QM_PARAMS, *PMHW_VDBOX_QM_PARAMS; 476 477 typedef struct _MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS 478 { 479 uint32_t uiList; 480 uint32_t uiLumaLogWeightDenom; 481 uint32_t uiChromaLogWeightDenom; 482 uint32_t uiLumaWeightFlag; 483 uint32_t uiChromaWeightFlag; 484 uint32_t uiNumRefForList; 485 int16_t Weights[2][32][3][2]; 486 PCODEC_AVC_ENCODE_PIC_PARAMS pAvcPicParams; 487 } MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS, *PMHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS; 488 489 typedef struct _MHW_VDBOX_PAK_INSERT_PARAMS 490 { 491 PBSBuffer pBsBuffer; 492 // also reuse dwBitSize for passing SrcDataEndingBitInclusion when (pEncoder->bLastPicInStream || pEncoder->bLastPicInSeq) 493 uint32_t dwBitSize; 494 uint32_t dwOffset; 495 uint32_t uiSkipEmulationCheckCount; 496 bool bLastPicInSeq; 497 bool bLastPicInStream; 498 bool bLastHeader; 499 bool bEmulationByteBitsInsert; 500 bool bSetLastPicInStreamData; 501 bool bSliceHeaderIndicator; 502 bool bHeaderLengthExcludeFrmSize; 503 uint32_t *pdwMpeg2PicHeaderTotalBufferSize; 504 uint32_t *pdwMpeg2PicHeaderDataStartOffset; 505 bool bResetBitstreamStartingPos; 506 bool bEndOfSlice; 507 uint32_t dwLastPicInSeqData; 508 uint32_t dwLastPicInStreamData; 509 PMHW_BATCH_BUFFER pBatchBufferForPakSlices; 510 bool bVdencInUse; 511 } MHW_VDBOX_PAK_INSERT_PARAMS, *PMHW_VDBOX_PAK_INSERT_PARAMS; 512 513 typedef struct _MHW_VDBOX_VP9_SEGMENT_STATE 514 { 515 uint32_t Mode; 516 PCODEC_VP9_SEGMENT_PARAMS pVp9SegmentParams; 517 PCODEC_VP9_ENCODE_SEGMENT_PARAMS pVp9EncodeSegmentParams; 518 uint8_t ucCurrentSegmentId; 519 uint8_t ucQPIndexLumaAC; 520 const uint8_t *pcucLfQpLookup; 521 uint8_t *pbSegStateBufferPtr; 522 } MHW_VDBOX_VP9_SEGMENT_STATE, *PMHW_VDBOX_VP9_SEGMENT_STATE; 523 524 typedef struct _MHW_VDBOX_HCP_BSD_PARAMS 525 { 526 uint32_t dwBsdDataLength; 527 uint32_t dwBsdDataStartOffset; 528 } MHW_VDBOX_HCP_BSD_PARAMS, *PMHW_VDBOX_HCP_BSD_PARAMS; 529 530 typedef struct _MHW_VDBOX_ROWSTORE_PARAMS 531 { 532 uint32_t Mode = 0; 533 uint32_t dwPicWidth = 0; 534 uint32_t bMbaff = 0; 535 bool bIsFrame = false; 536 uint8_t ucBitDepthMinus8 = 0; 537 uint8_t ucChromaFormat = 0; 538 uint8_t ucLCUSize = 0; 539 } MHW_VDBOX_ROWSTORE_PARAMS, *PMHW_VDBOX_ROWSTORE_PARAMS; 540 541 typedef struct _MHW_VDBOX_ROWSTORE_CACHE 542 { 543 bool bSupported; 544 bool bEnabled; 545 uint32_t dwAddress; 546 } MHW_VDBOX_ROWSTORE_CACHE, *PMHW_VDBOX_ROWSTORE_CACHE; 547 548 struct MHW_VDBOX_STATE_CMDSIZE_PARAMS 549 { 550 bool bShortFormat = false; 551 bool bHucDummyStream = false; 552 bool bSfcInUse = false; 553 bool bDecodeInUse = false; 554 uint32_t uNumStoreDataImm = 0; 555 uint32_t uNumStoreReg = 0; 556 uint32_t uNumMfxWait = 0; 557 uint32_t uNumAddConBBEnd = 0; 558 uint32_t uNumMiCopy = 0; 559 uint32_t uNumMiFlush = 0; 560 uint32_t bPerformHucStreamOut = false; 561 uint32_t uNumVdPipelineFlush = 0; ~MHW_VDBOX_STATE_CMDSIZE_PARAMSMHW_VDBOX_STATE_CMDSIZE_PARAMS562 virtual ~MHW_VDBOX_STATE_CMDSIZE_PARAMS() {} 563 }; 564 using PMHW_VDBOX_STATE_CMDSIZE_PARAMS = MHW_VDBOX_STATE_CMDSIZE_PARAMS * ; 565 566 typedef struct _MHW_VDBOX_AVC_SLICE_STATE 567 { 568 PCODEC_PIC_ID pAvcPicIdx = {}; 569 PMOS_RESOURCE presDataBuffer = nullptr; 570 uint32_t dwDataBufferOffset = 0; 571 uint32_t dwOffset = 0; 572 uint32_t dwLength = 0; 573 uint32_t dwSliceIndex = 0; 574 bool bLastSlice = false; 575 uint32_t dwTotalBytesConsumed = 0; 576 577 // Decoding Only 578 PCODEC_AVC_PIC_PARAMS pAvcPicParams = nullptr; 579 PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams = nullptr; 580 PCODEC_AVC_SLICE_PARAMS pAvcSliceParams = nullptr; 581 uint32_t dwNextOffset = 0; 582 uint32_t dwNextLength = 0; 583 bool bIntelEntrypointInUse = false; 584 bool bPicIdRemappingInUse = false; 585 bool bShortFormatInUse = false; 586 bool bPhantomSlice = false; 587 uint8_t ucDisableDeblockingFilterIdc = 0; 588 uint8_t ucSliceBetaOffsetDiv2 = 0; 589 uint8_t ucSliceAlphaC0OffsetDiv2 = 0; 590 591 // Encoding Only 592 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams = nullptr; 593 PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams = nullptr; 594 PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams = nullptr; 595 PBSBuffer pBsBuffer = nullptr; 596 PCODECHAL_NAL_UNIT_PARAMS * ppNalUnitParams = nullptr; 597 PMHW_BATCH_BUFFER pBatchBufferForPakSlices = nullptr; 598 bool bSingleTaskPhaseSupported = false; 599 bool bFirstPass = false; 600 bool bLastPass = false; 601 bool bBrcEnabled = false; 602 bool bRCPanicEnable = false; 603 bool bInsertBeforeSliceHeaders = false; 604 bool bAcceleratorHeaderPackingCaps = false; 605 uint32_t dwBatchBufferForPakSlicesStartOffset = 0; 606 uint32_t uiSkipEmulationCheckCount = 0; 607 uint32_t dwRoundingValue = 0; 608 uint32_t dwRoundingIntraValue = 0; 609 bool bRoundingInterEnable = false; 610 uint16_t wFrameFieldHeightInMB = 0; // Frame/field Height in MB 611 bool bVdencInUse = false; 612 bool bVdencNoTailInsertion = false; 613 bool oneOnOneMapping = false; 614 bool bFullFrameData = false; 615 } MHW_VDBOX_AVC_SLICE_STATE, *PMHW_VDBOX_AVC_SLICE_STATE; 616 617 typedef enum _MHW_VDBOX_DECODE_JPEG_FORMAT_CODE 618 { 619 MHW_VDBOX_DECODE_JPEG_FORMAT_SEPARATE_PLANE = 0, // formats of 3 separate plane for Y, U, and V respectively 620 MHW_VDBOX_DECODE_JPEG_FORMAT_NV12 = 1, 621 MHW_VDBOX_DECODE_JPEG_FORMAT_UYVY = 2, 622 MHW_VDBOX_DECODE_JPEG_FORMAT_YUY2 = 3 623 } MHW_VDBOX_DECODE_JPEG_FORMAT_CODE; 624 625 typedef struct _MHW_VDBOX_GPUNODE_LIMIT 626 { 627 bool bHcpInUse; 628 bool bHuCInUse; 629 bool bSfcInUse; 630 uint32_t dwGpuNodeToUse; 631 } MHW_VDBOX_GPUNODE_LIMIT, *PMHW_VDBOX_GPUNODE_LIMIT; 632 633 typedef enum _MHW_VDBOX_AVC_DMV_OFFSET 634 { 635 MHW_VDBOX_AVC_DMV_DEST_TOP = 32, 636 MHW_VDBOX_AVC_DMV_DEST_BOTTOM = 33 637 } MHW_VDBOX_AVC_DMV_OFFSET; 638 639 #endif 640