1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /** 3 * Copyright 2019-2024 NXP 4 * 5 * KEYWORDS: micro-power uPower driver API 6 * ----------------------------------------------------------------------------- 7 * PURPOSE: uPower driver API #defines and typedefs shared with the firmware 8 * ----------------------------------------------------------------------------- 9 * PARAMETERS: 10 * PARAM NAME RANGE:DESCRIPTION: DEFAULTS: UNITS 11 * ----------------------------------------------------------------------------- 12 * REUSE ISSUES: no reuse issues 13 */ 14 15 #ifndef UPWR_DEFS_H 16 #define UPWR_DEFS_H 17 18 #include <stdint.h> 19 20 #ifndef UPWR_PMC_SWT_WORDS 21 #define UPWR_PMC_SWT_WORDS (1U) 22 #endif 23 24 #ifndef UPWR_PMC_MEM_WORDS 25 #define UPWR_PMC_MEM_WORDS (2U) 26 #endif 27 28 /* **************************************************************************** 29 * DOWNSTREAM MESSAGES - COMMANDS/FUNCTIONS 30 * **************************************************************************** 31 */ 32 #define UPWR_SRVGROUP_BITS (4U) 33 #define UPWR_FUNCTION_BITS (4U) 34 #define UPWR_PWDOMAIN_BITS (4U) 35 #define UPWR_HEADER_BITS \ 36 (UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS + UPWR_PWDOMAIN_BITS) 37 #define UPWR_ARG_BITS (32U - UPWR_HEADER_BITS) 38 #if ((UPWR_ARG_BITS & 1U) > 0U) 39 #error "UPWR_ARG_BITS must be an even number" 40 #endif 41 #define UPWR_ARG64_BITS (64U - UPWR_HEADER_BITS) 42 #define UPWR_HALF_ARG_BITS (UPWR_ARG_BITS >> 1U) 43 #define UPWR_DUAL_OFFSET_BITS ((UPWR_ARG_BITS + 32U) >> 1U) 44 45 /* 46 * message header: header fields common to all downstream messages. 47 */ 48 struct upwr_msg_hdr { 49 uint32_t domain : UPWR_PWDOMAIN_BITS; /* power domain */ 50 uint32_t srvgrp : UPWR_SRVGROUP_BITS; /* service group */ 51 uint32_t function : UPWR_FUNCTION_BITS; /* function */ 52 uint32_t arg : UPWR_ARG_BITS; /* function-specific argument */ 53 }; 54 55 /* generic 1-word downstream message format */ 56 typedef union { 57 struct upwr_msg_hdr hdr; 58 uint32_t word; /* message first word */ 59 } upwr_down_1w_msg; 60 61 /* generic 2-word downstream message format */ 62 typedef struct { 63 struct upwr_msg_hdr hdr; 64 uint32_t word2; /* message second word */ 65 } upwr_down_2w_msg; 66 67 /* message format for functions that receive a pointer/offset */ 68 typedef struct { 69 struct upwr_msg_hdr hdr; 70 uint32_t ptr; /* config struct offset */ 71 } upwr_pointer_msg; 72 73 /* message format for functions that receive 2 pointers/offsets */ 74 typedef union { 75 struct upwr_msg_hdr hdr; 76 struct { 77 uint64_t rsv : UPWR_HEADER_BITS; 78 uint64_t ptr0 : UPWR_DUAL_OFFSET_BITS; 79 uint64_t ptr1 : UPWR_DUAL_OFFSET_BITS; 80 } ptrs; 81 } upwr_2pointer_msg; 82 83 #define UPWR_SG_EXCEPT (0U) /* 0 = exception */ 84 #define UPWR_SG_PWRMGMT (1U) /* 1 = power management */ 85 #define UPWR_SG_DELAYM (2U) /* 2 = delay measurement */ 86 #define UPWR_SG_VOLTM (3U) /* 3 = voltage measurement */ 87 #define UPWR_SG_CURRM (4U) /* 4 = current measurement */ 88 #define UPWR_SG_TEMPM (5U) /* 5 = temperature measurement */ 89 #define UPWR_SG_DIAG (6U) /* 6 = diagnostic */ 90 #define UPWR_SG_COUNT (7U) 91 92 typedef uint32_t upwr_sg_t; 93 94 /* ************************************************************************* 95 * Initialization - downstream 96 ***************************************************************************/ 97 typedef upwr_down_1w_msg upwr_start_msg; /* start command message */ 98 typedef upwr_down_1w_msg upwr_power_on_msg; /* power on command message */ 99 typedef upwr_down_1w_msg upwr_boot_start_msg; /* boot start command message */ 100 typedef union { 101 struct upwr_msg_hdr hdr; 102 upwr_power_on_msg power_on; 103 upwr_boot_start_msg boot_start; 104 upwr_start_msg start; 105 } upwr_startup_down_msg; 106 107 /* ************************************************************************* 108 * Service Group EXCEPTION - downstream 109 ***************************************************************************/ 110 111 #define UPWR_XCP_INIT (0U) /* 0 = init msg (not a service request itself) */ 112 #define UPWR_XCP_PING (0U) /* 0 = also ping request, since its response isan init msg */ 113 #define UPWR_XCP_START (1U) /* 1 = service start: upwr_start *(not a service request itself) */ 114 #define UPWR_XCP_SHUTDOWN (2U) /* 2 = service shutdown: upwr_xcp_shutdown */ 115 #define UPWR_XCP_CONFIG (3U) /* 3 = uPower configuration: upwr_xcp_config */ 116 #define UPWR_XCP_SW_ALARM (4U) /* 4 = uPower software alarm: upwr_xcp_sw_alarm */ 117 #define UPWR_XCP_I2C (5U) /* 5 = I2C access: upwr_xcp_i2c_access */ 118 #define UPWR_XCP_SPARE_6 (6U) /* 6 = spare */ 119 #define UPWR_XCP_SET_DDR_RETN (7U) /* 7 = set/clear ddr retention */ 120 #define UPWR_XCP_SET_RTD_APD_LLWU (8U) /* 8 = set/clear rtd/apd llwu */ 121 #define UPWR_XCP_SPARE_8 (8U) /* 8 = spare */ 122 #define UPWR_XCP_SET_RTD_USE_DDR (9U) /* 9 = M33 core set it is using DDR or not */ 123 #define UPWR_XCP_SPARE_9 (9U) /* 9 = spare */ 124 #define UPWR_XCP_SPARE_10 (10U) /* 10 = spare */ 125 #define UPWR_XCP_SET_MIPI_DSI_ENA (10U) /* 10 = set/clear mipi dsi ena */ 126 #define UPWR_XCP_SPARE_11 (11U) /* 11 = spare */ 127 #define UPWR_XCP_GET_MIPI_DSI_ENA (11U) /* 11 = get mipi dsi ena status */ 128 #define UPWR_XCP_SPARE_12 (12U) /* 12 = spare */ 129 #define UPWR_XCP_SET_OSC_MODE (12U) /* 12 = set uPower OSC mode, high or low */ 130 #define UPWR_XCP_SPARE_13 (13U) /* 13 = spare */ 131 #define UPWR_XCP_SPARE_14 (14U) /* 14 = spare */ 132 #define UPWR_XCP_SPARE_15 (15U) /* 15 = spare */ 133 #define UPWR_XCP_F_COUNT (16U) 134 135 typedef uint32_t upwr_xcp_f_t; 136 typedef upwr_down_1w_msg upwr_xcp_ping_msg; 137 typedef upwr_down_1w_msg upwr_xcp_shutdown_msg; 138 typedef upwr_power_on_msg upwr_xcp_power_on_msg; 139 typedef upwr_boot_start_msg upwr_xcp_boot_start_msg; 140 typedef upwr_start_msg upwr_xcp_start_msg; 141 typedef upwr_down_2w_msg upwr_xcp_config_msg; 142 typedef upwr_down_1w_msg upwr_xcp_swalarm_msg; 143 typedef upwr_down_1w_msg upwr_xcp_ddr_retn_msg; 144 typedef upwr_down_1w_msg upwr_xcp_set_mipi_dsi_ena_msg; 145 typedef upwr_down_1w_msg upwr_xcp_get_mipi_dsi_ena_msg; 146 typedef upwr_down_1w_msg upwr_xcp_rtd_use_ddr_msg; 147 typedef upwr_down_1w_msg upwr_xcp_rtd_apd_llwu_msg; 148 typedef upwr_down_1w_msg upwr_xcp_set_osc_mode_msg; 149 typedef upwr_pointer_msg upwr_xcp_i2c_msg; 150 151 /* structure pointed by message upwr_xcp_i2c_msg */ 152 typedef struct { 153 uint16_t addr; 154 int8_t data_size; 155 uint8_t subaddr_size; 156 uint32_t subaddr; 157 uint32_t data; 158 } upwr_i2c_access; 159 160 /* Exception all messages */ 161 typedef union { 162 struct upwr_msg_hdr hdr; /* message header */ 163 upwr_xcp_ping_msg ping; /* ping */ 164 upwr_xcp_start_msg start; /* service start */ 165 upwr_xcp_shutdown_msg shutdown; /* shutdown */ 166 upwr_xcp_boot_start_msg bootstart; /* boot start */ 167 upwr_xcp_config_msg config; /* uPower configuration */ 168 upwr_xcp_swalarm_msg swalarm; /* software alarm */ 169 upwr_xcp_i2c_msg i2c; /* I2C access */ 170 upwr_xcp_ddr_retn_msg set_ddr_retn; /* set ddr retention msg */ 171 upwr_xcp_set_mipi_dsi_ena_msg set_mipi_dsi_ena; /* set mipi dsi ena msg */ 172 upwr_xcp_get_mipi_dsi_ena_msg get_mipi_dsi_ena; /* get mipi dsi ena msg */ 173 upwr_xcp_rtd_use_ddr_msg set_rtd_use_ddr; /* set rtd is using ddr msg */ 174 upwr_xcp_rtd_apd_llwu_msg set_llwu; /* set rtd/apd llwu msg */ 175 upwr_xcp_set_osc_mode_msg set_osc_mode; /* set osc_mode msg */ 176 } upwr_xcp_msg; 177 178 /* structure pointed by message upwr_volt_dva_req_id_msg */ 179 typedef struct { 180 uint32_t id_word0; 181 uint32_t id_word1; 182 uint32_t mode; 183 } upwr_dva_id_struct; 184 185 /** 186 * PMIC voltage accuracy is 12.5 mV, 12500 uV 187 */ 188 #define PMIC_VOLTAGE_MIN_STEP 12500U 189 190 /* ************************************************************************* 191 * Service Group POWER MANAGEMENT - downstream 192 ***************************************************************************/ 193 194 #define UPWR_PWM_REGCFG (0U) /* 0 = regulator config: upwr_pwm_reg_config */ 195 #define UPWR_PWM_DEVMODE (0U) /* deprecated, for old compile */ 196 #define UPWR_PWM_VOLT (1U) /* 1 = voltage change: upwr_pwm_chng_reg_voltage */ 197 #define UPWR_PWM_SWITCH (2U) /* 2 = switch control: upwr_pwm_chng_switch_mem */ 198 #define UPWR_PWM_PWR_ON (3U) /* 3 = switch/RAM/ROM power on: upwr_pwm_power_on */ 199 #define UPWR_PWM_PWR_OFF (4U) /* 4 = switch/RAM/ROM power off: upwr_pwm_power_off */ 200 #define UPWR_PWM_RETAIN (5U) /* 5 = retain memory array: upwr_pwm_mem_retain */ 201 #define UPWR_PWM_DOM_BIAS (6U) /* 6 = Domain bias control: upwr_pwm_chng_dom_bias */ 202 #define UPWR_PWM_MEM_BIAS (7U) /* 7 = Memory bias control: upwr_pwm_chng_mem_bias */ 203 #define UPWR_PWM_PMICCFG (8U) /* 8 = PMIC configuration: upwr_pwm_pmic_config */ 204 #define UPWR_PWM_PMICMOD (8U) /* deprecated, for old compile */ 205 #define UPWR_PWM_PES (9U) /* 9 so far, no use */ 206 #define UPWR_PWM_CONFIG (10U) /* 10= apply power mode defined configuration */ 207 #define UPWR_PWM_CFGPTR (11U) /* 11= configuration pointer */ 208 #define UPWR_PWM_DOM_PWRON (12U) /* 12 = domain power on: upwr_pwm_dom_power_on */ 209 #define UPWR_PWM_BOOT (13U) /* 13 = boot start: upwr_pwm_boot_start */ 210 #define UPWR_PWM_FREQ (14U) /* 14 = domain frequency setup */ 211 #define UPWR_PWM_PARAM (15U) /* 15 = power management parameters */ 212 #define UPWR_PWM_F_COUNT (16U) 213 214 typedef uint32_t upwr_pwm_f_t; 215 216 #define MAX_PMETER_SSEL 7U 217 218 #define UPWR_VTM_CHNG_PMIC_RAIL_VOLT (0U) /* 0 = change pmic rail voltage */ 219 #define UPWR_VTM_GET_PMIC_RAIL_VOLT (1U) /* 1 = get pmic rail voltage */ 220 #define UPWR_VTM_PMIC_CONFIG (2U) /* 2 = configure PMIC IC */ 221 #define UPWR_VTM_DVA_DUMP_INFO (3U) /* 3 = dump dva information */ 222 #define UPWR_VTM_DVA_REQ_ID (4U) /* 4 = dva request ID array */ 223 #define UPWR_VTM_DVA_REQ_DOMAIN (5U) /* 5 = dva request domain */ 224 #define UPWR_VTM_DVA_REQ_SOC (6U) /* 6 = dva request the whole SOC */ 225 #define UPWR_VTM_PMETER_MEAS (7U) /* 7 = pmeter measure */ 226 #define UPWR_VTM_VMETER_MEAS (8U) /* 8 = vmeter measure */ 227 #define UPWR_VTM_PMIC_COLD_RESET (9U) /* 9 = pmic cold reset */ 228 #define UPWR_VTM_SET_DVFS_PMIC_RAIL (10U) /* 10 = set which domain use which pmic rail, for DVFS use */ 229 #define UPWR_VTM_SET_PMIC_MODE (11U) /* 11 = set pmic mode */ 230 #define UPWR_VTM_F_COUNT (16U) 231 232 typedef uint32_t upwr_volt_f_t; 233 234 #define VMETER_SEL_RTD 0U 235 #define VMETER_SEL_LDO 1U 236 #define VMETER_SEL_APD 2U 237 #define VMETER_SEL_AVD 3U 238 #define VMETER_SEL_MAX 3U 239 240 /** 241 * The total TSEL count is 256 242 */ 243 #define MAX_TEMP_TSEL 256U 244 245 /** 246 * Support 3 temperature sensor, sensor 0, 1, 2 247 */ 248 #define MAX_TEMP_SENSOR 2U 249 250 #define UPWR_TEMP_GET_CUR_TEMP (0U) /* 0 = get current temperature */ 251 #define UPWR_TEMP_F_COUNT (1U) 252 typedef uint32_t upwr_temp_f_t; 253 254 #define UPWR_DMETER_GET_DELAY_MARGIN (0U) /* 0 = get delay margin */ 255 #define UPWR_DMETER_SET_DELAY_MARGIN (1U) /* 1 = set delay margin */ 256 #define UPWR_PMON_REQ (2U) /* 2 = process monitor service */ 257 #define UPWR_DMETER_F_COUNT (3U) 258 259 typedef uint32_t upwr_dmeter_f_t; 260 261 typedef upwr_down_1w_msg upwr_volt_pmeter_meas_msg; 262 typedef upwr_down_1w_msg upwr_volt_pmic_set_mode_msg; 263 typedef upwr_down_1w_msg upwr_volt_vmeter_meas_msg; 264 265 struct upwr_reg_config_t { 266 uint32_t reg; 267 }; 268 269 /* set of 32 switches */ 270 struct upwr_switch_board_t { 271 uint32_t on; /* Switch on state,1 bit per instance */ 272 uint32_t mask; /* actuation mask, 1 bit per instance */ 273 }; 274 275 /* set of 32 RAM/ROM switches */ 276 struct upwr_mem_switches_t { 277 uint32_t array; /* RAM/ROM array state, 1 bit per instance */ 278 uint32_t perif; /* RAM/ROM peripheral state, 1 bit per instance */ 279 uint32_t mask; /* actuation mask, 1 bit per instance */ 280 }; 281 282 typedef upwr_down_1w_msg upwr_pwm_dom_pwron_msg; /* domain power on message */ 283 typedef upwr_down_1w_msg upwr_pwm_boot_start_msg; /* boot start message */ 284 285 /* functions with complex arguments use the pointer message formats: */ 286 typedef upwr_pointer_msg upwr_pwm_retain_msg; 287 typedef upwr_pointer_msg upwr_pwm_pmode_cfg_msg; 288 289 #if (UPWR_ARG_BITS < UPWR_DOMBIAS_ARG_BITS) 290 #if ((UPWR_ARG_BITS + 32) < UPWR_DOMBIAS_ARG_BITS) 291 #error "too few message bits for domain bias argument" 292 #endif 293 #endif 294 295 /* service upwr_pwm_chng_dom_bias message argument fields */ 296 #define UPWR_DOMBIAS_MODE_BITS (2U) 297 #define UPWR_DOMBIAS_RBB_BITS (8U) 298 #define UPWR_DOMBIAS_RSV_BITS (14U) 299 #define UPWR_DOMBIAS_ARG_BITS (UPWR_DOMBIAS_RSV_BITS + \ 300 (2U * UPWR_DOMBIAS_MODE_BITS) + \ 301 (4U * UPWR_DOMBIAS_RBB_BITS) + 2U) 302 /* 303 * upwr_pwm_dom_bias_args is an SoC-dependent message, 304 */ 305 typedef struct { 306 uint32_t: 12U; /* TODO: find a way to use UPWR_HEADER_BITS */ 307 uint32_t dommode : UPWR_DOMBIAS_MODE_BITS; 308 uint32_t avdmode : UPWR_DOMBIAS_MODE_BITS; 309 uint32_t domapply : 1U; 310 uint32_t avdapply : 1U; 311 uint32_t rsv : UPWR_DOMBIAS_RSV_BITS; 312 uint32_t domrbbn : UPWR_DOMBIAS_RBB_BITS; /* RTD/APD back bias N-well */ 313 uint32_t domrbbp : UPWR_DOMBIAS_RBB_BITS; /* RTD/APD back bias P-well */ 314 uint32_t avdrbbn : UPWR_DOMBIAS_RBB_BITS; /* AVD back bias N-well */ 315 uint32_t avdrbbp : UPWR_DOMBIAS_RBB_BITS; /* AVD back bias P-well */ 316 } upwr_pwm_dom_bias_args; 317 318 319 typedef union { 320 struct upwr_msg_hdr hdr; /* message header */ 321 struct { 322 upwr_pwm_dom_bias_args B; 323 } args; 324 } upwr_pwm_dom_bias_msg; 325 326 /* service upwr_pwm_chng_mem_bias message argument fields */ 327 /* 328 * upwr_pwm_mem_bias_args is an SoC-dependent message, 329 * defined in upower_soc_defs.h 330 */ 331 typedef struct { 332 uint32_t: 12U; /* TODO: find a way to use UPWR_HEADER_BITS */ 333 uint32_t en : 1U; 334 uint32_t rsv : 19U; 335 } upwr_pwm_mem_bias_args; 336 337 typedef union { 338 struct upwr_msg_hdr hdr; /* message header */ 339 struct { 340 upwr_pwm_mem_bias_args B; 341 } args; 342 } upwr_pwm_mem_bias_msg; 343 344 typedef upwr_pointer_msg upwr_pwm_pes_seq_msg; 345 346 /* upwr_pwm_reg_config-specific message format */ 347 typedef upwr_pointer_msg upwr_pwm_regcfg_msg; 348 349 /* upwr_volt_pmic_volt-specific message format */ 350 typedef union { 351 struct upwr_msg_hdr hdr; /* message header */ 352 struct { 353 uint32_t rsv : UPWR_HEADER_BITS; 354 uint32_t domain : 8U; 355 uint32_t rail : 8U; 356 } args; 357 } upwr_volt_dom_pmic_rail_msg; 358 359 typedef union { 360 struct upwr_msg_hdr hdr; 361 struct { 362 uint32_t rsv : UPWR_HEADER_BITS; 363 uint32_t rail : 4U; /* pmic rail id */ 364 uint32_t volt : 12U; /* voltage value, accurate to mV, support 0~3.3V */ 365 } args; 366 } upwr_volt_pmic_set_volt_msg; 367 368 typedef union { 369 struct upwr_msg_hdr hdr; 370 struct { 371 uint32_t rsv : UPWR_HEADER_BITS; 372 uint32_t rail : 16U; /* pmic rail id */ 373 } args; 374 } upwr_volt_pmic_get_volt_msg; 375 376 typedef union { 377 struct upwr_msg_hdr hdr; 378 struct { 379 uint32_t rsv :UPWR_HEADER_BITS; 380 uint32_t domain : 8U; 381 uint32_t mode : 8U; /* work mode */ 382 } args; 383 } upwr_volt_dva_req_domain_msg; 384 385 typedef union { 386 struct upwr_msg_hdr hdr; 387 struct { 388 uint32_t rsv : UPWR_HEADER_BITS; 389 uint32_t mode : 16U; /* work mode */ 390 } args; 391 } upwr_volt_dva_req_soc_msg; 392 393 typedef union { 394 struct upwr_msg_hdr hdr; 395 struct { 396 uint32_t rsv : UPWR_HEADER_BITS; 397 uint32_t addr_offset : 16U; /* addr_offset to 0x28330000 */ 398 } args; 399 } upwr_volt_dva_dump_info_msg; 400 401 typedef upwr_pointer_msg upwr_volt_pmiccfg_msg; 402 typedef upwr_pointer_msg upwr_volt_dva_req_id_msg; 403 typedef upwr_down_1w_msg upwr_volt_pmic_cold_reset_msg; 404 405 /* upwr_pwm_volt-specific message format */ 406 typedef union { 407 struct upwr_msg_hdr hdr; 408 struct { 409 uint32_t rsv : UPWR_HEADER_BITS; 410 uint32_t reg : UPWR_HALF_ARG_BITS; /* regulator id */ 411 uint32_t volt : UPWR_HALF_ARG_BITS; /* voltage value */ 412 } args; 413 } upwr_pwm_volt_msg; 414 415 /* upwr_pwm_freq_setup-specific message format */ 416 /** 417 * DVA adjust stage 418 */ 419 #define DVA_ADJUST_STAGE_INVALID 0U 420 /* first stage, gross adjust, for increase frequency use */ 421 #define DVA_ADJUST_STAGE_ONE 1U 422 /* second stage, fine adjust for increase frequency use */ 423 #define DVA_ADJUST_STAGE_TWO 2U 424 /* combine first + second stage, for descrese frequency use */ 425 #define DVA_ADJUST_STAGE_FULL 3U 426 427 /** 428 * This message structure is used for DVFS feature 429 * 1. Because user may use different PMIC or different board, 430 * the pmic regulator of RTD/APD may change, 431 * so, user need to tell uPower the regulator number. 432 * The number must be matched with PMIC IC and board. 433 * use 4 bits for pmic regulator, support to 16 regulator. 434 * 435 * use 2 bits for DVA stage 436 * 437 * use 10 bits for target frequency, accurate to MHz, support to 1024 MHz 438 */ 439 typedef union { 440 struct upwr_msg_hdr hdr; 441 struct { 442 uint32_t rsv : UPWR_HEADER_BITS; 443 uint32_t rail : 4; /* pmic regulator */ 444 uint32_t stage : 2; /* DVA stage */ 445 uint32_t target_freq : 10; /* target frequency */ 446 } args; 447 } upwr_pwm_freq_msg; 448 449 typedef upwr_down_2w_msg upwr_pwm_param_msg; 450 451 /* upwr_pwm_pmiccfg-specific message format */ 452 typedef upwr_pointer_msg upwr_pwm_pmiccfg_msg; 453 454 /* functions that pass a pointer use message format upwr_pointer_msg */ 455 typedef upwr_pointer_msg upwr_pwm_cfgptr_msg; 456 457 /* functions that pass 2 pointers use message format upwr_2pointer_msg 458 */ 459 typedef upwr_2pointer_msg upwr_pwm_switch_msg; 460 typedef upwr_2pointer_msg upwr_pwm_pwron_msg; 461 typedef upwr_2pointer_msg upwr_pwm_pwroff_msg; 462 463 /* Power Management all messages */ 464 typedef union { 465 struct upwr_msg_hdr hdr; /* message header */ 466 upwr_pwm_param_msg param; /* power management parameters */ 467 upwr_pwm_dom_bias_msg dom_bias; /* domain bias message */ 468 upwr_pwm_mem_bias_msg mem_bias; /* memory bias message */ 469 upwr_pwm_pes_seq_msg pes; /* PE seq. message */ 470 upwr_pwm_pmode_cfg_msg pmode; /* power mode config message */ 471 upwr_pwm_regcfg_msg regcfg; /* regulator config message */ 472 upwr_pwm_volt_msg volt; /* set voltage message */ 473 upwr_pwm_freq_msg freq; /* set frequency message */ 474 upwr_pwm_switch_msg switches; /* switch control message */ 475 upwr_pwm_pwron_msg pwron; /* switch/RAM/ROM power on message */ 476 upwr_pwm_pwroff_msg pwroff; /* switch/RAM/ROM power off message */ 477 upwr_pwm_retain_msg retain; /* memory retain message */ 478 upwr_pwm_cfgptr_msg cfgptr; /* configuration pointer message*/ 479 upwr_pwm_dom_pwron_msg dompwron; /* domain power on message */ 480 upwr_pwm_boot_start_msg boot; /* boot start message */ 481 } upwr_pwm_msg; 482 483 typedef union { 484 struct upwr_msg_hdr hdr; /* message header */ 485 upwr_volt_pmic_set_volt_msg set_pmic_volt; /* set pmic voltage message */ 486 upwr_volt_pmic_get_volt_msg get_pmic_volt; /* set pmic voltage message */ 487 upwr_volt_pmic_set_mode_msg set_pmic_mode; /* set pmic mode message */ 488 upwr_volt_pmiccfg_msg pmiccfg; /* PMIC configuration message */ 489 upwr_volt_dom_pmic_rail_msg dom_pmic_rail; /* domain bias message */ 490 upwr_volt_dva_dump_info_msg dva_dump_info; /* dump dva info message */ 491 upwr_volt_dva_req_id_msg dva_req_id; /* dump dva request id array message */ 492 upwr_volt_dva_req_domain_msg dva_req_domain; /* dump dva request domain message */ 493 upwr_volt_dva_req_soc_msg dva_req_soc; /* dump dva request whole soc message */ 494 upwr_volt_pmeter_meas_msg pmeter_meas_msg; /* pmeter measure message */ 495 upwr_volt_vmeter_meas_msg vmeter_meas_msg; /* vmeter measure message */ 496 upwr_volt_pmic_cold_reset_msg cold_reset_msg; /* pmic cold reset message */ 497 } upwr_volt_msg; 498 499 500 typedef union { 501 struct upwr_msg_hdr hdr; 502 struct { 503 uint32_t rsv : UPWR_HEADER_BITS; 504 uint32_t sensor_id : 16U; /* temperature sensor id */ 505 } args; 506 } upwr_temp_get_cur_temp_msg; 507 508 typedef union { 509 struct upwr_msg_hdr hdr; 510 struct { 511 uint32_t rsv : UPWR_HEADER_BITS; 512 uint32_t index : 8U; /* the delay meter index */ 513 uint32_t path : 8U; /* the critical path number */ 514 } args; 515 } upwr_dmeter_get_delay_margin_msg; 516 517 #define MAX_DELAY_MARGIN 63U 518 #define MAX_DELAY_CRITICAL_PATH 7U 519 #define MAX_DELAY_METER_NUM 1U 520 521 typedef union { 522 struct upwr_msg_hdr hdr; 523 struct { 524 uint32_t rsv : UPWR_HEADER_BITS; 525 uint32_t index: 4U; /* the delay meter index */ 526 uint32_t path: 4U; /* the critical path number */ 527 uint32_t dm: 8U; /* the delay margin value of delay meter */ 528 } args; 529 } upwr_dmeter_set_delay_margin_msg; 530 531 #define MAX_PMON_CHAIN_SEL 1U 532 533 typedef union { 534 struct upwr_msg_hdr hdr; 535 struct { 536 uint32_t rsv : UPWR_HEADER_BITS; 537 uint32_t chain_sel : 16U; /* the process monitor delay chain sel */ 538 } args; 539 } upwr_pmon_msg; 540 541 typedef union { 542 struct upwr_msg_hdr hdr; /* message header */ 543 upwr_temp_get_cur_temp_msg get_temp_msg; /* get current temperature message */ 544 } upwr_temp_msg; 545 546 typedef union { 547 struct upwr_msg_hdr hdr; /* message header */ 548 upwr_dmeter_get_delay_margin_msg get_margin_msg; /* get delay margin message */ 549 upwr_dmeter_set_delay_margin_msg set_margin_msg; /* set delay margin message */ 550 upwr_pmon_msg pmon_msg; /* process monitor message */ 551 } upwr_dmeter_msg; 552 553 typedef upwr_down_2w_msg upwr_down_max_msg; /* longest downstream msg */ 554 555 /* 556 * upwr_dom_bias_cfg_t and upwr_mem_bias_cfg_t are SoC-dependent structs, 557 * defined in upower_soc_defs.h 558 */ 559 /* Power and mem switches */ 560 typedef struct { 561 volatile struct upwr_switch_board_t swt_board[UPWR_PMC_SWT_WORDS]; 562 volatile struct upwr_mem_switches_t swt_mem[UPWR_PMC_MEM_WORDS]; 563 } swt_config_t; 564 565 /* ************************************************************************* 566 * Service Group DIAGNOSE - downstream 567 ***************************************************************************/ 568 /* Diagnose Functions */ 569 #define UPWR_DGN_MODE (0U) /* 0 = diagnose mode: upwr_dgn_mode */ 570 #define UPWR_DGN_F_COUNT (1U) 571 #define UPWR_DGN_BUFFER_EN (2U) 572 typedef uint32_t upwr_dgn_f_t; 573 574 #define UPWR_DGN_ALL2ERR (0U) /* record all until an error occurs, freeze recording on error */ 575 #define UPWR_DGN_ALL2HLT (1U) /* record all until an error occurs, halt core on error */ 576 #define UPWR_DGN_ALL (2U) /* trace, warnings, errors, task state recorded */ 577 #define UPWR_DGN_MAX UPWR_DGN_ALL 578 #define UPWR_DGN_TRACE (3U) /* trace, warnings, errors recorded */ 579 #define UPWR_DGN_SRVREQ (4U) /* service request activity recorded */ 580 #define UPWR_DGN_WARN (5U) /* warnings and errors recorded */ 581 #define UPWR_DGN_ERROR (6U) /* only errors recorded */ 582 #define UPWR_DGN_NONE (7U) /* no diagnostic recorded */ 583 #define UPWR_DGN_COUNT (8U) 584 typedef uint32_t upwr_dgn_mode_t; 585 586 typedef upwr_down_1w_msg upwr_dgn_mode_msg; 587 588 typedef union { 589 struct upwr_msg_hdr hdr; 590 upwr_dgn_mode_msg mode_msg; 591 } upwr_dgn_msg; 592 593 typedef struct { 594 struct upwr_msg_hdr hdr; 595 uint32_t buf_addr; 596 } upwr_dgn_v2_msg; 597 598 /* diagnostics log types in the shared RAM log buffer */ 599 600 typedef enum { 601 DGN_LOG_NONE = 0x00000000, 602 DGN_LOG_INFO = 0x10000000, 603 DGN_LOG_ERROR = 0x20000000, 604 DGN_LOG_ASSERT = 0x30000000, 605 DGN_LOG_EXCEPT = 0x40000000, 606 DGN_LOG_EVENT = 0x50000000, // old event trace 607 DGN_LOG_EVENTNEW = 0x60000000, // new event trace 608 DGN_LOG_SERVICE = 0x70000000, 609 DGN_LOG_TASKDEF = 0x80000000, 610 DGN_LOG_TASKEXE = 0x90000000, 611 DGN_LOG_MUTEX = 0xA0000000, 612 DGN_LOG_SEMAPH = 0xB0000000, 613 DGN_LOG_TIMER = 0xC0000000, 614 DGN_LOG_CALLTRACE = 0xD0000000, 615 DGN_LOG_DATA = 0xE0000000, 616 DGN_LOG_PCTRACE = 0xF0000000 617 } upwr_dgn_log_t; 618 619 /* **************************************************************************** 620 * UPSTREAM MESSAGES - RESPONSES 621 * **************************************************************************** 622 */ 623 /* generic ok/ko response message */ 624 #define UPWR_RESP_ERR_BITS (4U) 625 #define UPWR_RESP_HDR_BITS (UPWR_RESP_ERR_BITS+\ 626 UPWR_SRVGROUP_BITS+UPWR_FUNCTION_BITS) 627 #define UPWR_RESP_RET_BITS (32U - UPWR_RESP_HDR_BITS) 628 629 #define UPWR_RESP_OK (0U) /* no error */ 630 #define UPWR_RESP_SG_BUSY (1U) /* service group is busy */ 631 #define UPWR_RESP_SHUTDOWN (2U) /* services not up or shutting down */ 632 #define UPWR_RESP_BAD_REQ (3U) /* invalid request */ 633 #define UPWR_RESP_BAD_STATE (4U) /* system state doesn't allow perform the request */ 634 #define UPWR_RESP_UNINSTALLD (5U) /* service or function not installed */ 635 #define UPWR_RESP_UNINSTALLED (5U) /* service or function not installed (alias) */ 636 #define UPWR_RESP_RESOURCE (6U) /* resource not available */ 637 #define UPWR_RESP_TIMEOUT (7U) /* service timeout */ 638 #define UPWR_RESP_COUNT (8U) 639 640 typedef uint32_t upwr_resp_t; 641 642 struct upwr_resp_hdr { 643 uint32_t errcode : UPWR_RESP_ERR_BITS; 644 uint32_t srvgrp : UPWR_SRVGROUP_BITS; /* service group */ 645 uint32_t function: UPWR_FUNCTION_BITS; 646 uint32_t ret : UPWR_RESP_RET_BITS; /* return value, if any */ 647 }; 648 649 /* generic 1-word upstream message format */ 650 typedef union { 651 struct upwr_resp_hdr hdr; 652 uint32_t word; 653 } upwr_resp_msg; 654 655 /* generic 2-word upstream message format */ 656 typedef struct { 657 struct upwr_resp_hdr hdr; 658 uint32_t word2; /* message second word */ 659 } upwr_up_2w_msg; 660 661 typedef upwr_up_2w_msg upwr_up_max_msg; 662 663 /* ************************************************************************* 664 * Exception/Initialization - upstream 665 ***************************************************************************/ 666 #define UPWR_SOC_BITS (7U) 667 #define UPWR_VMINOR_BITS (4U) 668 #define UPWR_VFIXES_BITS (4U) 669 #define UPWR_VMAJOR_BITS \ 670 (32U - UPWR_HEADER_BITS - UPWR_SOC_BITS - UPWR_VMINOR_BITS - UPWR_VFIXES_BITS) 671 672 typedef struct { 673 uint32_t soc_id; 674 uint32_t vmajor; 675 uint32_t vminor; 676 uint32_t vfixes; 677 } upwr_code_vers_t; 678 679 /* message sent by firmware initialization, received by upwr_init */ 680 typedef union { 681 struct upwr_resp_hdr hdr; 682 struct { 683 uint32_t rsv : UPWR_RESP_HDR_BITS; 684 uint32_t soc : UPWR_SOC_BITS; /* SoC identification */ 685 uint32_t vmajor : UPWR_VMAJOR_BITS; /* firmware major version */ 686 uint32_t vminor : UPWR_VMINOR_BITS; /* firmware minor version */ 687 uint32_t vfixes : UPWR_VFIXES_BITS; /* firmware fixes version */ 688 } args; 689 } upwr_init_msg; 690 691 /* message sent by firmware when the core platform is powered up */ 692 typedef upwr_resp_msg upwr_power_up_msg; 693 694 /* message sent by firmware when the core reset is released for boot */ 695 typedef upwr_resp_msg upwr_boot_up_msg; 696 697 /* message sent by firmware when ready for service requests */ 698 #define UPWR_RAM_VMINOR_BITS (7) 699 #define UPWR_RAM_VFIXES_BITS (6) 700 #define UPWR_RAM_VMAJOR_BITS (32 - UPWR_HEADER_BITS \ 701 - UPWR_RAM_VFIXES_BITS - UPWR_RAM_VMINOR_BITS) 702 typedef union { 703 struct upwr_resp_hdr hdr; 704 struct { 705 uint32_t rsv : UPWR_RESP_HDR_BITS; 706 uint32_t vmajor : UPWR_RAM_VMAJOR_BITS; /* RAM fw major version */ 707 uint32_t vminor : UPWR_RAM_VMINOR_BITS; /* RAM fw minor version */ 708 uint32_t vfixes : UPWR_RAM_VFIXES_BITS; /* RAM fw fixes version */ 709 } args; 710 } upwr_ready_msg; 711 712 /* message sent by firmware when shutdown finishes */ 713 typedef upwr_resp_msg upwr_shutdown_msg; 714 715 typedef union { 716 struct upwr_resp_hdr hdr; 717 upwr_init_msg init; 718 upwr_power_up_msg pwrup; 719 upwr_boot_up_msg booted; 720 upwr_ready_msg ready; 721 } upwr_startup_up_msg; 722 723 /* message sent by firmware for uPower config setting */ 724 typedef upwr_resp_msg upwr_config_resp_msg; 725 726 /* message sent by firmware for uPower alarm */ 727 typedef upwr_resp_msg upwr_alarm_resp_msg; 728 729 /* ************************************************************************* 730 * Power Management - upstream 731 ***************************************************************************/ 732 typedef upwr_resp_msg upwr_param_resp_msg; 733 734 enum work_mode { 735 OVER_DRIVE, 736 NORMAL_DRIVE, 737 LOW_DRIVE 738 }; 739 740 #define UTIMER3_MAX_COUNT 0xFFFFU 741 742 #endif /* UPWR_DEFS_H */ 743