| /aosp_15_r20/external/llvm/test/MC/AArch64/ |
| H A D | arm64-advsimd.s | 1395 usra d0, d0, #1 define
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| /aosp_15_r20/external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2452 __ usra(d28, d27, 37); in GenerateTestSequenceNEON() local
2453 __ usra(v5.V16B(), v22.V16B(), 5); in GenerateTestSequenceNEON() local
2454 __ usra(v2.V2D(), v19.V2D(), 33); in GenerateTestSequenceNEON() local
2455 __ usra(v0.V2S(), v0.V2S(), 21); in GenerateTestSequenceNEON() local
2456 __ usra(v7.V4H(), v6.V4H(), 12); in GenerateTestSequenceNEON() local
2457 __ usra(v4.V4S(), v17.V4S(), 9); in GenerateTestSequenceNEON() local
2458 __ usra(v9.V8B(), v12.V8B(), 7); in GenerateTestSequenceNEON() local
2459 __ usra(v3.V8H(), v27.V8H(), 14); in GenerateTestSequenceNEON() local
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| H A D | test-api-movprfx-aarch64.cc | 2394 __ usra(z0.VnB(), z8.VnB(), 1); in TEST() local
3132 __ usra(z0.VnB(), z8.VnB(), 1); in TEST() local
3566 __ usra(z0.VnB(), z0.VnB(), 1); in TEST() local
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| /aosp_15_r20/external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 5130 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) { in usra() function in vixl::aarch64::Assembler
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| H A D | assembler-sve-aarch64.cc | 9635 void Assembler::usra(const ZRegister& zda, const ZRegister& zn, int shift) { in usra() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1758 LogicVRegister Simulator::usra(VectorFormat vform, in usra() function in vixl::aarch64::Simulator
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| /aosp_15_r20/external/executorch/examples/mediatek/models/llm_models/weights/Llama-3.2-1B-Instruct/ |
| H A D | tokenizer.json | 92956 "usra": 90544, number
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| /aosp_15_r20/external/executorch/examples/mediatek/models/llm_models/weights/Llama-3.2-3B-Instruct/ |
| H A D | tokenizer.json | 92956 "usra": 90544, number
|
| /aosp_15_r20/external/executorch/examples/mediatek/models/llm_models/weights/llama3-8B-instruct/ |
| H A D | tokenizer.json | 92897 "usra": 90544, number
|