1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/irqchip/arm-gic-v3.h>
4 #include <linux/irq.h>
5 #include <linux/irqdomain.h>
6 #include <linux/kstrtox.h>
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9 #include <linux/string_choices.h>
10 #include <kvm/arm_vgic.h>
11 #include <asm/kvm_hyp.h>
12 #include <asm/kvm_mmu.h>
13 #include <asm/kvm_asm.h>
14
15 #include "vgic.h"
16
17 static bool group0_trap;
18 static bool group1_trap;
19 static bool common_trap;
20 static bool dir_trap;
21 static bool gicv4_enable;
22
vgic_v3_set_underflow(struct kvm_vcpu * vcpu)23 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
24 {
25 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
26
27 cpuif->vgic_hcr |= ICH_HCR_UIE;
28 }
29
lr_signals_eoi_mi(u64 lr_val)30 static bool lr_signals_eoi_mi(u64 lr_val)
31 {
32 return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
33 !(lr_val & ICH_LR_HW);
34 }
35
vgic_v3_fold_lr_state(struct kvm_vcpu * vcpu)36 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
37 {
38 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
39 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
40 u32 model = vcpu->kvm->arch.vgic.vgic_model;
41 int lr;
42
43 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
44
45 cpuif->vgic_hcr &= ~ICH_HCR_UIE;
46
47 for (lr = 0; lr < cpuif->used_lrs; lr++) {
48 u64 val = cpuif->vgic_lr[lr];
49 u32 intid, cpuid;
50 struct vgic_irq *irq;
51 bool is_v2_sgi = false;
52 bool deactivated;
53
54 cpuid = val & GICH_LR_PHYSID_CPUID;
55 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
56
57 if (model == KVM_DEV_TYPE_ARM_VGIC_V3) {
58 intid = val & ICH_LR_VIRTUAL_ID_MASK;
59 } else {
60 intid = val & GICH_LR_VIRTUALID;
61 is_v2_sgi = vgic_irq_is_sgi(intid);
62 }
63
64 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
65 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
66 kvm_notify_acked_irq(vcpu->kvm, 0,
67 intid - VGIC_NR_PRIVATE_IRQS);
68
69 irq = vgic_get_vcpu_irq(vcpu, intid);
70 if (!irq) /* An LPI could have been unmapped. */
71 continue;
72
73 raw_spin_lock(&irq->irq_lock);
74
75 /* Always preserve the active bit, note deactivation */
76 deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT);
77 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
78
79 if (irq->active && is_v2_sgi)
80 irq->active_source = cpuid;
81
82 /* Edge is the only case where we preserve the pending bit */
83 if (irq->config == VGIC_CONFIG_EDGE &&
84 (val & ICH_LR_PENDING_BIT)) {
85 irq->pending_latch = true;
86
87 if (is_v2_sgi)
88 irq->source |= (1 << cpuid);
89 }
90
91 /*
92 * Clear soft pending state when level irqs have been acked.
93 */
94 if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
95 irq->pending_latch = false;
96
97 /* Handle resampling for mapped interrupts if required */
98 vgic_irq_handle_resampling(irq, deactivated, val & ICH_LR_PENDING_BIT);
99
100 raw_spin_unlock(&irq->irq_lock);
101 vgic_put_irq(vcpu->kvm, irq);
102 }
103
104 cpuif->used_lrs = 0;
105 }
106
107 /* Requires the irq to be locked already */
vgic_v3_populate_lr(struct kvm_vcpu * vcpu,struct vgic_irq * irq,int lr)108 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
109 {
110 u32 model = vcpu->kvm->arch.vgic.vgic_model;
111 u64 val = irq->intid;
112 bool allow_pending = true, is_v2_sgi;
113
114 is_v2_sgi = (vgic_irq_is_sgi(irq->intid) &&
115 model == KVM_DEV_TYPE_ARM_VGIC_V2);
116
117 if (irq->active) {
118 val |= ICH_LR_ACTIVE_BIT;
119 if (is_v2_sgi)
120 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
121 if (vgic_irq_is_multi_sgi(irq)) {
122 allow_pending = false;
123 val |= ICH_LR_EOI;
124 }
125 }
126
127 if (irq->hw && !vgic_irq_needs_resampling(irq)) {
128 val |= ICH_LR_HW;
129 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
130 /*
131 * Never set pending+active on a HW interrupt, as the
132 * pending state is kept at the physical distributor
133 * level.
134 */
135 if (irq->active)
136 allow_pending = false;
137 } else {
138 if (irq->config == VGIC_CONFIG_LEVEL) {
139 val |= ICH_LR_EOI;
140
141 /*
142 * Software resampling doesn't work very well
143 * if we allow P+A, so let's not do that.
144 */
145 if (irq->active)
146 allow_pending = false;
147 }
148 }
149
150 if (allow_pending && irq_is_pending(irq)) {
151 val |= ICH_LR_PENDING_BIT;
152
153 if (irq->config == VGIC_CONFIG_EDGE)
154 irq->pending_latch = false;
155
156 if (vgic_irq_is_sgi(irq->intid) &&
157 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
158 u32 src = ffs(irq->source);
159
160 if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
161 irq->intid))
162 return;
163
164 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
165 irq->source &= ~(1 << (src - 1));
166 if (irq->source) {
167 irq->pending_latch = true;
168 val |= ICH_LR_EOI;
169 }
170 }
171 }
172
173 /*
174 * Level-triggered mapped IRQs are special because we only observe
175 * rising edges as input to the VGIC. We therefore lower the line
176 * level here, so that we can take new virtual IRQs. See
177 * vgic_v3_fold_lr_state for more info.
178 */
179 if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
180 irq->line_level = false;
181
182 if (irq->group)
183 val |= ICH_LR_GROUP;
184
185 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
186
187 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
188 }
189
vgic_v3_clear_lr(struct kvm_vcpu * vcpu,int lr)190 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
191 {
192 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
193 }
194
vgic_v3_set_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)195 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
196 {
197 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
198 u32 model = vcpu->kvm->arch.vgic.vgic_model;
199 u32 vmcr;
200
201 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
202 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
203 ICH_VMCR_ACK_CTL_MASK;
204 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
205 ICH_VMCR_FIQ_EN_MASK;
206 } else {
207 /*
208 * When emulating GICv3 on GICv3 with SRE=1 on the
209 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
210 */
211 vmcr = ICH_VMCR_FIQ_EN_MASK;
212 }
213
214 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
215 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
216 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
217 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
218 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
219 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
220 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
221
222 cpu_if->vgic_vmcr = vmcr;
223 }
224
vgic_v3_get_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)225 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
226 {
227 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
228 u32 model = vcpu->kvm->arch.vgic.vgic_model;
229 u32 vmcr;
230
231 vmcr = cpu_if->vgic_vmcr;
232
233 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
234 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
235 ICH_VMCR_ACK_CTL_SHIFT;
236 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
237 ICH_VMCR_FIQ_EN_SHIFT;
238 } else {
239 /*
240 * When emulating GICv3 on GICv3 with SRE=1 on the
241 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
242 */
243 vmcrp->fiqen = 1;
244 vmcrp->ackctl = 0;
245 }
246
247 vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
248 vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
249 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
250 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
251 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
252 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
253 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
254 }
255
256 #define INITIAL_PENDBASER_VALUE \
257 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
258 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
259 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
260
vgic_v3_enable(struct kvm_vcpu * vcpu)261 void vgic_v3_enable(struct kvm_vcpu *vcpu)
262 {
263 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
264
265 /*
266 * By forcing VMCR to zero, the GIC will restore the binary
267 * points to their reset values. Anything else resets to zero
268 * anyway.
269 */
270 vgic_v3->vgic_vmcr = 0;
271
272 /*
273 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
274 * way, so we force SRE to 1 to demonstrate this to the guest.
275 * Also, we don't support any form of IRQ/FIQ bypass.
276 * This goes with the spec allowing the value to be RAO/WI.
277 */
278 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
279 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
280 ICC_SRE_EL1_DFB |
281 ICC_SRE_EL1_SRE);
282 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
283 } else {
284 vgic_v3->vgic_sre = 0;
285 }
286
287 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
288 ICH_VTR_ID_BITS_MASK) >>
289 ICH_VTR_ID_BITS_SHIFT;
290 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
291 ICH_VTR_PRI_BITS_MASK) >>
292 ICH_VTR_PRI_BITS_SHIFT) + 1;
293
294 /* Get the show on the road... */
295 vgic_v3->vgic_hcr = ICH_HCR_EN;
296 }
297
vcpu_set_ich_hcr(struct kvm_vcpu * vcpu)298 void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
299 {
300 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
301
302 /* Hide GICv3 sysreg if necessary */
303 if (!kvm_has_gicv3(vcpu->kvm)) {
304 vgic_v3->vgic_hcr |= ICH_HCR_TALL0 | ICH_HCR_TALL1 | ICH_HCR_TC;
305 return;
306 }
307
308 if (group0_trap)
309 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
310 if (group1_trap)
311 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
312 if (common_trap)
313 vgic_v3->vgic_hcr |= ICH_HCR_TC;
314 if (dir_trap)
315 vgic_v3->vgic_hcr |= ICH_HCR_TDIR;
316 }
317
vgic_v3_lpi_sync_pending_status(struct kvm * kvm,struct vgic_irq * irq)318 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
319 {
320 struct kvm_vcpu *vcpu;
321 int byte_offset, bit_nr;
322 gpa_t pendbase, ptr;
323 bool status;
324 u8 val;
325 int ret;
326 unsigned long flags;
327
328 retry:
329 vcpu = irq->target_vcpu;
330 if (!vcpu)
331 return 0;
332
333 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
334
335 byte_offset = irq->intid / BITS_PER_BYTE;
336 bit_nr = irq->intid % BITS_PER_BYTE;
337 ptr = pendbase + byte_offset;
338
339 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
340 if (ret)
341 return ret;
342
343 status = val & (1 << bit_nr);
344
345 raw_spin_lock_irqsave(&irq->irq_lock, flags);
346 if (irq->target_vcpu != vcpu) {
347 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
348 goto retry;
349 }
350 irq->pending_latch = status;
351 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
352
353 if (status) {
354 /* clear consumed data */
355 val &= ~(1 << bit_nr);
356 ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
357 if (ret)
358 return ret;
359 }
360 return 0;
361 }
362
363 /*
364 * The deactivation of the doorbell interrupt will trigger the
365 * unmapping of the associated vPE.
366 */
unmap_all_vpes(struct kvm * kvm)367 static void unmap_all_vpes(struct kvm *kvm)
368 {
369 struct vgic_dist *dist = &kvm->arch.vgic;
370 int i;
371
372 for (i = 0; i < dist->its_vm.nr_vpes; i++)
373 free_irq(dist->its_vm.vpes[i]->irq, kvm_get_vcpu(kvm, i));
374 }
375
map_all_vpes(struct kvm * kvm)376 static void map_all_vpes(struct kvm *kvm)
377 {
378 struct vgic_dist *dist = &kvm->arch.vgic;
379 int i;
380
381 for (i = 0; i < dist->its_vm.nr_vpes; i++)
382 WARN_ON(vgic_v4_request_vpe_irq(kvm_get_vcpu(kvm, i),
383 dist->its_vm.vpes[i]->irq));
384 }
385
386 /*
387 * vgic_v3_save_pending_tables - Save the pending tables into guest RAM
388 * kvm lock and all vcpu lock must be held
389 */
vgic_v3_save_pending_tables(struct kvm * kvm)390 int vgic_v3_save_pending_tables(struct kvm *kvm)
391 {
392 struct vgic_dist *dist = &kvm->arch.vgic;
393 struct vgic_irq *irq;
394 gpa_t last_ptr = ~(gpa_t)0;
395 bool vlpi_avail = false;
396 unsigned long index;
397 int ret = 0;
398 u8 val;
399
400 if (unlikely(!vgic_initialized(kvm)))
401 return -ENXIO;
402
403 /*
404 * A preparation for getting any VLPI states.
405 * The above vgic initialized check also ensures that the allocation
406 * and enabling of the doorbells have already been done.
407 */
408 if (kvm_vgic_global_state.has_gicv4_1) {
409 unmap_all_vpes(kvm);
410 vlpi_avail = true;
411 }
412
413 xa_for_each(&dist->lpi_xa, index, irq) {
414 int byte_offset, bit_nr;
415 struct kvm_vcpu *vcpu;
416 gpa_t pendbase, ptr;
417 bool is_pending;
418 bool stored;
419
420 vcpu = irq->target_vcpu;
421 if (!vcpu)
422 continue;
423
424 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
425
426 byte_offset = irq->intid / BITS_PER_BYTE;
427 bit_nr = irq->intid % BITS_PER_BYTE;
428 ptr = pendbase + byte_offset;
429
430 if (ptr != last_ptr) {
431 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
432 if (ret)
433 goto out;
434 last_ptr = ptr;
435 }
436
437 stored = val & (1U << bit_nr);
438
439 is_pending = irq->pending_latch;
440
441 if (irq->hw && vlpi_avail)
442 vgic_v4_get_vlpi_state(irq, &is_pending);
443
444 if (stored == is_pending)
445 continue;
446
447 if (is_pending)
448 val |= 1 << bit_nr;
449 else
450 val &= ~(1 << bit_nr);
451
452 ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
453 if (ret)
454 goto out;
455 }
456
457 out:
458 if (vlpi_avail)
459 map_all_vpes(kvm);
460
461 return ret;
462 }
463
464 /**
465 * vgic_v3_rdist_overlap - check if a region overlaps with any
466 * existing redistributor region
467 *
468 * @kvm: kvm handle
469 * @base: base of the region
470 * @size: size of region
471 *
472 * Return: true if there is an overlap
473 */
vgic_v3_rdist_overlap(struct kvm * kvm,gpa_t base,size_t size)474 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size)
475 {
476 struct vgic_dist *d = &kvm->arch.vgic;
477 struct vgic_redist_region *rdreg;
478
479 list_for_each_entry(rdreg, &d->rd_regions, list) {
480 if ((base + size > rdreg->base) &&
481 (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg)))
482 return true;
483 }
484 return false;
485 }
486
487 /*
488 * Check for overlapping regions and for regions crossing the end of memory
489 * for base addresses which have already been set.
490 */
vgic_v3_check_base(struct kvm * kvm)491 bool vgic_v3_check_base(struct kvm *kvm)
492 {
493 struct vgic_dist *d = &kvm->arch.vgic;
494 struct vgic_redist_region *rdreg;
495
496 if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
497 d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
498 return false;
499
500 list_for_each_entry(rdreg, &d->rd_regions, list) {
501 size_t sz = vgic_v3_rd_region_size(kvm, rdreg);
502
503 if (vgic_check_iorange(kvm, VGIC_ADDR_UNDEF,
504 rdreg->base, SZ_64K, sz))
505 return false;
506 }
507
508 if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base))
509 return true;
510
511 return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base,
512 KVM_VGIC_V3_DIST_SIZE);
513 }
514
515 /**
516 * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
517 * which has free space to put a new rdist region.
518 *
519 * @rd_regions: redistributor region list head
520 *
521 * A redistributor regions maps n redistributors, n = region size / (2 x 64kB).
522 * Stride between redistributors is 0 and regions are filled in the index order.
523 *
524 * Return: the redist region handle, if any, that has space to map a new rdist
525 * region.
526 */
vgic_v3_rdist_free_slot(struct list_head * rd_regions)527 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions)
528 {
529 struct vgic_redist_region *rdreg;
530
531 list_for_each_entry(rdreg, rd_regions, list) {
532 if (!vgic_v3_redist_region_full(rdreg))
533 return rdreg;
534 }
535 return NULL;
536 }
537
vgic_v3_rdist_region_from_index(struct kvm * kvm,u32 index)538 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
539 u32 index)
540 {
541 struct list_head *rd_regions = &kvm->arch.vgic.rd_regions;
542 struct vgic_redist_region *rdreg;
543
544 list_for_each_entry(rdreg, rd_regions, list) {
545 if (rdreg->index == index)
546 return rdreg;
547 }
548 return NULL;
549 }
550
551
vgic_v3_map_resources(struct kvm * kvm)552 int vgic_v3_map_resources(struct kvm *kvm)
553 {
554 struct vgic_dist *dist = &kvm->arch.vgic;
555 struct kvm_vcpu *vcpu;
556 unsigned long c;
557
558 kvm_for_each_vcpu(c, vcpu, kvm) {
559 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
560
561 if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
562 kvm_debug("vcpu %ld redistributor base not set\n", c);
563 return -ENXIO;
564 }
565 }
566
567 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
568 kvm_debug("Need to set vgic distributor addresses first\n");
569 return -ENXIO;
570 }
571
572 if (!vgic_v3_check_base(kvm)) {
573 kvm_debug("VGIC redist and dist frames overlap\n");
574 return -EINVAL;
575 }
576
577 /*
578 * For a VGICv3 we require the userland to explicitly initialize
579 * the VGIC before we need to use it.
580 */
581 if (!vgic_initialized(kvm)) {
582 return -EBUSY;
583 }
584
585 if (kvm_vgic_global_state.has_gicv4_1)
586 vgic_v4_configure_vsgis(kvm);
587
588 return 0;
589 }
590
591 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
592
early_group0_trap_cfg(char * buf)593 static int __init early_group0_trap_cfg(char *buf)
594 {
595 return kstrtobool(buf, &group0_trap);
596 }
597 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
598
early_group1_trap_cfg(char * buf)599 static int __init early_group1_trap_cfg(char *buf)
600 {
601 return kstrtobool(buf, &group1_trap);
602 }
603 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
604
early_common_trap_cfg(char * buf)605 static int __init early_common_trap_cfg(char *buf)
606 {
607 return kstrtobool(buf, &common_trap);
608 }
609 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
610
early_gicv4_enable(char * buf)611 static int __init early_gicv4_enable(char *buf)
612 {
613 return kstrtobool(buf, &gicv4_enable);
614 }
615 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
616
617 static const struct midr_range broken_seis[] = {
618 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
619 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
620 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
621 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
622 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
623 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
624 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
625 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
626 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
627 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
628 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
629 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
630 {},
631 };
632
vgic_v3_broken_seis(void)633 static bool vgic_v3_broken_seis(void)
634 {
635 return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&
636 is_midr_in_range_list(read_cpuid_id(), broken_seis));
637 }
638
639 /**
640 * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
641 * @info: pointer to the GIC description
642 *
643 * Returns 0 if the VGICv3 has been probed successfully, returns an error code
644 * otherwise
645 */
vgic_v3_probe(const struct gic_kvm_info * info)646 int vgic_v3_probe(const struct gic_kvm_info *info)
647 {
648 u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
649 bool has_v2;
650 int ret;
651
652 has_v2 = ich_vtr_el2 >> 63;
653 ich_vtr_el2 = (u32)ich_vtr_el2;
654
655 /*
656 * The ListRegs field is 5 bits, but there is an architectural
657 * maximum of 16 list registers. Just ignore bit 4...
658 */
659 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
660 kvm_vgic_global_state.can_emulate_gicv2 = false;
661 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
662
663 /* GICv4 support? */
664 if (info->has_v4) {
665 kvm_vgic_global_state.has_gicv4 = gicv4_enable;
666 kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable;
667 kvm_info("GICv4%s support %s\n",
668 kvm_vgic_global_state.has_gicv4_1 ? ".1" : "",
669 str_enabled_disabled(gicv4_enable));
670 }
671
672 kvm_vgic_global_state.vcpu_base = 0;
673
674 if (!info->vcpu.start) {
675 kvm_info("GICv3: no GICV resource entry\n");
676 } else if (!has_v2) {
677 pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
678 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
679 pr_warn("GICV physical address 0x%llx not page aligned\n",
680 (unsigned long long)info->vcpu.start);
681 } else if (kvm_get_mode() != KVM_MODE_PROTECTED) {
682 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
683 kvm_vgic_global_state.can_emulate_gicv2 = true;
684 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
685 if (ret) {
686 kvm_err("Cannot register GICv2 KVM device.\n");
687 return ret;
688 }
689 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
690 }
691 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
692 if (ret) {
693 kvm_err("Cannot register GICv3 KVM device.\n");
694 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
695 return ret;
696 }
697
698 if (kvm_vgic_global_state.vcpu_base == 0)
699 kvm_info("disabling GICv2 emulation\n");
700
701 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
702 group0_trap = true;
703 group1_trap = true;
704 }
705
706 if (vgic_v3_broken_seis()) {
707 kvm_info("GICv3 with broken locally generated SEI\n");
708
709 kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
710 group0_trap = true;
711 group1_trap = true;
712 if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
713 dir_trap = true;
714 else
715 common_trap = true;
716 }
717
718 if (group0_trap || group1_trap || common_trap | dir_trap) {
719 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n",
720 group0_trap ? "G0" : "",
721 group1_trap ? "G1" : "",
722 common_trap ? "C" : "",
723 dir_trap ? "D" : "");
724 static_branch_enable(&vgic_v3_cpuif_trap);
725 }
726
727 kvm_vgic_global_state.vctrl_base = NULL;
728 kvm_vgic_global_state.type = VGIC_V3;
729 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
730
731 return 0;
732 }
733
vgic_v3_load(struct kvm_vcpu * vcpu)734 void vgic_v3_load(struct kvm_vcpu *vcpu)
735 {
736 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
737
738 if (likely(!is_protected_kvm_enabled()))
739 kvm_call_hyp(__vgic_v3_restore_vmcr_aprs, cpu_if);
740
741 if (has_vhe())
742 __vgic_v3_activate_traps(cpu_if);
743
744 WARN_ON(vgic_v4_load(vcpu));
745 }
746
vgic_v3_put(struct kvm_vcpu * vcpu)747 void vgic_v3_put(struct kvm_vcpu *vcpu)
748 {
749 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
750
751 if (likely(!is_protected_kvm_enabled()))
752 kvm_call_hyp(__vgic_v3_save_vmcr_aprs, cpu_if);
753 WARN_ON(vgic_v4_put(vcpu));
754
755 if (has_vhe())
756 __vgic_v3_deactivate_traps(cpu_if);
757 }
758