xref: /aosp_15_r20/external/mesa3d/src/amd/vulkan/radv_physical_device.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2016 Red Hat.
3  * Copyright © 2016 Bas Nieuwenhuizen
4  *
5  * based in part on anv driver which is:
6  * Copyright © 2015 Intel Corporation
7  *
8  * SPDX-License-Identifier: MIT
9  */
10 
11 #ifndef RADV_PHYSICAL_DEVICE_H
12 #define RADV_PHYSICAL_DEVICE_H
13 
14 #include "ac_gpu_info.h"
15 #include "ac_perfcounter.h"
16 
17 #include "radv_instance.h"
18 #include "radv_queue.h"
19 #include "radv_radeon_winsys.h"
20 #include "ac_vcn_enc.h"
21 #include "wsi_common.h"
22 
23 #include "nir.h"
24 
25 #include "vk_physical_device.h"
26 
27 #ifndef _WIN32
28 #include <amdgpu.h>
29 #include <xf86drm.h>
30 #endif
31 
32 /* The "RAW" clocks on Linux are called "FAST" on FreeBSD */
33 #if !defined(CLOCK_MONOTONIC_RAW) && defined(CLOCK_MONOTONIC_FAST)
34 #define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC_FAST
35 #endif
36 
37 struct radv_binning_settings {
38    unsigned context_states_per_bin;    /* allowed range: [1, 6] */
39    unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
40    unsigned fpovs_per_batch;           /* allowed range: [0, 255], 0 = unlimited */
41 };
42 
43 struct radv_physical_device_cache_key {
44    enum radeon_family family;
45    uint32_t ptr_size;
46 
47    uint32_t conformant_trunc_coord : 1;
48    uint32_t clear_lds : 1;
49    uint32_t cs_wave32 : 1;
50    uint32_t disable_aniso_single_level : 1;
51    uint32_t disable_shrink_image_store : 1;
52    uint32_t disable_sinking_load_input_fs : 1;
53    uint32_t dual_color_blend_by_location : 1;
54    uint32_t emulate_rt : 1;
55    uint32_t ge_wave32 : 1;
56    uint32_t invariant_geom : 1;
57    uint32_t lower_discard_to_demote : 1;
58    uint32_t no_fmask : 1;
59    uint32_t no_ngg_gs : 1;
60    uint32_t no_rt : 1;
61    uint32_t ps_wave32 : 1;
62    uint32_t rt_wave64 : 1;
63    uint32_t split_fma : 1;
64    uint32_t ssbo_non_uniform : 1;
65    uint32_t tex_non_uniform : 1;
66    uint32_t use_llvm : 1;
67    uint32_t use_ngg : 1;
68    uint32_t use_ngg_culling : 1;
69 };
70 
71 enum radv_video_enc_hw_ver {
72    RADV_VIDEO_ENC_HW_1_2,
73    RADV_VIDEO_ENC_HW_2,
74    RADV_VIDEO_ENC_HW_3,
75    RADV_VIDEO_ENC_HW_4,
76 };
77 
78 struct radv_physical_device {
79    struct vk_physical_device vk;
80 
81    struct radeon_winsys *ws;
82    struct radeon_info info;
83    char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
84    char marketing_name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
85    uint8_t driver_uuid[VK_UUID_SIZE];
86    uint8_t device_uuid[VK_UUID_SIZE];
87    uint8_t cache_uuid[VK_UUID_SIZE];
88 
89    int local_fd;
90    int master_fd;
91    struct wsi_device wsi_device;
92 
93    /* Whether DCC should be enabled for MSAA textures. */
94    bool dcc_msaa_allowed;
95 
96    /* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */
97    bool use_fmask;
98 
99    /* Whether to enable NGG. */
100    bool use_ngg;
101 
102    /* Whether to enable NGG culling. */
103    bool use_ngg_culling;
104 
105    /* Whether to enable NGG streamout. */
106    bool use_ngg_streamout;
107 
108    /* Whether to emulate the number of primitives generated by GS. */
109    bool emulate_ngg_gs_query_pipeline_stat;
110 
111    /* Whether to use GS_FAST_LAUNCH(2) for mesh shaders. */
112    bool mesh_fast_launch_2;
113 
114    /* Whether to emulate mesh/task shader queries. */
115    bool emulate_mesh_shader_queries;
116 
117    /* Number of threads per wave. */
118    uint8_t ps_wave_size;
119    uint8_t cs_wave_size;
120    uint8_t ge_wave_size;
121    uint8_t rt_wave_size;
122 
123    /* Maximum compute shared memory size. */
124    uint32_t max_shared_size;
125 
126    /* Whether to use the LLVM compiler backend */
127    bool use_llvm;
128 
129    /* Whether to emulate ETC2 image support on HW without support. */
130    bool emulate_etc2;
131 
132    /* Whether to emulate ASTC image support on HW without support. */
133    bool emulate_astc;
134 
135    VkPhysicalDeviceMemoryProperties memory_properties;
136    enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
137    enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
138    unsigned heaps;
139 
140    /* Bitmask of memory types that use the 32-bit address space. */
141    uint32_t memory_types_32bit;
142 
143 #ifndef _WIN32
144    int available_nodes;
145    drmPciBusInfo bus_info;
146 
147    dev_t primary_devid;
148    dev_t render_devid;
149 #endif
150 
151    nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
152 
153    enum radv_queue_family vk_queue_to_radv[RADV_MAX_QUEUE_FAMILIES];
154    uint32_t num_queues;
155 
156    uint32_t gs_table_depth;
157 
158    struct ac_hs_info hs;
159    struct ac_task_info task_info;
160 
161    struct radv_binning_settings binning_settings;
162 
163    /* Performance counters. */
164    struct ac_perfcounters ac_perfcounters;
165 
166    uint32_t num_perfcounters;
167    struct radv_perfcounter_desc *perfcounters;
168 
169    struct {
170       unsigned data0;
171       unsigned data1;
172       unsigned cmd;
173       unsigned cntl;
174    } vid_dec_reg;
175    enum amd_ip_type vid_decode_ip;
176    uint32_t vid_addr_gfx_mode;
177    uint32_t stream_handle_base;
178    uint32_t stream_handle_counter;
179    uint32_t av1_version;
180    rvcn_enc_cmd_t vcn_enc_cmds;
181    enum radv_video_enc_hw_ver enc_hw_ver;
182    uint32_t encoder_interface_version;
183    bool video_encode_enabled;
184    bool video_decode_enabled;
185    struct radv_physical_device_cache_key cache_key;
186 
187    uint32_t tess_distribution_mode;
188 };
189 
190 VK_DEFINE_HANDLE_CASTS(radv_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
191 
192 static inline struct radv_instance *
radv_physical_device_instance(const struct radv_physical_device * pdev)193 radv_physical_device_instance(const struct radv_physical_device *pdev)
194 {
195    return (struct radv_instance *)pdev->vk.instance;
196 }
197 
198 static inline bool
radv_sparse_queue_enabled(const struct radv_physical_device * pdev)199 radv_sparse_queue_enabled(const struct radv_physical_device *pdev)
200 {
201    const struct radv_instance *instance = radv_physical_device_instance(pdev);
202 
203    /* Dedicated sparse queue requires VK_QUEUE_SUBMIT_MODE_THREADED, which is incompatible with
204     * VK_DEVICE_TIMELINE_MODE_EMULATED. */
205    return pdev->info.has_timeline_syncobj && !instance->drirc.legacy_sparse_binding;
206 }
207 
208 static inline bool
radv_has_shader_buffer_float_minmax(const struct radv_physical_device * pdev,unsigned bitsize)209 radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdev, unsigned bitsize)
210 {
211    return (pdev->info.gfx_level <= GFX7 && !pdev->use_llvm) || pdev->info.gfx_level == GFX10 ||
212           pdev->info.gfx_level == GFX10_3 ||
213           ((pdev->info.gfx_level == GFX11 || pdev->info.gfx_level == GFX11_5) && bitsize == 32);
214 }
215 
216 static inline bool
radv_has_pops(const struct radv_physical_device * pdev)217 radv_has_pops(const struct radv_physical_device *pdev)
218 {
219    return pdev->info.gfx_level >= GFX9 && !pdev->use_llvm;
220 }
221 
222 static inline bool
radv_has_uvd(struct radv_physical_device * pdev)223 radv_has_uvd(struct radv_physical_device *pdev)
224 {
225    enum radeon_family family = pdev->info.family;
226    /* Only support UVD on TONGA+ */
227    if (family < CHIP_TONGA)
228       return false;
229    return pdev->info.ip[AMD_IP_UVD].num_queues > 0;
230 }
231 
232 static inline enum radv_queue_family
vk_queue_to_radv(const struct radv_physical_device * pdev,int queue_family_index)233 vk_queue_to_radv(const struct radv_physical_device *pdev, int queue_family_index)
234 {
235    if (queue_family_index == VK_QUEUE_FAMILY_EXTERNAL || queue_family_index == VK_QUEUE_FAMILY_FOREIGN_EXT)
236       return RADV_QUEUE_FOREIGN;
237    if (queue_family_index == VK_QUEUE_FAMILY_IGNORED)
238       return RADV_QUEUE_IGNORED;
239 
240    assert(queue_family_index < RADV_MAX_QUEUE_FAMILIES);
241    return pdev->vk_queue_to_radv[queue_family_index];
242 }
243 
244 /**
245  * Helper used for debugging compiler issues by enabling/disabling LLVM for a
246  * specific shader stage (developers only).
247  */
248 static inline bool
radv_use_llvm_for_stage(const struct radv_physical_device * pdev,UNUSED gl_shader_stage stage)249 radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
250 {
251    return pdev->use_llvm;
252 }
253 
254 bool radv_enable_rt(const struct radv_physical_device *pdev, bool rt_pipelines);
255 
256 bool radv_emulate_rt(const struct radv_physical_device *pdev);
257 
258 uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
259 
260 VkResult create_null_physical_device(struct vk_instance *vk_instance);
261 
262 VkResult create_drm_physical_device(struct vk_instance *vk_instance, struct _drmDevice *device,
263                                     struct vk_physical_device **out);
264 
265 void radv_physical_device_destroy(struct vk_physical_device *vk_pdev);
266 
267 #endif /* RADV_PHYSICAL_DEVICE_H */
268