1 /*
2 * Copyright (c) 2009-2024 Broadcom. All Rights Reserved.
3 * The term “Broadcom” refers to Broadcom Inc.
4 * and/or its subsidiaries.
5 * SPDX-License-Identifier: MIT
6 */
7
8 /**
9 * @file
10 *
11 * Wrappers for DRM ioctl functionlaity used by the rest of the vmw
12 * drm winsys.
13 *
14 * Based on svgaicd_escape.c
15 */
16
17
18 #include "svga_cmd.h"
19 #include "util/u_memory.h"
20 #include "util/u_math.h"
21 #include "svgadump/svga_dump.h"
22 #include "frontend/drm_driver.h"
23 #include "vmw_screen.h"
24 #include "vmw_context.h"
25 #include "vmw_fence.h"
26 #include "xf86drm.h"
27 #include "vmwgfx_drm.h"
28 #include "svga3d_caps.h"
29 #include "svga3d_reg.h"
30
31 #include "util/os_mman.h"
32
33 #include <errno.h>
34 #include <unistd.h>
35
36 #define VMW_MAX_DEFAULT_TEXTURE_SIZE (128 * 1024 * 1024)
37 #define VMW_FENCE_TIMEOUT_SECONDS 3600UL
38
39 #define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
40 #define SVGA3D_FLAGS_UPPER_32(svga3d_flags) (svga3d_flags >> 32)
41 #define SVGA3D_FLAGS_LOWER_32(svga3d_flags) \
42 (svga3d_flags & ((uint64_t)UINT32_MAX))
43
44 struct vmw_region
45 {
46 uint32_t handle;
47 uint64_t map_handle;
48 void *data;
49 uint32_t map_count;
50 int drm_fd;
51 uint32_t size;
52 };
53
54 uint32_t
vmw_region_size(struct vmw_region * region)55 vmw_region_size(struct vmw_region *region)
56 {
57 return region->size;
58 }
59
60 #if defined(__DragonFly__) || defined(__FreeBSD__) || \
61 defined(__NetBSD__) || defined(__OpenBSD__)
62 #define ERESTART EINTR
63 #endif
64
65 uint32
vmw_ioctl_context_create(struct vmw_winsys_screen * vws)66 vmw_ioctl_context_create(struct vmw_winsys_screen *vws)
67 {
68 struct drm_vmw_context_arg c_arg;
69 int ret;
70
71 VMW_FUNC;
72
73 ret = drmCommandRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_CONTEXT,
74 &c_arg, sizeof(c_arg));
75
76 if (ret)
77 return -1;
78
79 vmw_printf("Context id is %d\n", c_arg.cid);
80 return c_arg.cid;
81 }
82
83 uint32
vmw_ioctl_extended_context_create(struct vmw_winsys_screen * vws,bool vgpu10)84 vmw_ioctl_extended_context_create(struct vmw_winsys_screen *vws,
85 bool vgpu10)
86 {
87 union drm_vmw_extended_context_arg c_arg;
88 int ret;
89
90 VMW_FUNC;
91 memset(&c_arg, 0, sizeof(c_arg));
92 c_arg.req = (vgpu10 ? drm_vmw_context_dx : drm_vmw_context_legacy);
93 ret = drmCommandWriteRead(vws->ioctl.drm_fd,
94 DRM_VMW_CREATE_EXTENDED_CONTEXT,
95 &c_arg, sizeof(c_arg));
96
97 if (ret)
98 return -1;
99
100 vmw_printf("Context id is %d\n", c_arg.cid);
101 return c_arg.rep.cid;
102 }
103
104 void
vmw_ioctl_context_destroy(struct vmw_winsys_screen * vws,uint32 cid)105 vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws, uint32 cid)
106 {
107 struct drm_vmw_context_arg c_arg;
108
109 VMW_FUNC;
110
111 memset(&c_arg, 0, sizeof(c_arg));
112 c_arg.cid = cid;
113
114 (void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_CONTEXT,
115 &c_arg, sizeof(c_arg));
116
117 }
118
119 uint32
vmw_ioctl_surface_create(struct vmw_winsys_screen * vws,SVGA3dSurface1Flags flags,SVGA3dSurfaceFormat format,unsigned usage,SVGA3dSize size,uint32_t numFaces,uint32_t numMipLevels,unsigned sampleCount)120 vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
121 SVGA3dSurface1Flags flags,
122 SVGA3dSurfaceFormat format,
123 unsigned usage,
124 SVGA3dSize size,
125 uint32_t numFaces, uint32_t numMipLevels,
126 unsigned sampleCount)
127 {
128 union drm_vmw_surface_create_arg s_arg;
129 struct drm_vmw_surface_create_req *req = &s_arg.req;
130 struct drm_vmw_surface_arg *rep = &s_arg.rep;
131 struct drm_vmw_size sizes[DRM_VMW_MAX_SURFACE_FACES*
132 DRM_VMW_MAX_MIP_LEVELS];
133 struct drm_vmw_size *cur_size;
134 uint32_t iFace;
135 uint32_t iMipLevel;
136 int ret;
137
138 vmw_printf("%s flags %d format %d\n", __func__, flags, format);
139
140 memset(&s_arg, 0, sizeof(s_arg));
141 req->flags = (uint32_t) flags;
142 req->scanout = !!(usage & SVGA_SURFACE_USAGE_SCANOUT);
143 req->format = (uint32_t) format;
144 req->shareable = true;
145
146 assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
147 DRM_VMW_MAX_MIP_LEVELS);
148 cur_size = sizes;
149 for (iFace = 0; iFace < numFaces; ++iFace) {
150 SVGA3dSize mipSize = size;
151
152 req->mip_levels[iFace] = numMipLevels;
153 for (iMipLevel = 0; iMipLevel < numMipLevels; ++iMipLevel) {
154 cur_size->width = mipSize.width;
155 cur_size->height = mipSize.height;
156 cur_size->depth = mipSize.depth;
157 mipSize.width = MAX2(mipSize.width >> 1, 1);
158 mipSize.height = MAX2(mipSize.height >> 1, 1);
159 mipSize.depth = MAX2(mipSize.depth >> 1, 1);
160 cur_size++;
161 }
162 }
163 for (iFace = numFaces; iFace < SVGA3D_MAX_SURFACE_FACES; ++iFace) {
164 req->mip_levels[iFace] = 0;
165 }
166
167 req->size_addr = (unsigned long)&sizes;
168
169 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SURFACE,
170 &s_arg, sizeof(s_arg));
171
172 if (ret)
173 return -1;
174
175 vmw_printf("Surface id is %d\n", rep->sid);
176
177 return rep->sid;
178 }
179
180
181 uint32
vmw_ioctl_gb_surface_create(struct vmw_winsys_screen * vws,SVGA3dSurfaceAllFlags flags,SVGA3dSurfaceFormat format,unsigned usage,SVGA3dSize size,uint32_t numFaces,uint32_t numMipLevels,unsigned sampleCount,uint32_t buffer_handle,SVGA3dMSPattern multisamplePattern,SVGA3dMSQualityLevel qualityLevel,struct vmw_region ** p_region)182 vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
183 SVGA3dSurfaceAllFlags flags,
184 SVGA3dSurfaceFormat format,
185 unsigned usage,
186 SVGA3dSize size,
187 uint32_t numFaces,
188 uint32_t numMipLevels,
189 unsigned sampleCount,
190 uint32_t buffer_handle,
191 SVGA3dMSPattern multisamplePattern,
192 SVGA3dMSQualityLevel qualityLevel,
193 struct vmw_region **p_region)
194 {
195 union {
196 union drm_vmw_gb_surface_create_ext_arg ext_arg;
197 union drm_vmw_gb_surface_create_arg arg;
198 } s_arg;
199 struct drm_vmw_gb_surface_create_rep *rep;
200 struct vmw_region *region = NULL;
201 int ret;
202
203 vmw_printf("%s flags %d format %d\n", __func__, flags, format);
204
205 if (p_region) {
206 region = CALLOC_STRUCT(vmw_region);
207 if (!region)
208 return SVGA3D_INVALID_ID;
209 }
210
211 memset(&s_arg, 0, sizeof(s_arg));
212
213 if (vws->ioctl.have_drm_2_15) {
214 struct drm_vmw_gb_surface_create_ext_req *req = &s_arg.ext_arg.req;
215 rep = &s_arg.ext_arg.rep;
216
217 req->version = drm_vmw_gb_surface_v1;
218 req->multisample_pattern = multisamplePattern;
219 req->quality_level = qualityLevel;
220 req->buffer_byte_stride = 0;
221 req->must_be_zero = 0;
222 req->base.svga3d_flags = SVGA3D_FLAGS_LOWER_32(flags);
223 req->svga3d_flags_upper_32_bits = SVGA3D_FLAGS_UPPER_32(flags);
224 req->base.format = (uint32_t) format;
225
226 if (usage & SVGA_SURFACE_USAGE_SCANOUT)
227 req->base.drm_surface_flags |= drm_vmw_surface_flag_scanout;
228
229 if ((usage & SVGA_SURFACE_USAGE_COHERENT) || vws->force_coherent)
230 req->base.drm_surface_flags |= drm_vmw_surface_flag_coherent;
231
232 req->base.drm_surface_flags |= drm_vmw_surface_flag_shareable;
233 req->base.drm_surface_flags |= drm_vmw_surface_flag_create_buffer;
234 req->base.base_size.width = size.width;
235 req->base.base_size.height = size.height;
236 req->base.base_size.depth = size.depth;
237 req->base.mip_levels = numMipLevels;
238 req->base.multisample_count = 0;
239 req->base.autogen_filter = SVGA3D_TEX_FILTER_NONE;
240
241 if (vws->base.have_vgpu10) {
242 req->base.array_size = numFaces;
243 req->base.multisample_count = sampleCount;
244 } else {
245 assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
246 DRM_VMW_MAX_MIP_LEVELS);
247 req->base.array_size = 0;
248 }
249
250 req->base.buffer_handle = buffer_handle ?
251 buffer_handle : SVGA3D_INVALID_ID;
252
253 ret = drmCommandWriteRead(vws->ioctl.drm_fd,
254 DRM_VMW_GB_SURFACE_CREATE_EXT, &s_arg.ext_arg,
255 sizeof(s_arg.ext_arg));
256
257 if (ret)
258 goto out_fail_create;
259 } else {
260 struct drm_vmw_gb_surface_create_req *req = &s_arg.arg.req;
261 rep = &s_arg.arg.rep;
262
263 req->svga3d_flags = (uint32_t) flags;
264 req->format = (uint32_t) format;
265
266 if (usage & SVGA_SURFACE_USAGE_SCANOUT)
267 req->drm_surface_flags |= drm_vmw_surface_flag_scanout;
268
269 req->drm_surface_flags |= drm_vmw_surface_flag_shareable;
270
271 req->drm_surface_flags |= drm_vmw_surface_flag_create_buffer;
272 req->base_size.width = size.width;
273 req->base_size.height = size.height;
274 req->base_size.depth = size.depth;
275 req->mip_levels = numMipLevels;
276 req->multisample_count = 0;
277 req->autogen_filter = SVGA3D_TEX_FILTER_NONE;
278
279 if (vws->base.have_vgpu10) {
280 req->array_size = numFaces;
281 req->multisample_count = sampleCount;
282 } else {
283 assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
284 DRM_VMW_MAX_MIP_LEVELS);
285 req->array_size = 0;
286 }
287
288 req->buffer_handle = buffer_handle ?
289 buffer_handle : SVGA3D_INVALID_ID;
290
291 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_CREATE,
292 &s_arg.arg, sizeof(s_arg.arg));
293
294 if (ret)
295 goto out_fail_create;
296 }
297
298 if (p_region) {
299 region->handle = rep->buffer_handle;
300 region->map_handle = rep->buffer_map_handle;
301 region->drm_fd = vws->ioctl.drm_fd;
302 region->size = rep->backup_size;
303 *p_region = region;
304 }
305
306 vmw_printf("Surface id is %d\n", rep->sid);
307 return rep->handle;
308
309 out_fail_create:
310 FREE(region);
311 return SVGA3D_INVALID_ID;
312 }
313
314 /**
315 * vmw_ioctl_surface_req - Fill in a struct surface_req
316 *
317 * @vws: Winsys screen
318 * @whandle: Surface handle
319 * @req: The struct surface req to fill in
320 * @needs_unref: This call takes a kernel surface reference that needs to
321 * be unreferenced.
322 *
323 * Returns 0 on success, negative error type otherwise.
324 * Fills in the surface_req structure according to handle type and kernel
325 * capabilities.
326 */
327 static int
vmw_ioctl_surface_req(const struct vmw_winsys_screen * vws,const struct winsys_handle * whandle,struct drm_vmw_surface_arg * req,bool * needs_unref)328 vmw_ioctl_surface_req(const struct vmw_winsys_screen *vws,
329 const struct winsys_handle *whandle,
330 struct drm_vmw_surface_arg *req,
331 bool *needs_unref)
332 {
333 int ret;
334
335 switch(whandle->type) {
336 case WINSYS_HANDLE_TYPE_SHARED:
337 case WINSYS_HANDLE_TYPE_KMS:
338 *needs_unref = false;
339 req->handle_type = DRM_VMW_HANDLE_LEGACY;
340 req->sid = whandle->handle;
341 break;
342 case WINSYS_HANDLE_TYPE_FD:
343 if (!vws->ioctl.have_drm_2_6) {
344 uint32_t handle;
345
346 ret = drmPrimeFDToHandle(vws->ioctl.drm_fd, whandle->handle, &handle);
347 if (ret) {
348 vmw_error("Failed to get handle from prime fd %d.\n",
349 (int) whandle->handle);
350 return -EINVAL;
351 }
352
353 *needs_unref = true;
354 req->handle_type = DRM_VMW_HANDLE_LEGACY;
355 req->sid = handle;
356 } else {
357 *needs_unref = false;
358 req->handle_type = DRM_VMW_HANDLE_PRIME;
359 req->sid = whandle->handle;
360 }
361 break;
362 default:
363 vmw_error("Attempt to import unsupported handle type %d.\n",
364 whandle->type);
365 return -EINVAL;
366 }
367
368 return 0;
369 }
370
371 /**
372 * vmw_ioctl_gb_surface_ref - Put a reference on a guest-backed surface and
373 * get surface information
374 *
375 * @vws: Screen to register the reference on
376 * @handle: Kernel handle of the guest-backed surface
377 * @flags: flags used when the surface was created
378 * @format: Format used when the surface was created
379 * @numMipLevels: Number of mipmap levels of the surface
380 * @p_region: On successful return points to a newly allocated
381 * struct vmw_region holding a reference to the surface backup buffer.
382 *
383 * Returns 0 on success, a system error on failure.
384 */
385 int
vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen * vws,const struct winsys_handle * whandle,SVGA3dSurfaceAllFlags * flags,SVGA3dSurfaceFormat * format,uint32_t * numMipLevels,uint32_t * handle,struct vmw_region ** p_region)386 vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
387 const struct winsys_handle *whandle,
388 SVGA3dSurfaceAllFlags *flags,
389 SVGA3dSurfaceFormat *format,
390 uint32_t *numMipLevels,
391 uint32_t *handle,
392 struct vmw_region **p_region)
393 {
394 struct vmw_region *region = NULL;
395 bool needs_unref = false;
396 int ret;
397
398 assert(p_region != NULL);
399 region = CALLOC_STRUCT(vmw_region);
400 if (!region)
401 return -ENOMEM;
402
403 if (vws->ioctl.have_drm_2_15) {
404 union drm_vmw_gb_surface_reference_ext_arg s_arg;
405 struct drm_vmw_surface_arg *req = &s_arg.req;
406 struct drm_vmw_gb_surface_ref_ext_rep *rep = &s_arg.rep;
407
408 memset(&s_arg, 0, sizeof(s_arg));
409 ret = vmw_ioctl_surface_req(vws, whandle, req, &needs_unref);
410 if (ret)
411 goto out_fail_req;
412
413 *handle = req->sid;
414 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF_EXT,
415 &s_arg, sizeof(s_arg));
416
417 if (ret)
418 goto out_fail_ref;
419
420 region->handle = rep->crep.buffer_handle;
421 region->map_handle = rep->crep.buffer_map_handle;
422 region->drm_fd = vws->ioctl.drm_fd;
423 region->size = rep->crep.backup_size;
424 *p_region = region;
425
426 *handle = rep->crep.handle;
427 *flags = SVGA3D_FLAGS_64(rep->creq.svga3d_flags_upper_32_bits,
428 rep->creq.base.svga3d_flags);
429 *format = rep->creq.base.format;
430 *numMipLevels = rep->creq.base.mip_levels;
431 } else {
432 union drm_vmw_gb_surface_reference_arg s_arg;
433 struct drm_vmw_surface_arg *req = &s_arg.req;
434 struct drm_vmw_gb_surface_ref_rep *rep = &s_arg.rep;
435
436 memset(&s_arg, 0, sizeof(s_arg));
437 ret = vmw_ioctl_surface_req(vws, whandle, req, &needs_unref);
438 if (ret)
439 goto out_fail_req;
440
441 *handle = req->sid;
442 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF,
443 &s_arg, sizeof(s_arg));
444
445 if (ret)
446 goto out_fail_ref;
447
448 region->handle = rep->crep.buffer_handle;
449 region->map_handle = rep->crep.buffer_map_handle;
450 region->drm_fd = vws->ioctl.drm_fd;
451 region->size = rep->crep.backup_size;
452 *p_region = region;
453
454 *handle = rep->crep.handle;
455 *flags = rep->creq.svga3d_flags;
456 *format = rep->creq.format;
457 *numMipLevels = rep->creq.mip_levels;
458 }
459
460 vmw_printf("%s flags %d format %d\n", __func__, *flags, *format);
461
462 if (needs_unref)
463 vmw_ioctl_surface_destroy(vws, *handle);
464
465 return 0;
466 out_fail_ref:
467 if (needs_unref)
468 vmw_ioctl_surface_destroy(vws, *handle);
469 out_fail_req:
470 FREE(region);
471 return ret;
472 }
473
474 void
vmw_ioctl_surface_destroy(struct vmw_winsys_screen * vws,uint32 sid)475 vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws, uint32 sid)
476 {
477 struct drm_vmw_surface_arg s_arg;
478
479 VMW_FUNC;
480
481 memset(&s_arg, 0, sizeof(s_arg));
482 s_arg.sid = sid;
483
484 (void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SURFACE,
485 &s_arg, sizeof(s_arg));
486 }
487
488 void
vmw_ioctl_command(struct vmw_winsys_screen * vws,int32_t cid,uint32_t throttle_us,void * commands,uint32_t size,struct pipe_fence_handle ** pfence,int32_t imported_fence_fd,uint32_t flags)489 vmw_ioctl_command(struct vmw_winsys_screen *vws, int32_t cid,
490 uint32_t throttle_us, void *commands, uint32_t size,
491 struct pipe_fence_handle **pfence, int32_t imported_fence_fd,
492 uint32_t flags)
493 {
494 struct drm_vmw_execbuf_arg arg;
495 struct drm_vmw_fence_rep rep;
496 int ret;
497 int argsize;
498
499 #if MESA_DEBUG
500 {
501 static bool firsttime = true;
502 static bool debug = false;
503 static bool skip = false;
504 if (firsttime) {
505 debug = debug_get_bool_option("SVGA_DUMP_CMD", false);
506 skip = debug_get_bool_option("SVGA_SKIP_CMD", false);
507 }
508 if (debug) {
509 VMW_FUNC;
510 svga_dump_commands(commands, size);
511 }
512 firsttime = false;
513 if (skip) {
514 size = 0;
515 }
516 }
517 #endif
518
519 memset(&arg, 0, sizeof(arg));
520 memset(&rep, 0, sizeof(rep));
521
522 if (flags & SVGA_HINT_FLAG_EXPORT_FENCE_FD) {
523 arg.flags |= DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD;
524 }
525
526 if (imported_fence_fd != -1) {
527 arg.flags |= DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD;
528 }
529
530 rep.error = -EFAULT;
531 if (pfence)
532 arg.fence_rep = (unsigned long)&rep;
533 arg.commands = (unsigned long)commands;
534 arg.command_size = size;
535 arg.throttle_us = throttle_us;
536 arg.version = vws->ioctl.drm_execbuf_version;
537 arg.context_handle = (vws->base.have_vgpu10 ? cid : SVGA3D_INVALID_ID);
538
539 /* Older DRM module requires this to be zero */
540 if (vws->base.have_fence_fd)
541 arg.imported_fence_fd = imported_fence_fd;
542
543 /* In DRM_VMW_EXECBUF_VERSION 1, the drm_vmw_execbuf_arg structure ends with
544 * the flags field. The structure size sent to drmCommandWrite must match
545 * the drm_execbuf_version. Otherwise, an invalid value will be returned.
546 */
547 argsize = vws->ioctl.drm_execbuf_version > 1 ? sizeof(arg) :
548 offsetof(struct drm_vmw_execbuf_arg, context_handle);
549 do {
550 ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_EXECBUF, &arg, argsize);
551 if (ret == -EBUSY)
552 usleep(1000);
553 } while(ret == -ERESTART || ret == -EBUSY);
554 if (ret) {
555 vmw_error("%s error %s.\n", __func__, strerror(-ret));
556 abort();
557 }
558
559 if (rep.error) {
560
561 /*
562 * Kernel has already synced, or caller requested no fence.
563 */
564 if (pfence)
565 *pfence = NULL;
566 } else {
567 if (pfence) {
568 vmw_fences_signal(vws->fence_ops, rep.passed_seqno, rep.seqno,
569 true);
570
571 /* Older DRM module will set this to zero, but -1 is the proper FD
572 * to use for no Fence FD support */
573 if (!vws->base.have_fence_fd)
574 rep.fd = -1;
575
576 *pfence = vmw_fence_create(vws->fence_ops, rep.handle,
577 rep.seqno, rep.mask, rep.fd);
578 if (*pfence == NULL) {
579 /*
580 * Fence creation failed. Need to sync.
581 */
582 (void) vmw_ioctl_fence_finish(vws, rep.handle, rep.mask);
583 vmw_ioctl_fence_unref(vws, rep.handle);
584 }
585 }
586 }
587 }
588
589
590 struct vmw_region *
vmw_ioctl_region_create(struct vmw_winsys_screen * vws,uint32_t size)591 vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size)
592 {
593 struct vmw_region *region;
594 union drm_vmw_alloc_dmabuf_arg arg;
595 struct drm_vmw_alloc_dmabuf_req *req = &arg.req;
596 struct drm_vmw_dmabuf_rep *rep = &arg.rep;
597 int ret;
598
599 vmw_printf("%s: size = %u\n", __func__, size);
600
601 region = CALLOC_STRUCT(vmw_region);
602 if (!region)
603 goto out_err1;
604
605 memset(&arg, 0, sizeof(arg));
606 req->size = size;
607 do {
608 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_ALLOC_DMABUF, &arg,
609 sizeof(arg));
610 } while (ret == -ERESTART);
611
612 if (ret) {
613 vmw_error("IOCTL failed %d: %s\n", ret, strerror(-ret));
614 goto out_err1;
615 }
616
617 region->data = NULL;
618 region->handle = rep->handle;
619 region->map_handle = rep->map_handle;
620 region->map_count = 0;
621 region->size = size;
622 region->drm_fd = vws->ioctl.drm_fd;
623
624 vmw_printf(" gmrId = %u, offset = %u\n",
625 region->ptr.gmrId, region->ptr.offset);
626
627 return region;
628
629 out_err1:
630 FREE(region);
631 return NULL;
632 }
633
634 void
vmw_ioctl_region_destroy(struct vmw_region * region)635 vmw_ioctl_region_destroy(struct vmw_region *region)
636 {
637 struct drm_vmw_unref_dmabuf_arg arg;
638
639 vmw_printf("%s: gmrId = %u, offset = %u\n", __func__,
640 region->ptr.gmrId, region->ptr.offset);
641
642 if (region->data) {
643 os_munmap(region->data, region->size);
644 region->data = NULL;
645 }
646
647 memset(&arg, 0, sizeof(arg));
648 arg.handle = region->handle;
649 drmCommandWrite(region->drm_fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg));
650
651 FREE(region);
652 }
653
654 SVGAGuestPtr
vmw_ioctl_region_ptr(struct vmw_region * region)655 vmw_ioctl_region_ptr(struct vmw_region *region)
656 {
657 SVGAGuestPtr ptr = {region->handle, 0};
658 return ptr;
659 }
660
661 void *
vmw_ioctl_region_map(struct vmw_region * region)662 vmw_ioctl_region_map(struct vmw_region *region)
663 {
664 void *map;
665
666 vmw_printf("%s: gmrId = %u, offset = %u\n", __func__,
667 region->ptr.gmrId, region->ptr.offset);
668
669 if (region->data == NULL) {
670 map = os_mmap(NULL, region->size, PROT_READ | PROT_WRITE, MAP_SHARED,
671 region->drm_fd, region->map_handle);
672 if (map == MAP_FAILED) {
673 vmw_error("%s: Map failed.\n", __func__);
674 return NULL;
675 }
676
677 // MADV_HUGEPAGE only exists on Linux
678 #ifdef MADV_HUGEPAGE
679 (void) madvise(map, region->size, MADV_HUGEPAGE);
680 #endif
681 region->data = map;
682 }
683
684 ++region->map_count;
685
686 return region->data;
687 }
688
689 void
vmw_ioctl_region_unmap(struct vmw_region * region)690 vmw_ioctl_region_unmap(struct vmw_region *region)
691 {
692 vmw_printf("%s: gmrId = %u, offset = %u\n", __func__,
693 region->ptr.gmrId, region->ptr.offset);
694
695 --region->map_count;
696 os_munmap(region->data, region->size);
697 region->data = NULL;
698 }
699
700 /**
701 * vmw_ioctl_syncforcpu - Synchronize a buffer object for CPU usage
702 *
703 * @region: Pointer to a struct vmw_region representing the buffer object.
704 * @dont_block: Dont wait for GPU idle, but rather return -EBUSY if the
705 * GPU is busy with the buffer object.
706 * @readonly: Hint that the CPU access is read-only.
707 * @allow_cs: Allow concurrent command submission while the buffer is
708 * synchronized for CPU. If FALSE command submissions referencing the
709 * buffer will block until a corresponding call to vmw_ioctl_releasefromcpu.
710 *
711 * This function idles any GPU activities touching the buffer and blocks
712 * command submission of commands referencing the buffer, even from
713 * other processes.
714 */
715 int
vmw_ioctl_syncforcpu(struct vmw_region * region,bool dont_block,bool readonly,bool allow_cs)716 vmw_ioctl_syncforcpu(struct vmw_region *region,
717 bool dont_block,
718 bool readonly,
719 bool allow_cs)
720 {
721 struct drm_vmw_synccpu_arg arg;
722 int ret;
723
724 memset(&arg, 0, sizeof(arg));
725 arg.op = drm_vmw_synccpu_grab;
726 arg.handle = region->handle;
727 arg.flags = drm_vmw_synccpu_read;
728 if (!readonly)
729 arg.flags |= drm_vmw_synccpu_write;
730 if (dont_block)
731 arg.flags |= drm_vmw_synccpu_dontblock;
732 if (allow_cs)
733 arg.flags |= drm_vmw_synccpu_allow_cs;
734
735 do {
736 ret = drmCommandWrite(region->drm_fd, DRM_VMW_SYNCCPU, &arg, sizeof(arg));
737 if (ret == -EBUSY)
738 usleep(1000);
739 } while (ret == -ERESTART || ret == -EBUSY);
740
741 if (ret)
742 vmw_error("%s Failed synccpu with error %s.\n", __func__, strerror(-ret));
743
744 return ret;
745 }
746
747 /**
748 * vmw_ioctl_releasefromcpu - Undo a previous syncforcpu.
749 *
750 * @region: Pointer to a struct vmw_region representing the buffer object.
751 * @readonly: Should hold the same value as the matching syncforcpu call.
752 * @allow_cs: Should hold the same value as the matching syncforcpu call.
753 */
754 void
vmw_ioctl_releasefromcpu(struct vmw_region * region,bool readonly,bool allow_cs)755 vmw_ioctl_releasefromcpu(struct vmw_region *region,
756 bool readonly,
757 bool allow_cs)
758 {
759 struct drm_vmw_synccpu_arg arg;
760
761 memset(&arg, 0, sizeof(arg));
762 arg.op = drm_vmw_synccpu_release;
763 arg.handle = region->handle;
764 arg.flags = drm_vmw_synccpu_read;
765 if (!readonly)
766 arg.flags |= drm_vmw_synccpu_write;
767 if (allow_cs)
768 arg.flags |= drm_vmw_synccpu_allow_cs;
769
770 (void) drmCommandWrite(region->drm_fd, DRM_VMW_SYNCCPU, &arg, sizeof(arg));
771 }
772
773 void
vmw_ioctl_fence_unref(struct vmw_winsys_screen * vws,uint32_t handle)774 vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
775 uint32_t handle)
776 {
777 struct drm_vmw_fence_arg arg;
778 int ret;
779
780 memset(&arg, 0, sizeof(arg));
781 arg.handle = handle;
782
783 ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_FENCE_UNREF,
784 &arg, sizeof(arg));
785 if (ret != 0)
786 vmw_error("%s Failed\n", __func__);
787 }
788
789 static inline uint32_t
vmw_drm_fence_flags(uint32_t flags)790 vmw_drm_fence_flags(uint32_t flags)
791 {
792 uint32_t dflags = 0;
793
794 if (flags & SVGA_FENCE_FLAG_EXEC)
795 dflags |= DRM_VMW_FENCE_FLAG_EXEC;
796 if (flags & SVGA_FENCE_FLAG_QUERY)
797 dflags |= DRM_VMW_FENCE_FLAG_QUERY;
798
799 return dflags;
800 }
801
802
803 int
vmw_ioctl_fence_signalled(struct vmw_winsys_screen * vws,uint32_t handle,uint32_t flags)804 vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
805 uint32_t handle,
806 uint32_t flags)
807 {
808 struct drm_vmw_fence_signaled_arg arg;
809 uint32_t vflags = vmw_drm_fence_flags(flags);
810 int ret;
811
812 memset(&arg, 0, sizeof(arg));
813 arg.handle = handle;
814 arg.flags = vflags;
815
816 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_SIGNALED,
817 &arg, sizeof(arg));
818
819 if (ret != 0)
820 return ret;
821
822 vmw_fences_signal(vws->fence_ops, arg.passed_seqno, 0, false);
823
824 return (arg.signaled) ? 0 : -1;
825 }
826
827
828
829 int
vmw_ioctl_fence_finish(struct vmw_winsys_screen * vws,uint32_t handle,uint32_t flags)830 vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
831 uint32_t handle,
832 uint32_t flags)
833 {
834 struct drm_vmw_fence_wait_arg arg;
835 uint32_t vflags = vmw_drm_fence_flags(flags);
836 int ret;
837
838 memset(&arg, 0, sizeof(arg));
839
840 arg.handle = handle;
841 arg.timeout_us = VMW_FENCE_TIMEOUT_SECONDS*1000000;
842 arg.lazy = 0;
843 arg.flags = vflags;
844
845 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_WAIT,
846 &arg, sizeof(arg));
847
848 if (ret != 0)
849 vmw_error("%s Failed\n", __func__);
850
851 return 0;
852 }
853
854 uint32
vmw_ioctl_shader_create(struct vmw_winsys_screen * vws,SVGA3dShaderType type,uint32 code_len)855 vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
856 SVGA3dShaderType type,
857 uint32 code_len)
858 {
859 struct drm_vmw_shader_create_arg sh_arg;
860 int ret;
861
862 VMW_FUNC;
863
864 memset(&sh_arg, 0, sizeof(sh_arg));
865
866 sh_arg.size = code_len;
867 sh_arg.buffer_handle = SVGA3D_INVALID_ID;
868 sh_arg.shader_handle = SVGA3D_INVALID_ID;
869 switch (type) {
870 case SVGA3D_SHADERTYPE_VS:
871 sh_arg.shader_type = drm_vmw_shader_type_vs;
872 break;
873 case SVGA3D_SHADERTYPE_PS:
874 sh_arg.shader_type = drm_vmw_shader_type_ps;
875 break;
876 default:
877 assert(!"Invalid shader type.");
878 break;
879 }
880
881 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SHADER,
882 &sh_arg, sizeof(sh_arg));
883
884 if (ret)
885 return SVGA3D_INVALID_ID;
886
887 return sh_arg.shader_handle;
888 }
889
890 void
vmw_ioctl_shader_destroy(struct vmw_winsys_screen * vws,uint32 shid)891 vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid)
892 {
893 struct drm_vmw_shader_arg sh_arg;
894
895 VMW_FUNC;
896
897 memset(&sh_arg, 0, sizeof(sh_arg));
898 sh_arg.handle = shid;
899
900 (void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SHADER,
901 &sh_arg, sizeof(sh_arg));
902
903 }
904
905 static int
vmw_ioctl_parse_caps(struct vmw_winsys_screen * vws,const uint32_t * cap_buffer)906 vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
907 const uint32_t *cap_buffer)
908 {
909 int i;
910
911 if (vws->base.have_gb_objects) {
912 for (i = 0; i < vws->ioctl.num_cap_3d; ++i) {
913 vws->ioctl.cap_3d[i].has_cap = true;
914 vws->ioctl.cap_3d[i].result.u = cap_buffer[i];
915 }
916 return 0;
917 } else {
918 const uint32 *capsBlock;
919 const SVGA3dCapsRecord *capsRecord = NULL;
920 uint32 offset;
921 const SVGA3dCapPair *capArray;
922 int numCaps, index;
923
924 /*
925 * Search linearly through the caps block records for the specified type.
926 */
927 capsBlock = cap_buffer;
928 for (offset = 0; capsBlock[offset] != 0; offset += capsBlock[offset]) {
929 const SVGA3dCapsRecord *record;
930 assert(offset < SVGA_FIFO_3D_CAPS_SIZE);
931 record = (const SVGA3dCapsRecord *) (capsBlock + offset);
932 if ((record->header.type >= SVGA3DCAPS_RECORD_DEVCAPS_MIN) &&
933 (record->header.type <= SVGA3DCAPS_RECORD_DEVCAPS_MAX) &&
934 (!capsRecord || (record->header.type > capsRecord->header.type))) {
935 capsRecord = record;
936 }
937 }
938
939 if(!capsRecord)
940 return -1;
941
942 /*
943 * Calculate the number of caps from the size of the record.
944 */
945 capArray = (const SVGA3dCapPair *) capsRecord->data;
946 numCaps = (int) ((capsRecord->header.length * sizeof(uint32) -
947 sizeof capsRecord->header) / (2 * sizeof(uint32)));
948
949 for (i = 0; i < numCaps; i++) {
950 index = capArray[i][0];
951 if (index < vws->ioctl.num_cap_3d) {
952 vws->ioctl.cap_3d[index].has_cap = true;
953 vws->ioctl.cap_3d[index].result.u = capArray[i][1];
954 } else {
955 debug_printf("Unknown devcaps seen: %d\n", index);
956 }
957 }
958 }
959 return 0;
960 }
961
962 bool
vmw_ioctl_init(struct vmw_winsys_screen * vws)963 vmw_ioctl_init(struct vmw_winsys_screen *vws)
964 {
965 struct drm_vmw_getparam_arg gp_arg;
966 struct drm_vmw_get_3d_cap_arg cap_arg;
967 unsigned int size;
968 int ret;
969 uint32_t *cap_buffer;
970 drmVersionPtr version;
971 bool drm_gb_capable;
972 bool have_drm_2_5;
973 const char *getenv_val;
974
975 VMW_FUNC;
976
977 version = drmGetVersion(vws->ioctl.drm_fd);
978 if (!version)
979 goto out_no_version;
980
981 have_drm_2_5 = version->version_major > 2 ||
982 (version->version_major == 2 && version->version_minor > 4);
983 vws->ioctl.have_drm_2_6 = version->version_major > 2 ||
984 (version->version_major == 2 && version->version_minor > 5);
985 vws->ioctl.have_drm_2_9 = version->version_major > 2 ||
986 (version->version_major == 2 && version->version_minor > 8);
987 vws->ioctl.have_drm_2_15 = version->version_major > 2 ||
988 (version->version_major == 2 && version->version_minor > 14);
989 vws->ioctl.have_drm_2_16 = version->version_major > 2 ||
990 (version->version_major == 2 && version->version_minor > 15);
991 vws->ioctl.have_drm_2_17 = version->version_major > 2 ||
992 (version->version_major == 2 && version->version_minor > 16);
993 vws->ioctl.have_drm_2_18 = version->version_major > 2 ||
994 (version->version_major == 2 && version->version_minor > 17);
995 vws->ioctl.have_drm_2_19 = version->version_major > 2 ||
996 (version->version_major == 2 && version->version_minor > 18);
997 vws->ioctl.have_drm_2_20 = version->version_major > 2 ||
998 (version->version_major == 2 && version->version_minor > 19);
999
1000 vws->ioctl.drm_execbuf_version = vws->ioctl.have_drm_2_9 ? 2 : 1;
1001
1002 drm_gb_capable = have_drm_2_5;
1003
1004 memset(&gp_arg, 0, sizeof(gp_arg));
1005 gp_arg.param = DRM_VMW_PARAM_3D;
1006 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1007 &gp_arg, sizeof(gp_arg));
1008 if (ret || gp_arg.value == 0) {
1009 vmw_error("No 3D enabled (%i, %s).\n", ret, strerror(-ret));
1010 goto out_no_3d;
1011 }
1012
1013 memset(&gp_arg, 0, sizeof(gp_arg));
1014 gp_arg.param = DRM_VMW_PARAM_FIFO_HW_VERSION;
1015 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1016 &gp_arg, sizeof(gp_arg));
1017 if (ret) {
1018 vmw_error("Failed to get fifo hw version (%i, %s).\n",
1019 ret, strerror(-ret));
1020 goto out_no_3d;
1021 }
1022 vws->ioctl.hwversion = gp_arg.value;
1023 getenv_val = getenv("SVGA_FORCE_HOST_BACKED");
1024 if (!getenv_val || strcmp(getenv_val, "0") == 0) {
1025 memset(&gp_arg, 0, sizeof(gp_arg));
1026 gp_arg.param = DRM_VMW_PARAM_HW_CAPS;
1027 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1028 &gp_arg, sizeof(gp_arg));
1029 } else {
1030 ret = -EINVAL;
1031 }
1032 if (ret)
1033 vws->base.have_gb_objects = false;
1034 else
1035 vws->base.have_gb_objects =
1036 !!(gp_arg.value & (uint64_t) SVGA_CAP_GBOBJECTS);
1037
1038 if (vws->base.have_gb_objects && !drm_gb_capable)
1039 goto out_no_3d;
1040
1041 vws->base.have_vgpu10 = false;
1042 vws->base.have_sm4_1 = false;
1043 vws->base.have_intra_surface_copy = false;
1044
1045 memset(&gp_arg, 0, sizeof(gp_arg));
1046 gp_arg.param = DRM_VMW_PARAM_DEVICE_ID;
1047 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1048 &gp_arg, sizeof(gp_arg));
1049 if (ret || gp_arg.value == 0) {
1050 vws->base.device_id = 0x0405; /* assume SVGA II */
1051 } else {
1052 vws->base.device_id = gp_arg.value;
1053 }
1054
1055 if (vws->base.have_gb_objects) {
1056 memset(&gp_arg, 0, sizeof(gp_arg));
1057 gp_arg.param = DRM_VMW_PARAM_MAX_MOB_MEMORY;
1058 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1059 &gp_arg, sizeof(gp_arg));
1060 if (ret) {
1061 /* Just guess a large enough value. */
1062 vws->ioctl.max_mob_memory = 256*1024*1024;
1063 } else {
1064 vws->ioctl.max_mob_memory = gp_arg.value;
1065 }
1066
1067 memset(&gp_arg, 0, sizeof(gp_arg));
1068 gp_arg.param = DRM_VMW_PARAM_MAX_MOB_SIZE;
1069 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1070 &gp_arg, sizeof(gp_arg));
1071
1072 if (ret || gp_arg.value == 0) {
1073 vws->ioctl.max_texture_size = VMW_MAX_DEFAULT_TEXTURE_SIZE;
1074 } else {
1075 vws->ioctl.max_texture_size = gp_arg.value;
1076 }
1077
1078 /* Never early flush surfaces, mobs do accounting. */
1079 vws->ioctl.max_surface_memory = -1;
1080
1081 if (vws->ioctl.have_drm_2_9) {
1082 memset(&gp_arg, 0, sizeof(gp_arg));
1083 gp_arg.param = DRM_VMW_PARAM_DX;
1084 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1085 &gp_arg, sizeof(gp_arg));
1086 if (ret == 0 && gp_arg.value != 0) {
1087 const char *vgpu10_val;
1088
1089 debug_printf("Have VGPU10 interface and hardware.\n");
1090 vws->base.have_vgpu10 = true;
1091 vgpu10_val = getenv("SVGA_VGPU10");
1092 if (vgpu10_val && strcmp(vgpu10_val, "0") == 0) {
1093 debug_printf("Disabling VGPU10 interface.\n");
1094 vws->base.have_vgpu10 = false;
1095 } else {
1096 debug_printf("Enabling VGPU10 interface.\n");
1097 }
1098 }
1099 }
1100
1101 if (vws->ioctl.have_drm_2_15 && vws->base.have_vgpu10) {
1102 memset(&gp_arg, 0, sizeof(gp_arg));
1103 gp_arg.param = DRM_VMW_PARAM_HW_CAPS2;
1104 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1105 &gp_arg, sizeof(gp_arg));
1106 if (ret == 0 && gp_arg.value != 0) {
1107 vws->base.have_intra_surface_copy = true;
1108 }
1109
1110 memset(&gp_arg, 0, sizeof(gp_arg));
1111 gp_arg.param = DRM_VMW_PARAM_SM4_1;
1112 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1113 &gp_arg, sizeof(gp_arg));
1114 if (ret == 0 && gp_arg.value != 0) {
1115 vws->base.have_sm4_1 = true;
1116 }
1117 }
1118
1119 if (vws->ioctl.have_drm_2_18 && vws->base.have_sm4_1) {
1120 memset(&gp_arg, 0, sizeof(gp_arg));
1121 gp_arg.param = DRM_VMW_PARAM_SM5;
1122 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1123 &gp_arg, sizeof(gp_arg));
1124 if (ret == 0 && gp_arg.value != 0) {
1125 vws->base.have_sm5 = true;
1126 }
1127 }
1128
1129 if (vws->ioctl.have_drm_2_20 && vws->base.have_sm5) {
1130 memset(&gp_arg, 0, sizeof(gp_arg));
1131 gp_arg.param = DRM_VMW_PARAM_GL43;
1132 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1133 &gp_arg, sizeof(gp_arg));
1134 if (ret == 0 && gp_arg.value != 0) {
1135 vws->base.have_gl43 = true;
1136 }
1137 }
1138
1139 memset(&gp_arg, 0, sizeof(gp_arg));
1140 gp_arg.param = DRM_VMW_PARAM_3D_CAPS_SIZE;
1141 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1142 &gp_arg, sizeof(gp_arg));
1143 if (ret)
1144 size = SVGA_FIFO_3D_CAPS_SIZE * sizeof(uint32_t);
1145 else
1146 size = gp_arg.value;
1147
1148 if (vws->base.have_gb_objects)
1149 vws->ioctl.num_cap_3d = size / sizeof(uint32_t);
1150 else
1151 vws->ioctl.num_cap_3d = SVGA3D_DEVCAP_MAX;
1152
1153 if (vws->ioctl.have_drm_2_16) {
1154 vws->base.have_coherent = true;
1155 getenv_val = getenv("SVGA_FORCE_COHERENT");
1156 if (getenv_val && strcmp(getenv_val, "0") != 0)
1157 vws->force_coherent = true;
1158 }
1159 } else {
1160 vws->ioctl.num_cap_3d = SVGA3D_DEVCAP_MAX;
1161
1162 memset(&gp_arg, 0, sizeof(gp_arg));
1163 gp_arg.param = DRM_VMW_PARAM_MAX_SURF_MEMORY;
1164 if (have_drm_2_5)
1165 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
1166 &gp_arg, sizeof(gp_arg));
1167 if (!have_drm_2_5 || ret) {
1168 /* Just guess a large enough value, around 800mb. */
1169 vws->ioctl.max_surface_memory = 0x30000000;
1170 } else {
1171 vws->ioctl.max_surface_memory = gp_arg.value;
1172 }
1173
1174 vws->ioctl.max_texture_size = VMW_MAX_DEFAULT_TEXTURE_SIZE;
1175
1176 size = SVGA_FIFO_3D_CAPS_SIZE * sizeof(uint32_t);
1177 }
1178
1179 debug_printf("VGPU10 interface is %s.\n",
1180 vws->base.have_vgpu10 ? "on" : "off");
1181
1182 cap_buffer = calloc(1, size);
1183 if (!cap_buffer) {
1184 debug_printf("Failed alloc fifo 3D caps buffer.\n");
1185 goto out_no_3d;
1186 }
1187
1188 vws->ioctl.cap_3d = calloc(vws->ioctl.num_cap_3d,
1189 sizeof(*vws->ioctl.cap_3d));
1190 if (!vws->ioctl.cap_3d) {
1191 debug_printf("Failed alloc fifo 3D caps buffer.\n");
1192 goto out_no_caparray;
1193 }
1194
1195 memset(&cap_arg, 0, sizeof(cap_arg));
1196 cap_arg.buffer = (uint64_t) (unsigned long) (cap_buffer);
1197 cap_arg.max_size = size;
1198
1199 /*
1200 * This call must always be after DRM_VMW_PARAM_MAX_MOB_MEMORY and
1201 * DRM_VMW_PARAM_SM4_1. This is because, based on these calls, kernel
1202 * driver sends the supported cap.
1203 */
1204 ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_GET_3D_CAP,
1205 &cap_arg, sizeof(cap_arg));
1206
1207 if (ret) {
1208 debug_printf("Failed to get 3D capabilities"
1209 " (%i, %s).\n", ret, strerror(-ret));
1210 goto out_no_caps;
1211 }
1212
1213 ret = vmw_ioctl_parse_caps(vws, cap_buffer);
1214 if (ret) {
1215 debug_printf("Failed to parse 3D capabilities"
1216 " (%i, %s).\n", ret, strerror(-ret));
1217 goto out_no_caps;
1218 }
1219
1220 if (((version->version_major == 2 && version->version_minor >= 10)
1221 || version->version_major > 2) && vws->base.have_vgpu10) {
1222
1223 /* support for these commands didn't make it into vmwgfx kernel
1224 * modules before 2.10.
1225 */
1226 vws->base.have_generate_mipmap_cmd = true;
1227 vws->base.have_set_predication_cmd = true;
1228 }
1229
1230 if (version->version_major == 2 && version->version_minor >= 14) {
1231 vws->base.have_fence_fd = true;
1232 }
1233
1234 free(cap_buffer);
1235 drmFreeVersion(version);
1236 vmw_printf("%s OK\n", __func__);
1237 return true;
1238 out_no_caps:
1239 free(vws->ioctl.cap_3d);
1240 out_no_caparray:
1241 free(cap_buffer);
1242 out_no_3d:
1243 drmFreeVersion(version);
1244 out_no_version:
1245 vws->ioctl.num_cap_3d = 0;
1246 debug_printf("%s Failed\n", __func__);
1247 return false;
1248 }
1249
1250
1251
1252 void
vmw_ioctl_cleanup(struct vmw_winsys_screen * vws)1253 vmw_ioctl_cleanup(struct vmw_winsys_screen *vws)
1254 {
1255 VMW_FUNC;
1256
1257 free(vws->ioctl.cap_3d);
1258 }
1259