1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #pragma once 26 27 #include <stdbool.h> 28 #include <stdint.h> 29 #include <stddef.h> 30 #include <limits.h> 31 #include "vpe_hw_types.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct vpe; 38 39 #define MAX_NB_POLYPHASE_COEFFS \ 40 (8 * 33) /* currently vpe supports up to 8 taps and 64 phases, only (32+1) phases needed*/ 41 42 enum vpe_status { 43 VPE_STATUS_OK = 1, 44 VPE_STATUS_ERROR, 45 VPE_STATUS_NO_MEMORY, 46 47 // errors for not supported operations 48 VPE_STATUS_NOT_SUPPORTED, 49 VPE_STATUS_INPUT_DCC_NOT_SUPPORTED, 50 VPE_STATUS_OUTPUT_DCC_NOT_SUPPORTED, 51 VPE_STATUS_SWIZZLE_NOT_SUPPORTED, 52 VPE_STATUS_NUM_STREAM_NOT_SUPPORTED, 53 VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED, 54 VPE_STATUS_COLOR_SPACE_VALUE_NOT_SUPPORTED, 55 VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED, 56 VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED, 57 VPE_STATUS_ROTATION_NOT_SUPPORTED, 58 VPE_STATUS_MIRROR_NOT_SUPPORTED, 59 VPE_STATUS_ALPHA_BLENDING_NOT_SUPPORTED, 60 VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED, 61 VPE_STATUS_LUMA_KEYING_NOT_SUPPORTED, 62 VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED, 63 VPE_STATUS_ADJUSTMENT_NOT_SUPPORTED, 64 VPE_STATUS_CMD_OVERFLOW_ERROR, 65 VPE_STATUS_SEGMENT_WIDTH_ERROR, 66 VPE_STATUS_PARAM_CHECK_ERROR, 67 VPE_STATUS_TONE_MAP_NOT_SUPPORTED, 68 VPE_STATUS_BAD_TONE_MAP_PARAMS, 69 VPE_STATUS_BAD_HDR_METADATA, 70 VPE_STATUS_BUFFER_OVERFLOW, 71 VPE_STATUS_BUFFER_UNDERRUN, 72 VPE_STATUS_BG_COLOR_OUT_OF_RANGE, 73 VPE_STATUS_REPEAT_ITEM, 74 VPE_STATUS_PATCH_OVER_MAXSIZE, 75 VPE_STATUS_INVALID_BUFFER_SIZE, 76 VPE_STATUS_SCALER_NOT_SET, 77 VPE_STATUS_GEOMETRICSCALING_ERROR 78 }; 79 80 /** HW IP level */ 81 enum vpe_ip_level { 82 VPE_IP_LEVEL_UNKNOWN = (-1), 83 VPE_IP_LEVEL_1_0, 84 VPE_IP_LEVEL_1_1 85 }; 86 87 /**************************************** 88 * Plane Caps 89 ****************************************/ 90 struct vpe_pixel_format_support { 91 uint32_t argb_packed_32b : 1; 92 uint32_t nv12 : 1; 93 uint32_t fp16 : 1; 94 uint32_t p010 : 1; /**< planar 4:2:0 10-bit */ 95 uint32_t p016 : 1; /**< planar 4:2:0 16-bit */ 96 uint32_t ayuv : 1; /**< packed 4:4:4 */ 97 uint32_t yuy2 : 1; /**< packed 4:2:2 */ 98 }; 99 100 struct vpe_plane_caps { 101 uint32_t per_pixel_alpha : 1; 102 103 struct vpe_pixel_format_support input_pixel_format_support; 104 struct vpe_pixel_format_support output_pixel_format_support; 105 106 /* max upscaling factor x 1000 107 * upscaling factors are always >= 1 108 * e.g. 1080p -> 8K is 4.0 => 4000 109 */ 110 uint32_t max_upscale_factor; 111 112 /* max downscale factor x1000 113 * downscale factors are always <= 1 114 * e.g 8K -> 1080p is 0.25 => 250 115 */ 116 uint32_t max_downscale_factor; 117 118 uint32_t pitch_alignment; /**< alignment in bytes */ 119 uint32_t addr_alignment; /**< alignment in bytes */ 120 uint32_t max_viewport_width; 121 }; 122 123 /************************* 124 * Color management caps 125 *************************/ 126 struct vpe_rom_curve_caps { 127 uint32_t srgb : 1; 128 uint32_t bt2020 : 1; 129 uint32_t gamma2_2 : 1; 130 uint32_t pq : 1; 131 uint32_t hlg : 1; 132 }; 133 134 struct dpp_color_caps { 135 uint32_t pre_csc : 1; 136 uint32_t luma_key : 1; 137 uint32_t dgam_ram : 1; 138 uint32_t post_csc : 1; /**< before gamut remap */ 139 uint32_t gamma_corr : 1; 140 uint32_t hw_3dlut : 1; 141 uint32_t ogam_ram : 1; 142 uint32_t ocsc : 1; 143 struct vpe_rom_curve_caps dgam_rom_caps; 144 }; 145 146 struct mpc_color_caps { 147 uint32_t gamut_remap : 1; 148 uint32_t ogam_ram : 1; 149 uint32_t ocsc : 1; 150 uint32_t shared_3d_lut : 1; /**< can be in either dpp or mpc, but single instance */ 151 uint32_t global_alpha : 1; /**< e.g. top plane 30 %. bottom 70 % */ 152 uint32_t top_bottom_blending : 1; /**< two-layer blending */ 153 }; 154 155 struct vpe_color_caps { 156 struct dpp_color_caps dpp; 157 struct mpc_color_caps mpc; 158 }; 159 160 /************************************************** 161 * VPE Capabilities. 162 * 163 * Those depend on the condition like input format 164 * shall be queried by vpe_cap_funcs 165 **************************************************/ 166 struct vpe_caps { 167 uint32_t max_downscale_ratio; /**< max downscaling ratio in hundred. 168 ratio as src/dest x 100. e.g 600 */ 169 uint64_t lut_size; /**< 3dlut size */ 170 171 uint32_t rotation_support : 1; 172 uint32_t h_mirror_support : 1; 173 uint32_t v_mirror_support : 1; 174 uint32_t is_apu : 1; 175 uint32_t bg_color_check_support : 1; 176 struct { 177 int num_dpp; 178 int num_opp; 179 int num_mpc_3dlut; 180 181 int num_queue; /**< num of hw queue */ 182 } resource_caps; 183 184 struct vpe_color_caps color_caps; 185 struct vpe_plane_caps plane_caps; 186 187 }; 188 189 /*********************************** 190 * Conditional Capabilities 191 ***********************************/ 192 /** DCC CAP */ 193 struct vpe_dcc_surface_param { 194 struct vpe_size surface_size; 195 enum vpe_surface_pixel_format format; 196 enum vpe_swizzle_mode_values swizzle_mode; 197 enum vpe_scan_direction scan; 198 enum vpe_mirror mirror; 199 }; 200 201 struct vpe_dcc_setting { 202 unsigned int max_compressed_blk_size; 203 unsigned int max_uncompressed_blk_size; 204 bool independent_64b_blks; 205 206 struct { 207 uint32_t dcc_256_64_64 : 1; 208 uint32_t dcc_128_128_uncontrained : 1; 209 uint32_t dcc_256_128_128 : 1; 210 uint32_t dcc_256_256_unconstrained : 1; 211 } dcc_controls; 212 }; 213 214 struct vpe_surface_dcc_cap { 215 union { 216 struct { 217 struct vpe_dcc_setting rgb; 218 } grph; 219 220 struct { 221 struct vpe_dcc_setting luma; 222 struct vpe_dcc_setting chroma; 223 } video; 224 }; 225 226 bool capable; 227 bool const_color_support; 228 229 }; 230 231 /** Conditional Capability functions */ 232 struct vpe_cap_funcs { 233 /** 234 * Get DCC support and setting according to the format, 235 * scan direction and swizzle mdoe. 236 * 237 * @param[in] vpe vpe instance 238 * @param[in] input surface and scan properties 239 * @param[in/out] output dcc capable result and related settings 240 * @return true if supported 241 */ 242 bool (*get_dcc_compression_output_cap)(const struct vpe *vpe, const struct vpe_dcc_surface_param *params, struct vpe_surface_dcc_cap *cap); 243 bool (*get_dcc_compression_input_cap)(const struct vpe *vpe, const struct vpe_dcc_surface_param *params, struct vpe_surface_dcc_cap *cap); 244 }; 245 246 /**************************************** 247 * VPE Init Param 248 ****************************************/ 249 /** Log function 250 * @param[in] log_ctx given in the struct vpe_init_params 251 * @param[in] fmt format string 252 */ 253 typedef void (*vpe_log_func_t)(void *log_ctx, const char *fmt, ...); 254 255 /** system memory zalloc, allocated memory initailized with 0 256 * 257 * @param[in] mem_ctx given in the struct vpe_init_params 258 * @param[in] size number of bytes 259 * @return allocated memory 260 */ 261 typedef void *(*vpe_zalloc_func_t)(void *mem_ctx, size_t size); 262 263 /** system memory free 264 * @param[in] mem_ctx given in the struct vpe_init_params 265 * @param[in] ptr number of bytes 266 */ 267 typedef void (*vpe_free_func_t)(void *mem_ctx, void *ptr); 268 269 struct vpe_callback_funcs { 270 void *log_ctx; /**< optional. provided by the caller and pass back to callback */ 271 vpe_log_func_t log; 272 273 void *mem_ctx; /**< optional. provided by the caller and pass back to callback */ 274 vpe_zalloc_func_t zalloc; 275 vpe_free_func_t free; 276 }; 277 278 struct vpe_mem_low_power_enable_options { 279 // override flags 280 struct { 281 uint32_t dscl : 1; 282 uint32_t cm : 1; 283 uint32_t mpc : 1; 284 } flags; 285 286 struct { 287 uint32_t dscl : 1; 288 uint32_t cm : 1; 289 uint32_t mpc : 1; 290 } bits; 291 }; 292 293 enum vpe_expansion_mode { 294 VPE_EXPANSION_MODE_DYNAMIC, 295 VPE_EXPANSION_MODE_ZERO 296 }; 297 298 enum vpe_clamping_range { 299 VPE_CLAMPING_FULL_RANGE = 0, /* No Clamping */ 300 VPE_CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ 301 VPE_CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ 302 VPE_CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ 303 /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ 304 VPE_CLAMPING_LIMITED_RANGE_PROGRAMMABLE 305 }; 306 307 struct vpe_clamping_params { 308 enum vpe_clamping_range clamping_range; 309 uint32_t r_clamp_component_upper; 310 uint32_t b_clamp_component_upper; 311 uint32_t g_clamp_component_upper; 312 uint32_t r_clamp_component_lower; 313 uint32_t b_clamp_component_lower; 314 uint32_t g_clamp_component_lower; 315 }; 316 317 struct vpe_visual_confirm { 318 union { 319 struct { 320 uint32_t input_format : 1; 321 uint32_t output_format : 1; 322 uint32_t reserved : 30; 323 }; 324 uint32_t value; 325 }; 326 }; 327 328 /** configurable params for debugging purpose */ 329 struct vpe_debug_options { 330 // override flags 331 struct { 332 uint32_t cm_in_bypass : 1; 333 uint32_t vpcnvc_bypass : 1; 334 uint32_t mpc_bypass : 1; 335 uint32_t identity_3dlut : 1; 336 uint32_t sce_3dlut : 1; 337 uint32_t disable_reuse_bit : 1; 338 uint32_t bg_color_fill_only : 1; 339 uint32_t assert_when_not_support : 1; 340 uint32_t bypass_gamcor : 1; 341 uint32_t bypass_ogam : 1; 342 uint32_t bypass_dpp_gamut_remap : 1; 343 uint32_t bypass_post_csc : 1; 344 uint32_t bypass_blndgam : 1; 345 uint32_t clamping_setting : 1; 346 uint32_t expansion_mode : 1; 347 uint32_t bypass_per_pixel_alpha : 1; 348 uint32_t dpp_crc_ctrl : 1; 349 uint32_t opp_pipe_crc_ctrl : 1; 350 uint32_t mpc_crc_ctrl : 1; 351 uint32_t bg_bit_depth : 1; 352 uint32_t visual_confirm : 1; 353 uint32_t skip_optimal_tap_check : 1; 354 uint32_t disable_3dlut_cache : 1; 355 } flags; 356 357 // valid only if the corresponding flag is set 358 uint32_t cm_in_bypass : 1; 359 uint32_t vpcnvc_bypass : 1; 360 uint32_t mpc_bypass : 1; 361 uint32_t identity_3dlut : 1; 362 uint32_t sce_3dlut : 1; 363 uint32_t disable_reuse_bit : 1; 364 uint32_t bg_color_fill_only : 1; 365 uint32_t assert_when_not_support : 1; 366 uint32_t bypass_gamcor : 1; 367 uint32_t bypass_ogam : 1; 368 uint32_t bypass_dpp_gamut_remap : 1; 369 uint32_t bypass_post_csc : 1; 370 uint32_t bypass_blndgam : 1; 371 uint32_t clamping_setting : 1; 372 uint32_t bypass_per_pixel_alpha : 1; 373 uint32_t dpp_crc_ctrl : 1; 374 uint32_t opp_pipe_crc_ctrl : 1; 375 uint32_t mpc_crc_ctrl : 1; 376 uint32_t skip_optimal_tap_check : 1; 377 uint32_t disable_3dlut_cache : 1; 378 uint32_t bg_bit_depth; 379 380 struct vpe_mem_low_power_enable_options enable_mem_low_power; 381 enum vpe_expansion_mode expansion_mode; 382 struct vpe_clamping_params clamping_params; 383 struct vpe_visual_confirm visual_confirm_params; 384 }; 385 386 struct vpe_init_data { 387 /** vpe ip info */ 388 uint8_t ver_major; 389 uint8_t ver_minor; 390 uint8_t ver_rev; 391 392 /** function callbacks */ 393 struct vpe_callback_funcs funcs; 394 395 /** debug options */ 396 struct vpe_debug_options debug; 397 }; 398 399 /** VPE instance created through vpelib entry function vpe_create() */ 400 struct vpe { 401 uint32_t version; /**< API version */ 402 enum vpe_ip_level level; /**< HW IP level */ 403 404 struct vpe_caps *caps; /**< general static chip caps */ 405 struct vpe_cap_funcs *cap_funcs; /**< conditional caps */ 406 }; 407 408 /***************************************************** 409 * Structures for build VPE command 410 *****************************************************/ 411 enum vpe_pixel_encoding { 412 VPE_PIXEL_ENCODING_YCbCr, 413 VPE_PIXEL_ENCODING_RGB, 414 VPE_PIXEL_ENCODING_COUNT 415 }; 416 417 enum vpe_color_range { 418 VPE_COLOR_RANGE_FULL, 419 VPE_COLOR_RANGE_STUDIO, 420 VPE_COLOR_RANGE_COUNT 421 }; 422 423 enum vpe_chroma_cositing { 424 VPE_CHROMA_COSITING_NONE, 425 VPE_CHROMA_COSITING_LEFT, 426 VPE_CHROMA_COSITING_TOPLEFT, 427 VPE_CHROMA_COSITING_COUNT 428 }; 429 430 enum vpe_color_primaries { 431 VPE_PRIMARIES_BT601, 432 VPE_PRIMARIES_BT709, 433 VPE_PRIMARIES_BT2020, 434 VPE_PRIMARIES_JFIF, 435 VPE_PRIMARIES_COUNT 436 }; 437 438 enum vpe_transfer_function { 439 VPE_TF_G22, 440 VPE_TF_G24, 441 VPE_TF_G10, 442 VPE_TF_PQ, 443 VPE_TF_PQ_NORMALIZED, 444 VPE_TF_HLG, 445 VPE_TF_SRGB, 446 VPE_TF_BT709, 447 VPE_TF_COUNT 448 }; 449 450 enum vpe_alpha_mode { 451 VPE_ALPHA_OPAQUE, 452 VPE_ALPHA_BGCOLOR 453 }; 454 455 struct vpe_color_space { 456 enum vpe_pixel_encoding encoding; 457 enum vpe_color_range range; 458 enum vpe_transfer_function tf; 459 enum vpe_chroma_cositing cositing; 460 enum vpe_color_primaries primaries; 461 }; 462 463 /* component values are in the range: 0 - 1.0f */ 464 struct vpe_color_rgba { 465 float r; 466 float g; 467 float b; 468 float a; 469 }; 470 471 struct vpe_color_ycbcra { 472 float y; 473 float cb; 474 float cr; 475 float a; 476 }; 477 478 struct vpe_color { 479 bool is_ycbcr; 480 union { 481 struct vpe_color_rgba rgba; 482 struct vpe_color_ycbcra ycbcra; 483 }; 484 }; 485 486 /** 487 * Adjustment Min Max default step 488 * Brightness -100.0f, 100.0f, 0.0f, 0.1f 489 * Contrast 0.0f, 2.0f, 1.0f, 0.01f 490 * Hue -180.0f, 180.0f, 0.0f, 1.0f 491 * Saturation 0.0f, 3.0f, 1.0f, 0.01f 492 * 493 */ 494 struct vpe_color_adjust { 495 float brightness; 496 float contrast; 497 float hue; 498 float saturation; 499 }; 500 501 struct vpe_surface_info { 502 503 /** surface addressing info */ 504 struct vpe_plane_address address; 505 enum vpe_swizzle_mode_values swizzle; 506 507 /** surface properties */ 508 struct vpe_plane_size plane_size; /**< pitch */ 509 struct vpe_plane_dcc_param dcc; 510 enum vpe_surface_pixel_format format; 511 512 struct vpe_color_space cs; 513 }; 514 515 struct vpe_blend_info { 516 bool blending; /**< enable blending */ 517 bool pre_multiplied_alpha; /**< is the pixel value pre-multiplied with alpha */ 518 bool global_alpha; /**< enable global alpha */ 519 float global_alpha_value; /**< global alpha value, should be 0.0~1.0 */ 520 }; 521 522 struct vpe_scaling_info { 523 struct vpe_rect src_rect; 524 struct vpe_rect dst_rect; 525 struct vpe_scaling_taps taps; 526 527 }; 528 struct vpe_scaling_filter_coeffs { 529 530 struct vpe_scaling_taps taps; 531 unsigned int nb_phases; 532 uint16_t horiz_polyphase_coeffs[MAX_NB_POLYPHASE_COEFFS]; /*max nb of taps is 4, max nb of 533 phases 33 = (32+1)*/ 534 uint16_t vert_polyphase_coeffs[MAX_NB_POLYPHASE_COEFFS]; /*max nb of taps is 4, max nb of 535 phases 33 = (32+1)*/ 536 }; 537 538 struct vpe_hdr_metadata { 539 uint16_t redX; 540 uint16_t redY; 541 uint16_t greenX; 542 uint16_t greenY; 543 uint16_t blueX; 544 uint16_t blueY; 545 uint16_t whiteX; 546 uint16_t whiteY; 547 548 uint32_t min_mastering; // luminance in 1/10000 nits 549 uint32_t max_mastering; // luminance in nits 550 uint32_t max_content; 551 uint32_t avg_content; 552 }; 553 554 struct vpe_reserved_param { 555 void *param; 556 uint32_t size; 557 }; 558 559 struct vpe_tonemap_params { 560 uint64_t UID; /* Unique ID for tonemap params */ 561 enum vpe_transfer_function shaper_tf; 562 enum vpe_transfer_function lut_out_tf; 563 enum vpe_color_primaries lut_in_gamut; 564 enum vpe_color_primaries lut_out_gamut; 565 uint16_t input_pq_norm_factor; 566 uint16_t lut_dim; 567 union { 568 uint16_t *lut_data; //CPU accessible 569 void *dma_lut_data; //GPU accessible only for fast load 570 }; 571 bool is_dma_lut; 572 bool enable_3dlut; 573 }; 574 575 struct vpe_stream { 576 struct vpe_surface_info surface_info; 577 struct vpe_scaling_info scaling_info; 578 struct vpe_blend_info blend_info; 579 struct vpe_color_adjust color_adj; 580 struct vpe_tonemap_params tm_params; 581 struct vpe_hdr_metadata hdr_metadata; 582 struct vpe_scaling_filter_coeffs polyphase_scaling_coeffs; 583 enum vpe_rotation_angle rotation; 584 bool horizontal_mirror; 585 bool vertical_mirror; 586 bool use_external_scaling_coeffs; 587 bool enable_luma_key; 588 float lower_luma_bound; 589 float upper_luma_bound; 590 struct vpe_reserved_param reserved_param; 591 592 struct { 593 uint32_t hdr_metadata : 1; 594 uint32_t geometric_scaling : 1; /* support 1 input stream only, 595 * if set, gamut/gamma remapping will be disabled, 596 * blending will be disabled 597 * dst rect must equal to target rect */ 598 uint32_t reserved : 30; 599 } flags; 600 }; 601 602 struct vpe_build_param { 603 /** source */ 604 uint32_t num_streams; 605 struct vpe_stream *streams; 606 607 /** destination */ 608 struct vpe_surface_info dst_surface; 609 struct vpe_rect target_rect; /**< rectangle in target surface to be blt'd. Ranges out of rect 610 won't be touched */ 611 struct vpe_color bg_color; 612 enum vpe_alpha_mode alpha_mode; 613 struct vpe_hdr_metadata hdr_metadata; 614 struct vpe_reserved_param dst_reserved_param; 615 616 // data flags 617 struct { 618 uint32_t hdr_metadata : 1; 619 uint32_t reserved : 31; 620 } flags; 621 622 uint16_t num_instances; 623 bool collaboration_mode; 624 }; 625 626 /** reported through vpe_check_support() 627 * Once the operation is supported, 628 * it returns the required memory for storing 629 * 1. command buffer 630 * 2. embedded buffer 631 * - Pointed by the command buffer content. 632 * - Shall be free'ed together with command buffer once 633 * command is finished. 634 */ 635 struct vpe_bufs_req { 636 uint64_t cmd_buf_size; /**< total command buffer size for all vpe commands */ 637 uint64_t emb_buf_size; /**< total size for storing all embedded data */ 638 }; 639 640 struct vpe_buf { 641 uint64_t gpu_va; /**< GPU start address of the buffer */ 642 uint64_t cpu_va; 643 uint64_t size; 644 bool tmz; /**< allocated from tmz */ 645 }; 646 647 struct vpe_build_bufs { 648 struct vpe_buf cmd_buf; /**< Command buffer. gpu_va is optional */ 649 struct vpe_buf emb_buf; /**< Embedded buffer */ 650 }; 651 652 #ifdef __cplusplus 653 } 654 #endif 655