1 /*
2 * Copyright 2008 Corbin Simpson <[email protected]>
3 * Copyright 2010 Marek Olšák <[email protected]>
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "r300_texture_desc.h"
8 #include "r300_context.h"
9
10 #include "util/format/u_format.h"
11 #include <inttypes.h>
12
13 /* Returns the number of pixels that the texture should be aligned to
14 * in the given dimension. */
r300_get_pixel_alignment(enum pipe_format format,unsigned num_samples,enum radeon_bo_layout microtile,enum radeon_bo_layout macrotile,enum r300_dim dim,bool is_rs690,bool scanout)15 unsigned r300_get_pixel_alignment(enum pipe_format format,
16 unsigned num_samples,
17 enum radeon_bo_layout microtile,
18 enum radeon_bo_layout macrotile,
19 enum r300_dim dim, bool is_rs690,
20 bool scanout)
21 {
22 static const unsigned table[2][5][3][2] =
23 {
24 {
25 /* Macro: linear linear linear
26 Micro: linear tiled square-tiled */
27 {{ 32, 1}, { 8, 4}, { 0, 0}}, /* 8 bits per pixel */
28 {{ 16, 1}, { 8, 2}, { 4, 4}}, /* 16 bits per pixel */
29 {{ 8, 1}, { 4, 2}, { 0, 0}}, /* 32 bits per pixel */
30 {{ 4, 1}, { 2, 2}, { 0, 0}}, /* 64 bits per pixel */
31 {{ 2, 1}, { 0, 0}, { 0, 0}} /* 128 bits per pixel */
32 },
33 {
34 /* Macro: tiled tiled tiled
35 Micro: linear tiled square-tiled */
36 {{256, 8}, {64, 32}, { 0, 0}}, /* 8 bits per pixel */
37 {{128, 8}, {64, 16}, {32, 32}}, /* 16 bits per pixel */
38 {{ 64, 8}, {32, 16}, { 0, 0}}, /* 32 bits per pixel */
39 {{ 32, 8}, {16, 16}, { 0, 0}}, /* 64 bits per pixel */
40 {{ 16, 8}, { 0, 0}, { 0, 0}} /* 128 bits per pixel */
41 }
42 };
43
44 unsigned tile = 0;
45 unsigned pixsize = util_format_get_blocksize(format);
46
47 assert(macrotile <= RADEON_LAYOUT_TILED);
48 assert(microtile <= RADEON_LAYOUT_SQUARETILED);
49 assert(pixsize <= 16);
50 assert(dim <= DIM_HEIGHT);
51
52 tile = table[macrotile][util_logbase2(pixsize)][microtile][dim];
53 if (macrotile == 0 && is_rs690 && dim == DIM_WIDTH) {
54 int align;
55 int h_tile;
56 h_tile = table[macrotile][util_logbase2(pixsize)][microtile][DIM_HEIGHT];
57 align = 64 / (pixsize * h_tile);
58 if (tile < align)
59 tile = align;
60 }
61
62 if (scanout) {
63 if (microtile || macrotile)
64 tile = MAX2(tile, 256 / pixsize);
65 else
66 tile = MAX2(tile, 64);
67 }
68
69 assert(tile);
70 return tile;
71 }
72
73 /* Return true if macrotiling should be enabled on the miplevel. */
r300_texture_macro_switch(struct r300_resource * tex,unsigned level,bool rv350_mode,enum r300_dim dim)74 static bool r300_texture_macro_switch(struct r300_resource *tex,
75 unsigned level,
76 bool rv350_mode,
77 enum r300_dim dim)
78 {
79 unsigned tile, texdim;
80
81 if (tex->b.nr_samples > 1) {
82 return true;
83 }
84
85 tile = r300_get_pixel_alignment(tex->b.format, tex->b.nr_samples,
86 tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0,
87 tex->b.bind & PIPE_BIND_SCANOUT);
88
89 if (dim == DIM_WIDTH) {
90 texdim = u_minify(tex->tex.width0, level);
91 } else {
92 texdim = u_minify(tex->tex.height0, level);
93 }
94
95 /* See TX_FILTER1_n.MACRO_SWITCH. */
96 if (rv350_mode) {
97 return texdim >= tile;
98 } else {
99 return texdim > tile;
100 }
101 }
102
103 /**
104 * Return the stride, in bytes, of the texture image of the given texture
105 * at the given level.
106 */
r300_texture_get_stride(struct r300_screen * screen,struct r300_resource * tex,unsigned level)107 static unsigned r300_texture_get_stride(struct r300_screen *screen,
108 struct r300_resource *tex,
109 unsigned level)
110 {
111 unsigned tile_width, width, stride;
112 bool is_rs690 = (screen->caps.family == CHIP_RS600 ||
113 screen->caps.family == CHIP_RS690 ||
114 screen->caps.family == CHIP_RS740);
115
116 if (tex->tex.stride_in_bytes_override)
117 return tex->tex.stride_in_bytes_override;
118
119 /* Check the level. */
120 if (level > tex->b.last_level) {
121 SCREEN_DBG(screen, DBG_TEX, "%s: level (%u) > last_level (%u)\n",
122 __func__, level, tex->b.last_level);
123 return 0;
124 }
125
126 width = u_minify(tex->tex.width0, level);
127
128 if (util_format_is_plain(tex->b.format)) {
129 /* MSAA and mipmapping are incompatible with scanout. */
130 assert(!(tex->b.bind & PIPE_BIND_SCANOUT) ||
131 (tex->b.last_level == 0 && tex->b.nr_samples <= 1));
132
133 tile_width = r300_get_pixel_alignment(tex->b.format,
134 tex->b.nr_samples,
135 tex->tex.microtile,
136 tex->tex.macrotile[level],
137 DIM_WIDTH, is_rs690,
138 tex->b.bind & PIPE_BIND_SCANOUT);
139 width = align(width, tile_width);
140
141 stride = util_format_get_stride(tex->b.format, width);
142 /* The alignment to 32 bytes is sort of implied by the layout... */
143 return stride;
144 } else {
145 return align(util_format_get_stride(tex->b.format, width), is_rs690 ? 64 : 32);
146 }
147 }
148
r300_texture_get_nblocksy(struct r300_resource * tex,unsigned level,bool * out_aligned_for_cbzb)149 static unsigned r300_texture_get_nblocksy(struct r300_resource *tex,
150 unsigned level,
151 bool *out_aligned_for_cbzb)
152 {
153 unsigned height, tile_height;
154
155 height = u_minify(tex->tex.height0, level);
156
157 /* Mipmapped and 3D textures must have their height aligned to POT. */
158 if ((tex->b.target != PIPE_TEXTURE_1D &&
159 tex->b.target != PIPE_TEXTURE_2D &&
160 tex->b.target != PIPE_TEXTURE_RECT) ||
161 tex->b.last_level != 0) {
162 height = util_next_power_of_two(height);
163 }
164
165 if (util_format_is_plain(tex->b.format)) {
166 tile_height = r300_get_pixel_alignment(tex->b.format,
167 tex->b.nr_samples,
168 tex->tex.microtile,
169 tex->tex.macrotile[level],
170 DIM_HEIGHT, 0,
171 tex->b.bind & PIPE_BIND_SCANOUT);
172 height = align(height, tile_height);
173
174 /* See if the CBZB clear can be used on the buffer,
175 * taking the texture size into account. */
176 if (out_aligned_for_cbzb) {
177 if (tex->tex.macrotile[level]) {
178 /* When clearing, the layer (width*height) is horizontally split
179 * into two, and the upper and lower halves are cleared by the CB
180 * and ZB units, respectively. Therefore, the number of macrotiles
181 * in the Y direction must be even. */
182
183 /* Align the height so that there is an even number of macrotiles.
184 * Do so for 3 or more macrotiles in the Y direction. */
185 if (level == 0 && tex->b.last_level == 0 &&
186 (tex->b.target == PIPE_TEXTURE_1D ||
187 tex->b.target == PIPE_TEXTURE_2D ||
188 tex->b.target == PIPE_TEXTURE_RECT) &&
189 height >= tile_height * 3) {
190 height = align(height, tile_height * 2);
191 }
192
193 *out_aligned_for_cbzb = height % (tile_height * 2) == 0;
194 } else {
195 *out_aligned_for_cbzb = false;
196 }
197 }
198 }
199
200 return util_format_get_nblocksy(tex->b.format, height);
201 }
202
203 /* Get a width in pixels from a stride in bytes. */
r300_stride_to_width(enum pipe_format format,unsigned stride_in_bytes)204 unsigned r300_stride_to_width(enum pipe_format format,
205 unsigned stride_in_bytes)
206 {
207 return (stride_in_bytes / util_format_get_blocksize(format)) *
208 util_format_get_blockwidth(format);
209 }
210
r300_setup_miptree(struct r300_screen * screen,struct r300_resource * tex,bool align_for_cbzb)211 static void r300_setup_miptree(struct r300_screen *screen,
212 struct r300_resource *tex,
213 bool align_for_cbzb)
214 {
215 struct pipe_resource *base = &tex->b;
216 unsigned stride, size, layer_size, nblocksy, i;
217 bool rv350_mode = screen->caps.family >= CHIP_R350;
218 bool aligned_for_cbzb;
219
220 tex->tex.size_in_bytes = 0;
221
222 SCREEN_DBG(screen, DBG_TEXALLOC,
223 "r300: Making miptree for texture, format %s\n",
224 util_format_short_name(base->format));
225
226 for (i = 0; i <= base->last_level; i++) {
227 /* Let's see if this miplevel can be macrotiled. */
228 tex->tex.macrotile[i] =
229 (tex->tex.macrotile[0] == RADEON_LAYOUT_TILED &&
230 r300_texture_macro_switch(tex, i, rv350_mode, DIM_WIDTH) &&
231 r300_texture_macro_switch(tex, i, rv350_mode, DIM_HEIGHT)) ?
232 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
233
234 stride = r300_texture_get_stride(screen, tex, i);
235
236 /* Compute the number of blocks in Y, see if the CBZB clear can be
237 * used on the texture. */
238 aligned_for_cbzb = false;
239 if (align_for_cbzb && tex->tex.cbzb_allowed[i])
240 nblocksy = r300_texture_get_nblocksy(tex, i, &aligned_for_cbzb);
241 else
242 nblocksy = r300_texture_get_nblocksy(tex, i, NULL);
243
244 layer_size = stride * nblocksy;
245
246 if (base->nr_samples > 1) {
247 layer_size *= base->nr_samples;
248 }
249
250 if (base->target == PIPE_TEXTURE_CUBE)
251 size = layer_size * 6;
252 else
253 size = layer_size * u_minify(tex->tex.depth0, i);
254
255 tex->tex.offset_in_bytes[i] = tex->tex.size_in_bytes;
256 tex->tex.size_in_bytes = tex->tex.offset_in_bytes[i] + size;
257 tex->tex.layer_size_in_bytes[i] = layer_size;
258 tex->tex.stride_in_bytes[i] = stride;
259 tex->tex.cbzb_allowed[i] = tex->tex.cbzb_allowed[i] && aligned_for_cbzb;
260
261 if (tex->b.bind & PIPE_BIND_SCANOUT) {
262 assert(i == 0);
263 tex->tex.stride_in_bytes_override = stride;
264 }
265
266 SCREEN_DBG(screen, DBG_TEXALLOC, "r300: Texture miptree: Level %d "
267 "(%dx%dx%d px, pitch %d bytes) %d bytes total, macrotiled %s\n",
268 i, u_minify(tex->tex.width0, i), u_minify(tex->tex.height0, i),
269 u_minify(tex->tex.depth0, i), stride, tex->tex.size_in_bytes,
270 tex->tex.macrotile[i] ? "TRUE" : "FALSE");
271 }
272 }
273
r300_setup_flags(struct r300_resource * tex)274 static void r300_setup_flags(struct r300_resource *tex)
275 {
276 tex->tex.uses_stride_addressing =
277 !util_is_power_of_two_or_zero(tex->b.width0) ||
278 (tex->tex.stride_in_bytes_override &&
279 r300_stride_to_width(tex->b.format,
280 tex->tex.stride_in_bytes_override) != tex->b.width0);
281
282 tex->tex.is_npot =
283 tex->tex.uses_stride_addressing ||
284 !util_is_power_of_two_or_zero(tex->b.height0) ||
285 !util_is_power_of_two_or_zero(tex->b.depth0);
286 }
287
r300_setup_cbzb_flags(struct r300_screen * rscreen,struct r300_resource * tex)288 static void r300_setup_cbzb_flags(struct r300_screen *rscreen,
289 struct r300_resource *tex)
290 {
291 unsigned i, bpp;
292 bool first_level_valid;
293
294 bpp = util_format_get_blocksizebits(tex->b.format);
295
296 /* 1) The texture must be point-sampled,
297 * 2) The depth must be 16 or 32 bits.
298 * 3) If the midpoint ZB offset is not aligned to 2048, it returns garbage
299 * with certain texture sizes. Macrotiling ensures the alignment. */
300 first_level_valid = tex->b.nr_samples <= 1 &&
301 (bpp == 16 || bpp == 32) &&
302 tex->tex.macrotile[0];
303
304 if (SCREEN_DBG_ON(rscreen, DBG_NO_CBZB))
305 first_level_valid = false;
306
307 for (i = 0; i <= tex->b.last_level; i++)
308 tex->tex.cbzb_allowed[i] = first_level_valid && tex->tex.macrotile[i];
309 }
310
r300_pixels_to_dwords(unsigned stride,unsigned height,unsigned xblock,unsigned yblock)311 static unsigned r300_pixels_to_dwords(unsigned stride,
312 unsigned height,
313 unsigned xblock, unsigned yblock)
314 {
315 return (util_align_npot(stride, xblock) * align(height, yblock)) / (xblock * yblock);
316 }
317
r300_setup_hyperz_properties(struct r300_screen * screen,struct r300_resource * tex)318 static void r300_setup_hyperz_properties(struct r300_screen *screen,
319 struct r300_resource *tex)
320 {
321 /* The tile size of 1 DWORD in ZMASK RAM is:
322 *
323 * GPU Pipes 4x4 mode 8x8 mode
324 * ------------------------------------------
325 * R580 4P/1Z 32x32 64x64
326 * RV570 3P/1Z 48x16 96x32
327 * RV530 1P/2Z 32x16 64x32
328 * 1P/1Z 16x16 32x32
329 */
330 static unsigned zmask_blocks_x_per_dw[4] = {4, 8, 12, 8};
331 static unsigned zmask_blocks_y_per_dw[4] = {4, 4, 4, 8};
332
333 /* In HIZ RAM, one dword is always 8x8 pixels (each byte is 4x4 pixels),
334 * but the blocks have very weird ordering.
335 *
336 * With 2 pipes and an image of size 8xY, where Y >= 1,
337 * clearing 4 dwords clears blocks like this:
338 *
339 * 01012323
340 *
341 * where numbers correspond to dword indices. The blocks are interleaved
342 * in the X direction, so the alignment must be 4x1 blocks (32x8 pixels).
343 *
344 * With 4 pipes and an image of size 8xY, where Y >= 4,
345 * clearing 8 dwords clears blocks like this:
346 * 01012323
347 * 45456767
348 * 01012323
349 * 45456767
350 * where numbers correspond to dword indices. The blocks are interleaved
351 * in both directions, so the alignment must be 4x4 blocks (32x32 pixels)
352 */
353 static unsigned hiz_align_x[4] = {8, 32, 48, 32};
354 static unsigned hiz_align_y[4] = {8, 8, 8, 32};
355
356 if (util_format_is_depth_or_stencil(tex->b.format) &&
357 util_format_get_blocksizebits(tex->b.format) == 32 &&
358 tex->tex.microtile) {
359 unsigned i, pipes;
360
361 if (screen->caps.family == CHIP_RV530) {
362 pipes = screen->info.r300_num_z_pipes;
363 } else {
364 pipes = screen->info.r300_num_gb_pipes;
365 }
366
367 for (i = 0; i <= tex->b.last_level; i++) {
368 unsigned zcomp_numdw, zcompsize, hiz_numdw, stride, height;
369
370 stride = r300_stride_to_width(tex->b.format,
371 tex->tex.stride_in_bytes[i]);
372 stride = align(stride, 16);
373 height = u_minify(tex->b.height0, i);
374
375 /* The 8x8 compression mode needs macrotiling. */
376 zcompsize = screen->caps.z_compress == R300_ZCOMP_8X8 &&
377 tex->tex.macrotile[i] &&
378 tex->b.nr_samples <= 1 ? 8 : 4;
379
380 /* Get the ZMASK buffer size in dwords. */
381 zcomp_numdw = r300_pixels_to_dwords(stride, height,
382 zmask_blocks_x_per_dw[pipes-1] * zcompsize,
383 zmask_blocks_y_per_dw[pipes-1] * zcompsize);
384
385 /* Check whether we have enough ZMASK memory. */
386 if (util_format_get_blocksizebits(tex->b.format) == 32 &&
387 zcomp_numdw <= screen->caps.zmask_ram * pipes) {
388 tex->tex.zmask_dwords[i] = zcomp_numdw;
389 tex->tex.zcomp8x8[i] = zcompsize == 8;
390
391 tex->tex.zmask_stride_in_pixels[i] =
392 util_align_npot(stride, zmask_blocks_x_per_dw[pipes-1] * zcompsize);
393 } else {
394 tex->tex.zmask_dwords[i] = 0;
395 tex->tex.zcomp8x8[i] = false;
396 tex->tex.zmask_stride_in_pixels[i] = 0;
397 }
398
399 /* Now setup HIZ. */
400 stride = util_align_npot(stride, hiz_align_x[pipes-1]);
401 height = align(height, hiz_align_y[pipes-1]);
402
403 /* Get the HIZ buffer size in dwords. */
404 hiz_numdw = (stride * height) / (8*8 * pipes);
405
406 /* Check whether we have enough HIZ memory. */
407 if (hiz_numdw <= screen->caps.hiz_ram * pipes) {
408 tex->tex.hiz_dwords[i] = hiz_numdw;
409 tex->tex.hiz_stride_in_pixels[i] = stride;
410 } else {
411 tex->tex.hiz_dwords[i] = 0;
412 tex->tex.hiz_stride_in_pixels[i] = 0;
413 }
414 }
415 }
416 }
417
r300_setup_cmask_properties(struct r300_screen * screen,struct r300_resource * tex)418 static void r300_setup_cmask_properties(struct r300_screen *screen,
419 struct r300_resource *tex)
420 {
421 static unsigned cmask_align_x[4] = {16, 32, 48, 32};
422 static unsigned cmask_align_y[4] = {16, 16, 16, 32};
423 unsigned pipes, stride, cmask_num_dw, cmask_max_size;
424
425 if (!screen->caps.has_cmask) {
426 return;
427 }
428
429 /* We need an AA colorbuffer, no mipmaps. */
430 if (tex->b.nr_samples <= 1 ||
431 tex->b.last_level > 0 ||
432 util_format_is_depth_or_stencil(tex->b.format)) {
433 return;
434 }
435
436 /* FP16 AA needs R500 and a fairly new DRM. */
437 if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
438 tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
439 !screen->caps.is_r500) {
440 return;
441 }
442
443 if (SCREEN_DBG_ON(screen, DBG_NO_CMASK)) {
444 return;
445 }
446
447 /* CMASK is part of raster pipes. The number of Z pipes doesn't matter. */
448 pipes = screen->info.r300_num_gb_pipes;
449
450 /* The single-pipe cards have 5120 dwords of CMASK RAM,
451 * the other cards have 4096 dwords of CMASK RAM per pipe. */
452 cmask_max_size = pipes == 1 ? 5120 : pipes * 4096;
453
454 stride = r300_stride_to_width(tex->b.format,
455 tex->tex.stride_in_bytes[0]);
456 stride = align(stride, 16);
457
458 /* Get the CMASK size in dwords. */
459 cmask_num_dw = r300_pixels_to_dwords(stride, tex->b.height0,
460 cmask_align_x[pipes-1],
461 cmask_align_y[pipes-1]);
462
463 /* Check the CMASK size against the CMASK memory limit. */
464 if (cmask_num_dw <= cmask_max_size) {
465 tex->tex.cmask_dwords = cmask_num_dw;
466 tex->tex.cmask_stride_in_pixels =
467 util_align_npot(stride, cmask_align_x[pipes-1]);
468 }
469 }
470
r300_setup_tiling(struct r300_screen * screen,struct r300_resource * tex)471 static void r300_setup_tiling(struct r300_screen *screen,
472 struct r300_resource *tex)
473 {
474 enum pipe_format format = tex->b.format;
475 bool rv350_mode = screen->caps.family >= CHIP_R350;
476 bool is_zb = util_format_is_depth_or_stencil(format);
477 bool dbg_no_tiling = SCREEN_DBG_ON(screen, DBG_NO_TILING);
478 bool force_microtiling =
479 (tex->b.flags & R300_RESOURCE_FORCE_MICROTILING) != 0;
480
481 if (tex->b.nr_samples > 1) {
482 tex->tex.microtile = RADEON_LAYOUT_TILED;
483 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED;
484 return;
485 }
486
487 tex->tex.microtile = RADEON_LAYOUT_LINEAR;
488 tex->tex.macrotile[0] = RADEON_LAYOUT_LINEAR;
489
490 if (tex->b.usage == PIPE_USAGE_STAGING) {
491 return;
492 }
493
494 if (!util_format_is_plain(format)) {
495 return;
496 }
497
498 /* If height == 1, disable microtiling except for zbuffer. */
499 if (!force_microtiling && !is_zb &&
500 (tex->b.height0 == 1 || dbg_no_tiling)) {
501 return;
502 }
503
504 /* Set microtiling. */
505 switch (util_format_get_blocksize(format)) {
506 case 1:
507 case 4:
508 case 8:
509 tex->tex.microtile = RADEON_LAYOUT_TILED;
510 break;
511
512 case 2:
513 tex->tex.microtile =
514 tex->b.bind & PIPE_BIND_SCANOUT ?
515 RADEON_LAYOUT_TILED : RADEON_LAYOUT_SQUARETILED;
516 break;
517 }
518
519 if (dbg_no_tiling) {
520 return;
521 }
522
523 /* Set macrotiling. */
524 if (r300_texture_macro_switch(tex, 0, rv350_mode, DIM_WIDTH) &&
525 r300_texture_macro_switch(tex, 0, rv350_mode, DIM_HEIGHT)) {
526 tex->tex.macrotile[0] = RADEON_LAYOUT_TILED;
527 }
528 }
529
r300_tex_print_info(struct r300_resource * tex,const char * func)530 static void r300_tex_print_info(struct r300_resource *tex,
531 const char *func)
532 {
533 fprintf(stderr,
534 "r300: %s: Macro: %s, Micro: %s, Pitch: %i, Dim: %ix%ix%i, "
535 "LastLevel: %i, Size: %i, Format: %s, Samples: %i\n",
536 func,
537 tex->tex.macrotile[0] ? "YES" : " NO",
538 tex->tex.microtile ? "YES" : " NO",
539 r300_stride_to_width(tex->b.format, tex->tex.stride_in_bytes[0]),
540 tex->b.width0, tex->b.height0, tex->b.depth0,
541 tex->b.last_level, tex->tex.size_in_bytes,
542 util_format_short_name(tex->b.format),
543 tex->b.nr_samples);
544 }
545
r300_texture_desc_init(struct r300_screen * rscreen,struct r300_resource * tex,const struct pipe_resource * base)546 void r300_texture_desc_init(struct r300_screen *rscreen,
547 struct r300_resource *tex,
548 const struct pipe_resource *base)
549 {
550 tex->b.target = base->target;
551 tex->b.format = base->format;
552 tex->b.width0 = base->width0;
553 tex->b.height0 = base->height0;
554 tex->b.depth0 = base->depth0;
555 tex->b.array_size = base->array_size;
556 tex->b.last_level = base->last_level;
557 tex->b.nr_samples = base->nr_samples;
558 tex->tex.width0 = base->width0;
559 tex->tex.height0 = base->height0;
560 tex->tex.depth0 = base->depth0;
561
562 /* There is a CB memory addressing hardware bug that limits the width
563 * of the MSAA buffer in some cases in R520. In order to get around it,
564 * the following code lowers the sample count depending on the format and
565 * the width.
566 *
567 * The only catch is that all MSAA colorbuffers and a zbuffer which are
568 * supposed to be used together should always be bound together. Only
569 * then the correct minimum sample count of all bound buffers is used
570 * for rendering. */
571 if (rscreen->caps.is_r500) {
572 /* FP16 6x MSAA buffers are limited to a width of 1360 pixels. */
573 if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
574 tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
575 tex->b.nr_samples == 6 && tex->b.width0 > 1360) {
576 tex->b.nr_samples = 4;
577 }
578
579 /* FP16 4x MSAA buffers are limited to a width of 2048 pixels. */
580 if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
581 tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
582 tex->b.nr_samples == 4 && tex->b.width0 > 2048) {
583 tex->b.nr_samples = 2;
584 }
585 }
586
587 /* 32-bit 6x MSAA buffers are limited to a width of 2720 pixels.
588 * This applies to all R300-R500 cards. */
589 if (util_format_get_blocksizebits(tex->b.format) == 32 &&
590 !util_format_is_depth_or_stencil(tex->b.format) &&
591 tex->b.nr_samples == 6 && tex->b.width0 > 2720) {
592 tex->b.nr_samples = 4;
593 }
594
595 r300_setup_flags(tex);
596
597 /* Align a 3D NPOT texture to POT. */
598 if (base->target == PIPE_TEXTURE_3D && tex->tex.is_npot) {
599 tex->tex.width0 = util_next_power_of_two(tex->tex.width0);
600 tex->tex.height0 = util_next_power_of_two(tex->tex.height0);
601 tex->tex.depth0 = util_next_power_of_two(tex->tex.depth0);
602 }
603
604 /* Setup tiling. */
605 if (tex->tex.microtile == RADEON_LAYOUT_UNKNOWN) {
606 r300_setup_tiling(rscreen, tex);
607 }
608
609 r300_setup_cbzb_flags(rscreen, tex);
610
611 /* Setup the miptree description. */
612 r300_setup_miptree(rscreen, tex, true);
613 /* If the required buffer size is larger than the given max size,
614 * try again without the alignment for the CBZB clear. */
615 if (tex->buf && tex->tex.size_in_bytes > tex->buf->size) {
616 r300_setup_miptree(rscreen, tex, false);
617
618 /* Make sure the buffer we got is large enough. */
619 if (tex->tex.size_in_bytes > tex->buf->size) {
620 fprintf(stderr,
621 "r300: I got a pre-allocated buffer to use it as a texture "
622 "storage, but the buffer is too small. I'll use the buffer "
623 "anyway, because I can't crash here, but it's dangerous. "
624 "This can be a DDX bug. Got: %"PRIu64"B, Need: %uB, Info:\n",
625 tex->buf->size, tex->tex.size_in_bytes);
626 r300_tex_print_info(tex, "texture_desc_init");
627 /* Oops, what now. Apps will break if we fail this,
628 * so just pretend everything's okay. */
629 }
630 }
631
632 r300_setup_hyperz_properties(rscreen, tex);
633 r300_setup_cmask_properties(rscreen, tex);
634
635 if (SCREEN_DBG_ON(rscreen, DBG_TEX))
636 r300_tex_print_info(tex, "texture_desc_init");
637 }
638
r300_texture_get_offset(struct r300_resource * tex,unsigned level,unsigned layer)639 unsigned r300_texture_get_offset(struct r300_resource *tex,
640 unsigned level, unsigned layer)
641 {
642 unsigned offset = tex->tex.offset_in_bytes[level];
643
644 switch (tex->b.target) {
645 case PIPE_TEXTURE_3D:
646 case PIPE_TEXTURE_CUBE:
647 return offset + layer * tex->tex.layer_size_in_bytes[level];
648
649 default:
650 assert(layer == 0);
651 return offset;
652 }
653 }
654