1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11 #include <linux/fault-inject.h>
12
13 #include <generated/xe_wa_oob.h>
14
15 #include "regs/xe_engine_regs.h"
16 #include "regs/xe_gt_regs.h"
17 #include "regs/xe_regs.h"
18 #include "xe_device_types.h"
19 #include "xe_force_wake.h"
20 #include "xe_gt.h"
21 #include "xe_hw_engine_types.h"
22 #include "xe_mmio.h"
23 #include "xe_platform_types.h"
24 #include "xe_rtp.h"
25 #include "xe_sriov.h"
26 #include "xe_step.h"
27
28 /**
29 * DOC: Hardware workarounds
30 *
31 * Hardware workarounds are register programming documented to be executed in
32 * the driver that fall outside of the normal programming sequences for a
33 * platform. There are some basic categories of workarounds, depending on
34 * how/when they are applied:
35 *
36 * - LRC workarounds: workarounds that touch registers that are
37 * saved/restored to/from the HW context image. The list is emitted (via Load
38 * Register Immediate commands) once when initializing the device and saved in
39 * the default context. That default context is then used on every context
40 * creation to have a "primed golden context", i.e. a context image that
41 * already contains the changes needed to all the registers.
42 *
43 * - Engine workarounds: the list of these WAs is applied whenever the specific
44 * engine is reset. It's also possible that a set of engine classes share a
45 * common power domain and they are reset together. This happens on some
46 * platforms with render and compute engines. In this case (at least) one of
47 * them need to keeep the workaround programming: the approach taken in the
48 * driver is to tie those workarounds to the first compute/render engine that
49 * is registered. When executing with GuC submission, engine resets are
50 * outside of kernel driver control, hence the list of registers involved in
51 * written once, on engine initialization, and then passed to GuC, that
52 * saves/restores their values before/after the reset takes place. See
53 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
54 *
55 * - GT workarounds: the list of these WAs is applied whenever these registers
56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
57 *
58 * - Register whitelist: some workarounds need to be implemented in userspace,
59 * but need to touch privileged registers. The whitelist in the kernel
60 * instructs the hardware to allow the access to happen. From the kernel side,
61 * this is just a special case of a MMIO workaround (as we write the list of
62 * these to/be-whitelisted registers to some special HW registers).
63 *
64 * - Workaround batchbuffers: buffers that get executed automatically by the
65 * hardware on every HW context restore. These buffers are created and
66 * programmed in the default context so the hardware always go through those
67 * programming sequences when switching contexts. The support for workaround
68 * batchbuffers is enabled these hardware mechanisms:
69 *
70 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
71 * context, pointing the hardware to jump to that location when that offset
72 * is reached in the context restore. Workaround batchbuffer in the driver
73 * currently uses this mechanism for all platforms.
74 *
75 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
76 * pointing the hardware to a buffer to continue executing after the
77 * engine registers are restored in a context restore sequence. This is
78 * currently not used in the driver.
79 *
80 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
81 * a central place. Those are peppered around the rest of the code, as needed.
82 * Workarounds related to the display IP are the main example.
83 *
84 * .. [1] Technically, some registers are powercontext saved & restored, so they
85 * survive a suspend/resume. In practice, writing them again is not too
86 * costly and simplifies things, so it's the approach taken in the driver.
87 *
88 * .. note::
89 * Hardware workarounds in xe work the same way as in i915, with the
90 * difference of how they are maintained in the code. In xe it uses the
91 * xe_rtp infrastructure so the workarounds can be kept in tables, following
92 * a more declarative approach rather than procedural.
93 */
94
95 #undef XE_REG_MCR
96 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
97
98 __diag_push();
99 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
100
101 static const struct xe_rtp_entry_sr gt_was[] = {
102 { XE_RTP_NAME("14011060649"),
103 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
104 ENGINE_CLASS(VIDEO_DECODE),
105 FUNC(xe_rtp_match_even_instance)),
106 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
107 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
108 },
109 { XE_RTP_NAME("14011059788"),
110 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
111 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
112 },
113 { XE_RTP_NAME("14015795083"),
114 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
115 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
116 },
117
118 /* DG1 */
119
120 { XE_RTP_NAME("1409420604"),
121 XE_RTP_RULES(PLATFORM(DG1)),
122 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
123 },
124 { XE_RTP_NAME("1408615072"),
125 XE_RTP_RULES(PLATFORM(DG1)),
126 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
127 },
128
129 /* DG2 */
130
131 { XE_RTP_NAME("22010523718"),
132 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
133 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
134 },
135 { XE_RTP_NAME("14011006942"),
136 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
137 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
138 },
139 { XE_RTP_NAME("14014830051"),
140 XE_RTP_RULES(PLATFORM(DG2)),
141 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
142 },
143 { XE_RTP_NAME("18018781329"),
144 XE_RTP_RULES(PLATFORM(DG2)),
145 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
146 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
147 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
148 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
149 },
150 { XE_RTP_NAME("1509235366"),
151 XE_RTP_RULES(PLATFORM(DG2)),
152 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
153 INVALIDATION_BROADCAST_MODE_DIS |
154 GLOBAL_INVALIDATION_MODE))
155 },
156
157 /* PVC */
158
159 { XE_RTP_NAME("18018781329"),
160 XE_RTP_RULES(PLATFORM(PVC)),
161 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
162 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
163 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
164 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
165 },
166 { XE_RTP_NAME("16016694945"),
167 XE_RTP_RULES(PLATFORM(PVC)),
168 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
169 },
170
171 /* Xe_LPG */
172
173 { XE_RTP_NAME("14015795083"),
174 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
175 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
176 },
177 { XE_RTP_NAME("14018575942"),
178 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
179 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
180 },
181 { XE_RTP_NAME("22016670082"),
182 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
183 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
184 },
185
186 /* Xe_LPM+ */
187
188 { XE_RTP_NAME("16021867713"),
189 XE_RTP_RULES(MEDIA_VERSION(1300),
190 ENGINE_CLASS(VIDEO_DECODE)),
191 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
192 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
193 },
194 { XE_RTP_NAME("22016670082"),
195 XE_RTP_RULES(MEDIA_VERSION(1300)),
196 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
197 },
198
199 /* Xe2_LPG */
200
201 { XE_RTP_NAME("16020975621"),
202 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
203 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
204 },
205 { XE_RTP_NAME("14018157293"),
206 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
207 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
208 SET(XEHPC_L3CLOS_MASK(1), ~0),
209 SET(XEHPC_L3CLOS_MASK(2), ~0),
210 SET(XEHPC_L3CLOS_MASK(3), ~0))
211 },
212
213 /* Xe2_LPM */
214
215 { XE_RTP_NAME("14017421178"),
216 XE_RTP_RULES(MEDIA_VERSION(2000),
217 ENGINE_CLASS(VIDEO_DECODE)),
218 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
219 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
220 },
221 { XE_RTP_NAME("16021867713"),
222 XE_RTP_RULES(MEDIA_VERSION(2000),
223 ENGINE_CLASS(VIDEO_DECODE)),
224 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
225 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
226 },
227 { XE_RTP_NAME("14019449301"),
228 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
229 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
230 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
231 },
232
233 /* Xe2_HPM */
234
235 { XE_RTP_NAME("16021867713"),
236 XE_RTP_RULES(MEDIA_VERSION(1301),
237 ENGINE_CLASS(VIDEO_DECODE)),
238 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
239 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
240 },
241 { XE_RTP_NAME("14020316580"),
242 XE_RTP_RULES(MEDIA_VERSION(1301)),
243 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
244 VDN_HCP_POWERGATE_ENABLE(0) |
245 VDN_MFXVDENC_POWERGATE_ENABLE(0) |
246 VDN_HCP_POWERGATE_ENABLE(2) |
247 VDN_MFXVDENC_POWERGATE_ENABLE(2))),
248 },
249 { XE_RTP_NAME("14019449301"),
250 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
251 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
252 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
253 },
254
255 /* Xe3_LPG */
256
257 { XE_RTP_NAME("14021871409"),
258 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
259 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
260 },
261
262 /* Xe3_LPM */
263
264 { XE_RTP_NAME("16021867713"),
265 XE_RTP_RULES(MEDIA_VERSION(3000),
266 ENGINE_CLASS(VIDEO_DECODE)),
267 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
268 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
269 },
270 { XE_RTP_NAME("16021865536"),
271 XE_RTP_RULES(MEDIA_VERSION(3000),
272 ENGINE_CLASS(VIDEO_DECODE)),
273 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
274 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
275 },
276 { XE_RTP_NAME("14021486841"),
277 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
278 ENGINE_CLASS(VIDEO_DECODE)),
279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
281 },
282
283 {}
284 };
285
286 static const struct xe_rtp_entry_sr engine_was[] = {
287 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
288 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
289 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
290 FF_TESSELATION_DOP_GATE_DISABLE))
291 },
292 { XE_RTP_NAME("1409804808"),
293 XE_RTP_RULES(GRAPHICS_VERSION(1200),
294 ENGINE_CLASS(RENDER),
295 IS_INTEGRATED),
296 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
297 },
298 { XE_RTP_NAME("14010229206, 1409085225"),
299 XE_RTP_RULES(GRAPHICS_VERSION(1200),
300 ENGINE_CLASS(RENDER),
301 IS_INTEGRATED),
302 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
303 },
304 { XE_RTP_NAME("1606931601"),
305 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
306 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
307 },
308 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
309 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
310 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
311 FF_DOP_CLOCK_GATE_DISABLE))
312 },
313 { XE_RTP_NAME("1406941453"),
314 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
315 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
316 },
317 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
318 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
319 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
320 FFSC_PERCTX_PREEMPT_CTRL))
321 },
322
323 /* TGL */
324
325 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
326 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
327 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
328 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
329 RC_SEMA_IDLE_MSG_DISABLE))
330 },
331
332 /* RKL */
333
334 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
335 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
336 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
337 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
338 RC_SEMA_IDLE_MSG_DISABLE))
339 },
340
341 /* ADL-P */
342
343 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
344 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
345 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
346 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
347 RC_SEMA_IDLE_MSG_DISABLE))
348 },
349
350 /* DG2 */
351
352 { XE_RTP_NAME("22013037850"),
353 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
354 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
355 DISABLE_128B_EVICTION_COMMAND_UDW))
356 },
357 { XE_RTP_NAME("22014226127"),
358 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
359 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
360 },
361 { XE_RTP_NAME("18017747507"),
362 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
363 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
364 POLYGON_TRIFAN_LINELOOP_DISABLE))
365 },
366 { XE_RTP_NAME("22012826095, 22013059131"),
367 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
368 FUNC(xe_rtp_match_first_render_or_compute)),
369 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
370 MAXREQS_PER_BANK,
371 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
372 },
373 { XE_RTP_NAME("22013059131"),
374 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
375 FUNC(xe_rtp_match_first_render_or_compute)),
376 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
377 },
378 { XE_RTP_NAME("14015227452"),
379 XE_RTP_RULES(PLATFORM(DG2),
380 FUNC(xe_rtp_match_first_render_or_compute)),
381 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
382 },
383 { XE_RTP_NAME("18028616096"),
384 XE_RTP_RULES(PLATFORM(DG2),
385 FUNC(xe_rtp_match_first_render_or_compute)),
386 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
387 },
388 { XE_RTP_NAME("22015475538"),
389 XE_RTP_RULES(PLATFORM(DG2),
390 FUNC(xe_rtp_match_first_render_or_compute)),
391 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
392 },
393 { XE_RTP_NAME("22012654132"),
394 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
395 FUNC(xe_rtp_match_first_render_or_compute)),
396 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
397 /*
398 * Register can't be read back for verification on
399 * DG2 due to Wa_14012342262
400 */
401 .read_mask = 0))
402 },
403 { XE_RTP_NAME("1509727124"),
404 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
405 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
406 },
407 { XE_RTP_NAME("22012856258"),
408 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
409 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
410 },
411 { XE_RTP_NAME("22010960976, 14013347512"),
412 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
413 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
414 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
415 },
416 { XE_RTP_NAME("14015150844"),
417 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
418 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
419 XE_RTP_NOCHECK))
420 },
421
422 /* PVC */
423
424 { XE_RTP_NAME("22014226127"),
425 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
426 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
427 },
428 { XE_RTP_NAME("14015227452"),
429 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
430 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
431 },
432 { XE_RTP_NAME("18020744125"),
433 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
434 ENGINE_CLASS(COMPUTE)),
435 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
436 },
437 { XE_RTP_NAME("14014999345"),
438 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
439 GRAPHICS_STEP(B0, C0)),
440 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
441 },
442
443 /* Xe_LPG */
444
445 { XE_RTP_NAME("14017856879"),
446 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
447 FUNC(xe_rtp_match_first_render_or_compute)),
448 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
449 },
450 { XE_RTP_NAME("14015150844"),
451 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
452 FUNC(xe_rtp_match_first_render_or_compute)),
453 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
454 XE_RTP_NOCHECK))
455 },
456 { XE_RTP_NAME("14020495402"),
457 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
458 FUNC(xe_rtp_match_first_render_or_compute)),
459 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
460 },
461
462 /* Xe2_LPG */
463
464 { XE_RTP_NAME("18032247524"),
465 XE_RTP_RULES(GRAPHICS_VERSION(2004),
466 FUNC(xe_rtp_match_first_render_or_compute)),
467 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
468 },
469 { XE_RTP_NAME("16018712365"),
470 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
471 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
472 },
473 { XE_RTP_NAME("14018957109"),
474 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
475 FUNC(xe_rtp_match_first_render_or_compute)),
476 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
477 },
478 { XE_RTP_NAME("14020338487"),
479 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
480 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
481 },
482 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
483 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
484 FUNC(xe_rtp_match_first_render_or_compute)),
485 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
486 },
487 { XE_RTP_NAME("14019322943"),
488 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
489 FUNC(xe_rtp_match_first_render_or_compute)),
490 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
491 },
492 { XE_RTP_NAME("14018471104"),
493 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
494 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
495 },
496 { XE_RTP_NAME("16018737384"),
497 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
498 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
499 },
500 /*
501 * These two workarounds are the same, just applying to different
502 * engines. Although Wa_18032095049 (for the RCS) isn't required on
503 * all steppings, disabling these reports has no impact for our
504 * driver or the GuC, so we go ahead and treat it the same as
505 * Wa_16021639441 which does apply to all steppings.
506 */
507 { XE_RTP_NAME("18032095049, 16021639441"),
508 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
509 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
510 GHWSP_CSB_REPORT_DIS |
511 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
512 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
513 },
514 { XE_RTP_NAME("16018610683"),
515 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
516 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
517 },
518 { XE_RTP_NAME("14021402888"),
519 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
520 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
521 },
522
523 /* Xe2_HPG */
524
525 { XE_RTP_NAME("16018712365"),
526 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
527 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
528 },
529 { XE_RTP_NAME("16018737384"),
530 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
531 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
532 },
533 { XE_RTP_NAME("14019988906"),
534 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
535 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
536 },
537 { XE_RTP_NAME("14019877138"),
538 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
539 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
540 },
541 { XE_RTP_NAME("14020338487"),
542 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
543 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
544 },
545 { XE_RTP_NAME("18032247524"),
546 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
547 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
548 },
549 { XE_RTP_NAME("14018471104"),
550 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
551 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
552 },
553 /*
554 * Although this workaround isn't required for the RCS, disabling these
555 * reports has no impact for our driver or the GuC, so we go ahead and
556 * apply this to all engines for simplicity.
557 */
558 { XE_RTP_NAME("16021639441"),
559 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
560 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
561 GHWSP_CSB_REPORT_DIS |
562 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
563 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
564 },
565 { XE_RTP_NAME("14019811474"),
566 XE_RTP_RULES(GRAPHICS_VERSION(2001),
567 FUNC(xe_rtp_match_first_render_or_compute)),
568 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
569 },
570 { XE_RTP_NAME("14021402888"),
571 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
572 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
573 },
574 { XE_RTP_NAME("14021821874"),
575 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
576 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
577 },
578
579 /* Xe2_LPM */
580
581 { XE_RTP_NAME("16021639441"),
582 XE_RTP_RULES(MEDIA_VERSION(2000)),
583 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
584 GHWSP_CSB_REPORT_DIS |
585 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
586 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
587 },
588
589 /* Xe2_HPM */
590
591 { XE_RTP_NAME("16021639441"),
592 XE_RTP_RULES(MEDIA_VERSION(1301)),
593 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
594 GHWSP_CSB_REPORT_DIS |
595 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
596 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
597 },
598
599 /* Xe3_LPG */
600
601 { XE_RTP_NAME("14021402888"),
602 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), FUNC(xe_rtp_match_first_render_or_compute)),
603 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
604 },
605 { XE_RTP_NAME("18034896535"),
606 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
607 FUNC(xe_rtp_match_first_render_or_compute)),
608 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
609 },
610 { XE_RTP_NAME("16024792527"),
611 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
612 FUNC(xe_rtp_match_first_render_or_compute)),
613 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
614 SMP_FORCE_128B_OVERFETCH))
615 },
616
617 {}
618 };
619
620 static const struct xe_rtp_entry_sr lrc_was[] = {
621 { XE_RTP_NAME("16011163337"),
622 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
623 /* read verification is ignored due to 1608008084. */
624 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
625 FF_MODE2_GS_TIMER_MASK,
626 FF_MODE2_GS_TIMER_224))
627 },
628 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
629 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
630 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
631 DISABLE_CPS_AWARE_COLOR_PIPE))
632 },
633 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
634 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
635 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
636 PREEMPT_GPGPU_LEVEL_MASK,
637 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
638 },
639 { XE_RTP_NAME("1806527549"),
640 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
641 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
642 },
643 { XE_RTP_NAME("1606376872"),
644 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
645 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
646 },
647
648 /* DG1 */
649
650 { XE_RTP_NAME("1409044764"),
651 XE_RTP_RULES(PLATFORM(DG1)),
652 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
653 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
654 },
655 { XE_RTP_NAME("22010493298"),
656 XE_RTP_RULES(PLATFORM(DG1)),
657 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
658 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
659 },
660
661 /* DG2 */
662
663 { XE_RTP_NAME("16013271637"),
664 XE_RTP_RULES(PLATFORM(DG2)),
665 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
666 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
667 },
668 { XE_RTP_NAME("14014947963"),
669 XE_RTP_RULES(PLATFORM(DG2)),
670 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
671 PREEMPTION_VERTEX_COUNT,
672 0x4000))
673 },
674 { XE_RTP_NAME("18018764978"),
675 XE_RTP_RULES(PLATFORM(DG2)),
676 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
677 SCOREBOARD_STALL_FLUSH_CONTROL))
678 },
679 { XE_RTP_NAME("18019271663"),
680 XE_RTP_RULES(PLATFORM(DG2)),
681 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
682 },
683 { XE_RTP_NAME("14019877138"),
684 XE_RTP_RULES(PLATFORM(DG2)),
685 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
686 },
687
688 /* PVC */
689
690 { XE_RTP_NAME("16017236439"),
691 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
692 FUNC(xe_rtp_match_even_instance)),
693 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
694 BCS_SWCTRL_DISABLE_256B,
695 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
696 },
697
698 /* Xe_LPG */
699
700 { XE_RTP_NAME("18019271663"),
701 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
702 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
703 },
704 { XE_RTP_NAME("14019877138"),
705 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
706 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
707 },
708
709 /* Xe2_LPG */
710
711 { XE_RTP_NAME("16020518922"),
712 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
713 ENGINE_CLASS(RENDER)),
714 XE_RTP_ACTIONS(SET(FF_MODE,
715 DIS_TE_AUTOSTRIP |
716 DIS_MESH_PARTIAL_AUTOSTRIP |
717 DIS_MESH_AUTOSTRIP),
718 SET(VFLSKPD,
719 DIS_PARTIAL_AUTOSTRIP |
720 DIS_AUTOSTRIP))
721 },
722 { XE_RTP_NAME("14019386621"),
723 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
724 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
725 },
726 { XE_RTP_NAME("14019877138"),
727 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
728 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
729 },
730 { XE_RTP_NAME("14020013138"),
731 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
732 ENGINE_CLASS(RENDER)),
733 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
734 },
735 { XE_RTP_NAME("14019988906"),
736 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
737 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
738 },
739 { XE_RTP_NAME("16020183090"),
740 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
741 ENGINE_CLASS(RENDER)),
742 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
743 },
744 { XE_RTP_NAME("18033852989"),
745 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
746 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
747 },
748 { XE_RTP_NAME("14021567978"),
749 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
750 ENGINE_CLASS(RENDER)),
751 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
752 },
753 { XE_RTP_NAME("14020756599"),
754 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
755 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
756 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
757 },
758 { XE_RTP_NAME("14021490052"),
759 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
760 XE_RTP_ACTIONS(SET(FF_MODE,
761 DIS_MESH_PARTIAL_AUTOSTRIP |
762 DIS_MESH_AUTOSTRIP),
763 SET(VFLSKPD,
764 DIS_PARTIAL_AUTOSTRIP |
765 DIS_AUTOSTRIP))
766 },
767 { XE_RTP_NAME("15016589081"),
768 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
769 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
770 },
771
772 /* Xe2_HPG */
773 { XE_RTP_NAME("15010599737"),
774 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
775 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
776 },
777 { XE_RTP_NAME("14019386621"),
778 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
779 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
780 },
781 { XE_RTP_NAME("14020756599"),
782 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
783 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
784 },
785 { XE_RTP_NAME("14021490052"),
786 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
787 XE_RTP_ACTIONS(SET(FF_MODE,
788 DIS_MESH_PARTIAL_AUTOSTRIP |
789 DIS_MESH_AUTOSTRIP),
790 SET(VFLSKPD,
791 DIS_PARTIAL_AUTOSTRIP |
792 DIS_AUTOSTRIP))
793 },
794 { XE_RTP_NAME("15016589081"),
795 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
796 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
797 },
798
799 /* Xe3_LPG */
800 { XE_RTP_NAME("14021490052"),
801 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
802 ENGINE_CLASS(RENDER)),
803 XE_RTP_ACTIONS(SET(FF_MODE,
804 DIS_MESH_PARTIAL_AUTOSTRIP |
805 DIS_MESH_AUTOSTRIP),
806 SET(VFLSKPD,
807 DIS_PARTIAL_AUTOSTRIP |
808 DIS_AUTOSTRIP))
809 },
810
811 {}
812 };
813
814 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
815 #include <generated/xe_wa_oob.c>
816 {}
817 };
818
819 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
820
821 __diag_pop();
822
823 /**
824 * xe_wa_process_oob - process OOB workaround table
825 * @gt: GT instance to process workarounds for
826 *
827 * Process OOB workaround table for this platform, marking in @gt the
828 * workarounds that are active.
829 */
xe_wa_process_oob(struct xe_gt * gt)830 void xe_wa_process_oob(struct xe_gt *gt)
831 {
832 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
833
834 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
835 ARRAY_SIZE(oob_was));
836 gt->wa_active.oob_initialized = true;
837 xe_rtp_process(&ctx, oob_was);
838 }
839
840 /**
841 * xe_wa_process_gt - process GT workaround table
842 * @gt: GT instance to process workarounds for
843 *
844 * Process GT workaround table for this platform, saving in @gt all the
845 * workarounds that need to be applied at the GT level.
846 */
xe_wa_process_gt(struct xe_gt * gt)847 void xe_wa_process_gt(struct xe_gt *gt)
848 {
849 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
850
851 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
852 ARRAY_SIZE(gt_was));
853 xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr);
854 }
855 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
856
857 /**
858 * xe_wa_process_engine - process engine workaround table
859 * @hwe: engine instance to process workarounds for
860 *
861 * Process engine workaround table for this platform, saving in @hwe all the
862 * workarounds that need to be applied at the engine level that match this
863 * engine.
864 */
xe_wa_process_engine(struct xe_hw_engine * hwe)865 void xe_wa_process_engine(struct xe_hw_engine *hwe)
866 {
867 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
868
869 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
870 ARRAY_SIZE(engine_was));
871 xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
872 }
873
874 /**
875 * xe_wa_process_lrc - process context workaround table
876 * @hwe: engine instance to process workarounds for
877 *
878 * Process context workaround table for this platform, saving in @hwe all the
879 * workarounds that need to be applied on context restore. These are workarounds
880 * touching registers that are part of the HW context image.
881 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)882 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
883 {
884 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
885
886 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
887 ARRAY_SIZE(lrc_was));
888 xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
889 }
890
891 /**
892 * xe_wa_init - initialize gt with workaround bookkeeping
893 * @gt: GT instance to initialize
894 *
895 * Returns 0 for success, negative error code otherwise.
896 */
xe_wa_init(struct xe_gt * gt)897 int xe_wa_init(struct xe_gt *gt)
898 {
899 struct xe_device *xe = gt_to_xe(gt);
900 size_t n_oob, n_lrc, n_engine, n_gt, total;
901 unsigned long *p;
902
903 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
904 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
905 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
906 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
907 total = n_gt + n_engine + n_lrc + n_oob;
908
909 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
910 if (!p)
911 return -ENOMEM;
912
913 gt->wa_active.gt = p;
914 p += n_gt;
915 gt->wa_active.engine = p;
916 p += n_engine;
917 gt->wa_active.lrc = p;
918 p += n_lrc;
919 gt->wa_active.oob = p;
920
921 return 0;
922 }
923 ALLOW_ERROR_INJECTION(xe_wa_init, ERRNO); /* See xe_pci_probe() */
924
xe_wa_dump(struct xe_gt * gt,struct drm_printer * p)925 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
926 {
927 size_t idx;
928
929 drm_printf(p, "GT Workarounds\n");
930 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
931 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
932
933 drm_printf(p, "\nEngine Workarounds\n");
934 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
935 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
936
937 drm_printf(p, "\nLRC Workarounds\n");
938 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
939 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
940
941 drm_printf(p, "\nOOB Workarounds\n");
942 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
943 if (oob_was[idx].name)
944 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
945 }
946
947 /*
948 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
949 * adding anything to this function; most workarounds should be implemented
950 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
951 * which are relatively rare. Since the registers these workarounds target are
952 * outside the GT, they should only need to be applied once at device
953 * probe/resume; they will not lose their values on any kind of GT or engine
954 * reset.
955 *
956 * TODO: We may want to move this over to xe_rtp in the future once we have
957 * enough workarounds to justify the work.
958 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)959 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
960 {
961 struct xe_mmio *mmio = &tile->mmio;
962
963 if (IS_SRIOV_VF(tile->xe))
964 return;
965
966 if (XE_WA(tile->primary_gt, 22010954014))
967 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
968 }
969