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/aosp_15_r20/external/rust/android-crates-io/crates/gdbstub_arch/src/aarch64/reg/
Did.rs8 /// - individual variants for those described in section B1.2. _Registers in
12 /// - a generic variant for system registers, accessed through MSR/MRS
15 /// trace registers_) or `0b11` (_Non-debug System registers_ and
16 /// _Special-purpose registers_), as `0b0x` do not encode registers;
17 /// - a variant for the abstraction of process state information, `PSTATE`
18 /// (section D1.4.), which should be preferred over field-specific
19 /// special-purpose registers (`NZCV`, `DAIF`, ...)
22 /// the `System` variant. When those aren't available (_e.g._ for newly-added
27 /// To future-proof and greatly simplify the implementation, the target's XML
28 /// must encode system registers by using their 16-bit encoding as the `regnum`
[all …]
/aosp_15_r20/external/deqp-deps/SPIRV-Tools/source/opt/
Dmerge_return_pass.h7 // http://www.apache.org/licenses/LICENSE-2.0
35 * post-dominated by the merge block, except return blocks and break blocks.
47 * with a branch. If current block is not within structured control flow, this
48 * is the final return. This block should branch to the new return block (its
50 * the branch destination should be the innermost construct's merge. This
51 * merge will always exist because a single case switch is added around the
54 * predication path should branch to the merge block of the inner-most loop
56 * been exited, it will be at the merge of the single case switch, which will
76 * 0 (single case switch header)
86 * (ret) 4 (single case switch merge)
[all …]
Ddead_branch_elim_pass.cpp10 // http://www.apache.org/licenses/LICENSE-2.0
38 Instruction* cInst = get_def_use_mgr()->GetDef(condId); in GetConstCondition()
39 switch (cInst->opcode()) { in GetConstCondition()
52 GetConstCondition(cInst->GetSingleWordInOperand(0), &negVal); in GetConstCondition()
61 Instruction* sInst = get_def_use_mgr()->GetDef(selId); in GetConstInteger()
62 uint32_t typeId = sInst->type_id(); in GetConstInteger()
63 Instruction* typeInst = get_def_use_mgr()->GetDef(typeId); in GetConstInteger()
64 if (!typeInst || (typeInst->opcode() != spv::Op::OpTypeInt)) return false; in GetConstInteger()
65 // TODO(greg-lunarg): Support non-32 bit ints in GetConstInteger()
66 if (typeInst->GetSingleWordInOperand(0) != 32) return false; in GetConstInteger()
[all …]
/aosp_15_r20/external/swiftshader/third_party/SPIRV-Tools/source/opt/
H A Dmerge_return_pass.h7 // http://www.apache.org/licenses/LICENSE-2.0
35 * post-dominated by the merge block, except return blocks and break blocks.
47 * with a branch. If current block is not within structured control flow, this
48 * is the final return. This block should branch to the new return block (its
50 * the branch destination should be the innermost construct's merge. This
51 * merge will always exist because a single case switch is added around the
54 * predication path should branch to the merge block of the inner-most loop
56 * been exited, it will be at the merge of the single case switch, which will
76 * 0 (single case switch header)
86 * (ret) 4 (single case switch merge)
[all …]
H A Ddead_branch_elim_pass.cpp10 // http://www.apache.org/licenses/LICENSE-2.0
38 Instruction* cInst = get_def_use_mgr()->GetDef(condId); in GetConstCondition()
39 switch (cInst->opcode()) { in GetConstCondition()
52 GetConstCondition(cInst->GetSingleWordInOperand(0), &negVal); in GetConstCondition()
61 Instruction* sInst = get_def_use_mgr()->GetDef(selId); in GetConstInteger()
62 uint32_t typeId = sInst->type_id(); in GetConstInteger()
63 Instruction* typeInst = get_def_use_mgr()->GetDef(typeId); in GetConstInteger()
64 if (!typeInst || (typeInst->opcode() != spv::Op::OpTypeInt)) return false; in GetConstInteger()
65 // TODO(greg-lunarg): Support non-32 bit ints in GetConstInteger()
66 if (typeInst->GetSingleWordInOperand(0) != 32) return false; in GetConstInteger()
[all …]
/aosp_15_r20/external/angle/third_party/spirv-tools/src/source/opt/
H A Dmerge_return_pass.h7 // http://www.apache.org/licenses/LICENSE-2.0
35 * post-dominated by the merge block, except return blocks and break blocks.
47 * with a branch. If current block is not within structured control flow, this
48 * is the final return. This block should branch to the new return block (its
50 * the branch destination should be the innermost construct's merge. This
51 * merge will always exist because a single case switch is added around the
54 * predication path should branch to the merge block of the inner-most loop
56 * been exited, it will be at the merge of the single case switch, which will
76 * 0 (single case switch header)
86 * (ret) 4 (single case switch merge)
[all …]
H A Ddead_branch_elim_pass.cpp10 // http://www.apache.org/licenses/LICENSE-2.0
38 Instruction* cInst = get_def_use_mgr()->GetDef(condId); in GetConstCondition()
39 switch (cInst->opcode()) { in GetConstCondition()
52 GetConstCondition(cInst->GetSingleWordInOperand(0), &negVal); in GetConstCondition()
61 Instruction* sInst = get_def_use_mgr()->GetDef(selId); in GetConstInteger()
62 uint32_t typeId = sInst->type_id(); in GetConstInteger()
63 Instruction* typeInst = get_def_use_mgr()->GetDef(typeId); in GetConstInteger()
64 if (!typeInst || (typeInst->opcode() != spv::Op::OpTypeInt)) return false; in GetConstInteger()
65 // TODO(greg-lunarg): Support non-32 bit ints in GetConstInteger()
66 if (typeInst->GetSingleWordInOperand(0) != 32) return false; in GetConstInteger()
[all …]
/aosp_15_r20/system/extras/simpleperf/
H A Dcmd_inject.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
26 #include <android-base/parseint.h>
27 #include <android-base/strings.h>
91 OverflowSafeAdd(res.first->second, p.second); in Merge()
97 OverflowSafeAdd(res.first->second, p.second); in Merge()
103 OverflowSafeAdd(res.first->second, p.second); in Merge()
111 return vaddr - segment.vaddr + segment.file_offset; in VaddrToOffset()
125 if (auto elf = ElfFile::Open(dso->GetDebugFilePath(), &status); elf) { in GetExecutableSegments()
126 segments = elf->GetProgramHeader(); in GetExecutableSegments()
134 // Base class for reading perf.data and generating AutoFDO or branch list data.
[all …]
/aosp_15_r20/external/python/cpython3/.azure-pipelines/windows-release/
Dcheckout.yml5 - checkout: none
7 - script: git clone --progress -v --depth ${{ parameters.depth }} --branch $(SourceTag) --single-br…
11 - script: git clone --progress -v --depth ${{ parameters.depth }} --branch $(SourceTag) --single-br…
15 - script: git clone --progress -v --depth ${{ parameters.depth }} --branch $(Build.SourceBranchName…
19 - script: git clone --progress -v --depth ${{ parameters.depth }} --branch $(Build.SourceBranchName…
/aosp_15_r20/external/mesa3d/src/broadcom/vulkan/
H A Dv3dvx_meta_common.c45 const struct v3dv_frame_tiling *tiling = &job->frame_tiling; in emit_rcl_prologue()
47 struct v3dv_cl *rcl = &job->rcl; in emit_rcl_prologue()
49 tiling->layers * 256 * in emit_rcl_prologue()
51 if (job->cmd_buffer->state.oom) in emit_rcl_prologue()
54 assert(!tiling->msaa || !tiling->double_buffer); in emit_rcl_prologue()
57 config.image_width_pixels = tiling->width; in emit_rcl_prologue()
58 config.image_height_pixels = tiling->height; in emit_rcl_prologue()
60 config.multisample_mode_4x = tiling->msaa; in emit_rcl_prologue()
61 config.double_buffer_in_non_ms_mode = tiling->double_buffer; in emit_rcl_prologue()
63 config.maximum_bpp_of_all_render_targets = tiling->internal_bpp; in emit_rcl_prologue()
[all …]
/aosp_15_r20/external/deqp-deps/SPIRV-Tools/source/fuzz/protobufs/
Dspvtoolsfuzz.proto7 // http://www.apache.org/licenses/LICENSE-2.0
16 // 'spvtools_fuzz' appears in the names of global-scope symbols that protoc
18 // clashes with other globally-scoped symbols.
58 // - id_of_interest = 42
59 // - enclosing_instruction = (
64 // - in_operand_index = 1
89 // The object being accessed - a scalar or composite
106 // GLSL-like syntax):
115 // - (7, 9, [0]) describes the 'f' field.
116 // - (7, 9, [1,1]) describes the y component of the 'g' field.
[all …]
/aosp_15_r20/external/angle/third_party/spirv-tools/src/source/fuzz/protobufs/
H A Dspvtoolsfuzz.proto7 // http://www.apache.org/licenses/LICENSE-2.0
16 // 'spvtools_fuzz' appears in the names of global-scope symbols that protoc
18 // clashes with other globally-scoped symbols.
58 // - id_of_interest = 42
59 // - enclosing_instruction = (
64 // - in_operand_index = 1
89 // The object being accessed - a scalar or composite
106 // GLSL-like syntax):
115 // - (7, 9, [0]) describes the 'f' field.
116 // - (7, 9, [1,1]) describes the y component of the 'g' field.
[all …]
/aosp_15_r20/external/swiftshader/third_party/SPIRV-Tools/source/fuzz/protobufs/
H A Dspvtoolsfuzz.proto7 // http://www.apache.org/licenses/LICENSE-2.0
16 // 'spvtools_fuzz' appears in the names of global-scope symbols that protoc
18 // clashes with other globally-scoped symbols.
58 // - id_of_interest = 42
59 // - enclosing_instruction = (
64 // - in_operand_index = 1
89 // The object being accessed - a scalar or composite
106 // GLSL-like syntax):
115 // - (7, 9, [0]) describes the 'f' field.
116 // - (7, 9, [1,1]) describes the y component of the 'g' field.
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp1 //===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // (2) fuses compares and branches into COMPARE AND BRANCH instructions
13 //===----------------------------------------------------------------------===//
36 #define DEBUG_TYPE "systemz-elim-compare"
38 STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
39 STATISTIC(LoadAndTraps, "Number of load-and-trap instructions");
41 STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
59 // via a sub- or super-register.
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp1 //===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // (2) fuses compares and branches into COMPARE AND BRANCH instructions
13 //===----------------------------------------------------------------------===//
36 #define DEBUG_TYPE "systemz-elim-compare"
38 STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
39 STATISTIC(LoadAndTraps, "Number of load-and-trap instructions");
41 STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
59 // via a sub- or super-register.
[all …]
/aosp_15_r20/external/aws-sdk-java-v2/services/amplify/src/main/resources/codegen-resources/
H A Dservice-2.json4 "apiVersion":"2017-07-25",
7 "protocol":"rest-json",
13 "uid":"amplify-2017-07-25"
66 "documentation":"<p> Creates a new branch for an Amplify app. </p>"
169 "documentation":"<p> Deletes a branch for an Amplify app. </p>"
203 "documentation":"<p> Deletes a job for a branch of an Amplify app. </p>"
301 "documentation":"<p> Returns a branch for an Amplify app. </p>"
334 "documentation":"<p> Returns a job for a branch of an Amplify app. </p>"
382 "documentation":"<p>Returns a list of artifacts for a specified app, branch, and job. </p>"
443 "documentation":"<p> Lists the jobs for a branch of an Amplify app. </p>"
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp1 //===---- PPCReduceCRLogicals.cpp - Reduce CR Bit Logical operations ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===---------------------------------------------------------------------===//
10 // register. These instructions have a fairly high latency and only a single
15 //===---------------------------------------------------------------------===//
26 #include "llvm/Config/llvm-config.h"
32 #define DEBUG_TYPE "ppc-reduce-cr-ops"
35 "Number of single-use binary CR logical ops contained in a block");
58 for (auto &MI : Successor->instrs()) { in updatePHIs()
61 // This is a really ugly-looking loop, but it was pillaged directly from in updatePHIs()
[all …]
/aosp_15_r20/external/deqp-deps/SPIRV-Tools/source/fuzz/
Dtransformation_flatten_conditional_branch.cpp7 // http://www.apache.org/licenses/LICENSE-2.0
50 if (!header_block || !header_block->GetMergeInst() || in IsApplicable()
51 header_block->GetMergeInst()->opcode() != spv::Op::OpSelectionMerge) { in IsApplicable()
56 if (header_block->terminator()->opcode() != spv::Op::OpBranchConditional) { in IsApplicable()
60 // The branch condition cannot be irrelevant: we will make reference to it in IsApplicable()
64 if (transformation_context.GetFactManager()->IdIsIrrelevant( in IsApplicable()
65 header_block->terminator()->GetSingleWordInOperand(0))) { in IsApplicable()
128 auto value_def = ir_context->get_def_use_mgr()->GetDef( in IsApplicable()
131 value_def->type_id() != inst_to_info.first->type_id() || in IsApplicable()
145 !transformation_context.GetOverflowIdSource()->HasOverflowIds()) { in IsApplicable()
[all …]
/aosp_15_r20/external/angle/third_party/spirv-tools/src/source/fuzz/
H A Dtransformation_flatten_conditional_branch.cpp7 // http://www.apache.org/licenses/LICENSE-2.0
50 if (!header_block || !header_block->GetMergeInst() || in IsApplicable()
51 header_block->GetMergeInst()->opcode() != spv::Op::OpSelectionMerge) { in IsApplicable()
56 if (header_block->terminator()->opcode() != spv::Op::OpBranchConditional) { in IsApplicable()
60 // The branch condition cannot be irrelevant: we will make reference to it in IsApplicable()
64 if (transformation_context.GetFactManager()->IdIsIrrelevant( in IsApplicable()
65 header_block->terminator()->GetSingleWordInOperand(0))) { in IsApplicable()
128 auto value_def = ir_context->get_def_use_mgr()->GetDef( in IsApplicable()
131 value_def->type_id() != inst_to_info.first->type_id() || in IsApplicable()
145 !transformation_context.GetOverflowIdSource()->HasOverflowIds()) { in IsApplicable()
[all …]
/aosp_15_r20/external/swiftshader/third_party/SPIRV-Tools/source/fuzz/
H A Dtransformation_flatten_conditional_branch.cpp7 // http://www.apache.org/licenses/LICENSE-2.0
50 if (!header_block || !header_block->GetMergeInst() || in IsApplicable()
51 header_block->GetMergeInst()->opcode() != spv::Op::OpSelectionMerge) { in IsApplicable()
56 if (header_block->terminator()->opcode() != spv::Op::OpBranchConditional) { in IsApplicable()
60 // The branch condition cannot be irrelevant: we will make reference to it in IsApplicable()
64 if (transformation_context.GetFactManager()->IdIsIrrelevant( in IsApplicable()
65 header_block->terminator()->GetSingleWordInOperand(0))) { in IsApplicable()
128 auto value_def = ir_context->get_def_use_mgr()->GetDef( in IsApplicable()
131 value_def->type_id() != inst_to_info.first->type_id() || in IsApplicable()
145 !transformation_context.GetOverflowIdSource()->HasOverflowIds()) { in IsApplicable()
[all …]
/aosp_15_r20/external/swiftshader/third_party/subzero/docs/
H A DDESIGN.rst5 ------------
9 PNaCl toolchain to compile their application to architecture-neutral PNaCl
10 bitcode (a ``.pexe`` file), using as much architecture-neutral optimization as
14 <https://developer.chrome.com/native-client/reference/sandbox_internals/index>`_
15 native code. The translator uses architecture-specific optimizations as much as
19 future page loads. However, first-time user experience is hampered by long
20 translation times. The LLVM-based PNaCl translator is pretty slow, even when
21 using ``-O0`` to minimize optimizations, so delays are especially noticeable on
22 slow browser platforms such as ARM-based Chromebooks.
26 - Parallel translation. However, slow machines where this matters most, e.g.
[all …]
/aosp_15_r20/external/swiftshader/third_party/subzero/
H A DDESIGN.rst5 ------------
9 PNaCl toolchain to compile their application to architecture-neutral PNaCl
10 bitcode (a ``.pexe`` file), using as much architecture-neutral optimization as
14 <https://developer.chrome.com/native-client/reference/sandbox_internals/index>`_
15 native code. The translator uses architecture-specific optimizations as much as
19 future page loads. However, first-time user experience is hampered by long
20 translation times. The LLVM-based PNaCl translator is pretty slow, even when
21 using ``-O0`` to minimize optimizations, so delays are especially noticeable on
22 slow browser platforms such as ARM-based Chromebooks.
26 - Parallel translation. However, slow machines where this matters most, e.g.
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp1 //===---- PPCReduceCRLogicals.cpp - Reduce CR Bit Logical operations ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===---------------------------------------------------------------------===//
10 // register. These instructions have a fairly high latency and only a single
15 //===---------------------------------------------------------------------===//
26 #include "llvm/Config/llvm-config.h"
32 #define DEBUG_TYPE "ppc-reduce-cr-ops"
35 "Number of single-use binary CR logical ops contained in a block");
58 for (auto &MI : Successor->instrs()) { in updatePHIs()
61 // This is a really ugly-looking loop, but it was pillaged directly from in updatePHIs()
[all …]
/aosp_15_r20/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/share/man/man1/
Dx86_64-w64-mingw32-gcov.126 .\" Set up some character translations and predefined strings. \*(-- will
32 .tr \(*W-
35 . ds -- \(*W-
37 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
38 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
45 . ds -- \|\(em\|
51 .\" Escape single quotes in literal strings from groff's Unicode transform.
72 .\" Fear. Run. Save yourself. No user-serviceable parts.
82 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
98 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
[all …]
/aosp_15_r20/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp1 //===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===//
8 //===----------------------------------------------------------------------===//
12 // (2) fuses compares and branches into COMPARE AND BRANCH instructions
14 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "systemz-elim-compare"
30 STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
32 STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
50 // via a sub- or super-register.
98 if ((*SI)->isLiveIn(SystemZ::CC)) in isCCLiveOut()
136 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
[all …]

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