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/linux-6.14.4/tools/testing/vma/
Dvma.c44 } while (0)
206 int count = 0; in cleanup_mm()
211 vma_iter_set(vmi, 0); in cleanup_mm()
218 mm->map_count = 0; in cleanup_mm()
244 struct vm_area_struct *vma_left = alloc_vma(&mm, 0, 0x1000, 0, flags); in test_simple_merge()
245 struct vm_area_struct *vma_right = alloc_vma(&mm, 0x2000, 0x3000, 2, flags); in test_simple_merge()
246 VMA_ITERATOR(vmi, &mm, 0x1000); in test_simple_merge()
250 .start = 0x1000, in test_simple_merge()
251 .end = 0x2000, in test_simple_merge()
262 ASSERT_EQ(vma->vm_start, 0); in test_simple_merge()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/sprd/
Dums512.dtsi18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
[all …]
Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
27 apahb_gate: apahb-gate@0 {
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
42 pmu_gate: pmu-gate@0 {
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6ul-ccimx6ulsom.dtsi12 reg = <0x80000000 0>; /* will be filled by U-Boot */
23 size = <0x4000000>;
35 pinctrl-0 = <&pinctrl_gpmi_nand>;
42 pinctrl-0 = <&pinctrl_i2c1>;
47 reg = <0x08>;
171 pinctrl-0 = <&pinctrl_uart1>;
179 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>;
190 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
191 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
192 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
[all …]
Dimx6q-apalis-ixora-v1.2.dts37 pinctrl-0 = <&pinctrl_leds_ixora>;
63 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
65 pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
77 pinctrl-0 = <&pinctrl_enable_can1_power>;
87 pinctrl-0 = <&pinctrl_enable_can2_power>;
105 pinctrl-0 = <&pinctrl_uart24_forceoff>;
127 reg = <0x68>;
132 reg = <0x50>;
147 pinctrl-0 = <&pinctrl_reset_moci>;
221 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
[all …]
Dimx6ul-ccimx6ulsbcpro.dts21 pwms = <&pwm5 0 50000 0>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
51 pinctrl-0 = <&pinctrl_adc1>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1_master>;
79 pinctrl-0 = <&pinctrl_enet1>;
87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
96 #size-cells = <0>;
98 ethphy0: ethernet-phy@0 {
[all …]
/linux-6.14.4/drivers/accel/habanalabs/include/goya/asic_reg/
Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/linux-6.14.4/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/linux-6.14.4/sound/isa/msnd/
Dmsnd.c48 writew(0, base + JQS_wHead); in snd_msnd_init_queue()
49 writew(0, base + JQS_wTail); in snd_msnd_init_queue()
58 while (timeout-- > 0) in snd_msnd_wait_TXDE()
60 return 0; in snd_msnd_wait_TXDE()
70 while (timeout-- > 0) in snd_msnd_wait_HC0()
72 return 0; in snd_msnd_wait_HC0()
82 if (snd_msnd_wait_HC0(dev) == 0) { in snd_msnd_send_dsp_cmd()
85 return 0; in snd_msnd_send_dsp_cmd()
100 if (snd_msnd_wait_TXDE(dev) == 0) { in snd_msnd_send_word()
104 return 0; in snd_msnd_send_word()
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dtcsrcc-sm8750.c25 .halt_reg = 0x0,
28 .enable_reg = 0x0,
29 .enable_mask = BIT(0),
38 .halt_reg = 0x1000,
41 .enable_reg = 0x1000,
42 .enable_mask = BIT(0),
55 .halt_reg = 0x2000,
58 .enable_reg = 0x2000,
59 .enable_mask = BIT(0),
72 .halt_reg = 0x3000,
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
29 pruss1: pruss@0 {
31 reg = <0x0 0x80000>;
36 pruss1_mem: memories@0 {
37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
39 <0x10000 0x8000>;
[all …]
/linux-6.14.4/tools/testing/selftests/bpf/progs/
Dtest_ringbuf_write.c14 int pid = 0;
17 long passed = 0;
18 long discarded = 0;
27 return 0; in test_ringbuf_write()
29 sample1 = bpf_ringbuf_reserve(&ringbuf, 0x3000, 0); in test_ringbuf_write()
31 return 0; in test_ringbuf_write()
33 sample2 = bpf_ringbuf_reserve(&ringbuf, 0x3000, 0); in test_ringbuf_write()
35 bpf_ringbuf_discard(sample1, 0); in test_ringbuf_write()
37 return 0; in test_ringbuf_write()
43 bpf_ringbuf_discard(sample1, 0); in test_ringbuf_write()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux-6.14.4/drivers/net/dsa/mv88e6xxx/
Dglobal1.h16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
/linux-6.14.4/arch/powerpc/include/asm/
Dkdump.h7 #define KDUMP_KERNELBASE 0x2000000
12 #define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
23 #define KDUMP_TRAMPOLINE_START 0x0100
24 #define KDUMP_TRAMPOLINE_END 0x3000
26 #define KDUMP_TRAMPOLINE_START (0x0100 + PAGE_OFFSET)
27 #define KDUMP_TRAMPOLINE_END (0x3000 + PAGE_OFFSET)
/linux-6.14.4/arch/arm/boot/dts/intel/ixp/
Dintel-ixp43x-gateworks-gw2358.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x57>;
81 flash@0,0 {
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Dsprd,ums512-glbreg.yaml41 "^clock-controller@[0-9a-f]+$":
57 reg = <0x71000000 0x3000>;
60 ranges = <0 0x71000000 0x3000>;
62 clock-controller@0 {
64 reg = <0x0 0x2000>;
72 reg = <0x32360000 0x1000>;
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dpq3-i2c-0.dtsi2 * PQ3 I2C device tree stub [ controller @ offset 0x3000 ]
37 #size-cells = <0>;
38 cell-index = <0>;
40 reg = <0x3000 0x100>;
41 interrupts = <43 2 0 0>;
/linux-6.14.4/arch/sh/boot/romimage/
Dmmcif-sh7724.c14 #define MMCIF_BASE (void __iomem *)0xa4ca0000
16 #define MSTPCR2 0xa4150038
17 #define PTWCR 0xa4050146
18 #define PTXCR 0xa4050148
19 #define PSELA 0xa405014e
20 #define PSELE 0xa4050156
21 #define HIZCRC 0xa405015c
22 #define DRVCRA 0xa405018a
42 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
45 __raw_writew(0x0000, PTWCR); in mmcif_loader()
[all …]
/linux-6.14.4/drivers/gpu/drm/vc4/
Dvc4_hvs.c216 for (i = 0; i < 64; i += 4) { in vc4_hvs_dump_state()
217 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", in vc4_hvs_dump_state()
219 readl((u32 __iomem *)hvs->dlist + i + 0), in vc4_hvs_dump_state()
237 return 0; in vc4_hvs_debugfs_underrun()
252 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { in vc4_hvs_debugfs_dlist()
262 next_entry_start = 0; in vc4_hvs_debugfs_dlist()
266 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, in vc4_hvs_debugfs_dlist()
279 return 0; in vc4_hvs_debugfs_dlist()
293 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { in vc6_hvs_debugfs_dlist()
309 next_entry_start = 0; in vc6_hvs_debugfs_dlist()
[all …]
/linux-6.14.4/drivers/staging/gpib/include/
Dplx9050.h13 PLX9050_INTCSR_REG = 0x4c,
14 PLX9050_CNTRL_REG = 0x50
18 PLX9050_LINTR1_EN_BIT = 0x1,
19 PLX9050_LINTR1_POLARITY_BIT = 0x2,
20 PLX9050_LINTR1_STATUS_BIT = 0x4,
21 PLX9050_LINTR2_EN_BIT = 0x8,
22 PLX9050_LINTR2_POLARITY_BIT = 0x10,
23 PLX9050_LINTR2_STATUS_BIT = 0x20,
24 PLX9050_PCI_INTR_EN_BIT = 0x40,
25 PLX9050_SOFT_INTR_BIT = 0x80,
[all …]

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