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/linux-6.14.4/drivers/accel/habanalabs/include/goya/asic_reg/
Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
[all …]
Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/linux-6.14.4/drivers/media/common/b2c2/
Dflexcop-sram.c28 return 0; in flexcop_sram_init()
55 return 0; in flexcop_sram_set_dest()
75 #if 0
81 for (i = 0; i < len; i++) {
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
91 if (retries == 0)
94 write_reg_dw(adapter, 0x700, command);
106 for (i = 0; i < len; i++) {
107 command = bank | addr | 0x04008000;
[all …]
/linux-6.14.4/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux-6.14.4/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drenesas,usb2-phy.yaml56 enum: [0, 1] # and 0 is deprecated.
123 reg = <0xee080200 0x700>;
131 reg = <0xee0a0200 0x700>;
/linux-6.14.4/arch/loongarch/include/asm/
Dbarrier.h11 * Bit4: ordering or completion (0: completion, 1: ordering)
12 * Bit3: barrier for previous read (0: true, 1: false)
13 * Bit2: barrier for previous write (0: true, 1: false)
14 * Bit1: barrier for succeeding read (0: true, 1: false)
15 * Bit0: barrier for succeeding write (0: true, 1: false)
17 * Hint 0x700: barrier for "read after read" from the same address
20 #define DBAR(hint) __asm__ __volatile__("dbar %0 " : : "I"(hint) : "memory")
22 #define crwrw 0b00000
23 #define cr_r_ 0b00101
24 #define c_w_w 0b01010
[all …]
/linux-6.14.4/arch/x86/include/asm/
Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
[all …]
/linux-6.14.4/drivers/pinctrl/samsung/
Dpinctrl-exynos.h20 #define EXYNOS_PIN_CON_FUNC_EINT 0xf
23 #define EXYNOS_GPIO_ECON_OFFSET 0x700
24 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
25 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
26 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
27 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
28 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
29 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
30 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
31 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
[all …]
/linux-6.14.4/include/linux/
Dcb710.h109 #define cb710_dump_regs(c, d) do {} while (0)
112 #define CB710_DUMP_REGS_MMC 0x0F
113 #define CB710_DUMP_REGS_MS 0x30
114 #define CB710_DUMP_REGS_SM 0xC0
115 #define CB710_DUMP_REGS_ALL 0xFF
116 #define CB710_DUMP_REGS_MASK 0xFF
118 #define CB710_DUMP_ACCESS_8 0x100
119 #define CB710_DUMP_ACCESS_16 0x200
120 #define CB710_DUMP_ACCESS_32 0x400
121 #define CB710_DUMP_ACCESS_ALL 0x700
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux-6.14.4/drivers/regulator/
Dmt6357-regulator.c53 .enable_mask = BIT(0), \
75 .enable_mask = BIT(0), \
96 .enable_mask = BIT(0), \
99 .da_vsel_mask = 0x7f00, \
114 .enable_mask = BIT(0), \
134 if (ret != 0) { in mt6357_get_buck_voltage_sel()
178 0,
186 0,
188 0,
189 0,
[all …]
Dmt6358-regulator.c54 .enable_mask = BIT(0), \
58 .qi = BIT(0), \
82 .vsel_mask = GENMASK(3, 0), \
107 .enable_mask = BIT(0), \
112 .qi = BIT(0), \
127 .vsel_mask = GENMASK(3, 0), \
155 .enable_mask = BIT(0), \
159 .qi = BIT(0), \
183 .vsel_mask = GENMASK(3, 0), \
208 .enable_mask = BIT(0), \
[all …]
/linux-6.14.4/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dpsoc_etr_masks.h24 #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0
25 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF
28 #define PSOC_ETR_STS_FULL_SHIFT 0
29 #define PSOC_ETR_STS_FULL_MASK 0x1
31 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2
33 #define PSOC_ETR_STS_TMCREADY_MASK 0x4
35 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8
37 #define PSOC_ETR_STS_EMPTY_MASK 0x10
39 #define PSOC_ETR_STS_MEMERR_MASK 0x20
42 #define PSOC_ETR_RRD_RRD_SHIFT 0
[all …]
/linux-6.14.4/tools/perf/arch/powerpc/util/
Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/linux-6.14.4/arch/powerpc/kvm/
Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/linux-6.14.4/arch/loongarch/mm/
Dtlbex.S32 tlb_do_page_fault 0
44 jirl ra, t0, 0
66 ld.d t1, t1, 0
71 ld.d t1, t1, 0
75 ld.d ra, t1, 0
91 ll.d t0, t1, 0
93 ld.d t0, t1, 0
100 sc.d t0, t1, 0
103 st.d t0, t1, 0
107 ld.d t0, t1, 0
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-si.yaml39 reg = <0x700 0x80>;

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