Searched +full:0 +full:xc7018 (Results 1 – 5 of 5) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | qcom,qcs8300-gcc.yaml | 27 - description: PCIE 0 Pipe clock source
31 - description: UFS Phy Rx symbol 0 clock source
33 - description: UFS Phy Tx symbol 0 clock source
51 reg = <0x00100000 0xc7018>;
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| D | qcom,sa8775p-gcc.yaml | 34 - description: PCIe 0 pipe clock
63 reg = <0x100000 0xc7018>;
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| /linux-6.14.4/drivers/clk/qcom/ |
| D | gcc-sa8775p.c | 74 .offset = 0x0,
77 .enable_reg = 0x4b028,
78 .enable_mask = BIT(0),
89 { 0x1, 2 },
94 .offset = 0x0,
111 .offset = 0x1000,
114 .enable_reg = 0x4b028,
126 .offset = 0x4000,
129 .enable_reg = 0x4b028,
141 .offset = 0x5000,
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/qcom/ |
| D | qcs8300.dtsi | 29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0 0x0>;
66 reg = <0x0 0x100>;
85 reg = <0x0 0x200>;
104 reg = <0x0 0x300>;
123 reg = <0x0 0x10000>;
142 reg = <0x0 0x10100>;
[all …]
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| D | sa8775p.dtsi | 30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
89 reg = <0x0 0x200>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
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