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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Drcar-pci-host.yaml115 reg = <0 0xfe000000 0 0x80000>;
118 bus-range = <0x00 0xff>;
120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Drcar-pci-ep.yaml79 reg = <0xfe000000 0x80000>,
80 <0xfe100000 0x100000>,
81 <0xfe200000 0x200000>,
82 <0x30000000 0x8000000>,
83 <0x38000000 0x8000000>;
/linux-6.14.4/arch/arm/mach-mmp/
Daddr-map.h15 #define APB_PHYS_BASE 0xd4000000
16 #define APB_VIRT_BASE IOMEM(0xfe000000)
17 #define APB_PHYS_SIZE 0x00200000
19 #define AXI_PHYS_BASE 0xd4200000
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
21 #define AXI_PHYS_SIZE 0x00200000
23 #define PGU_PHYS_BASE 0xe0000000
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
25 #define PGU_PHYS_SIZE 0x00100000
27 /* Static Memory Controller - Chip Select 0 and 1 */
[all …]
/linux-6.14.4/arch/arm/mach-tegra/
Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml82 "^usb@[0-9a-f]+$":
111 usb@0 {
112 #address-cells = <0x2>;
113 #size-cells = <0x2>;
115 reg = <0x0 0xff9d0000 0x0 0x100>;
123 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
129 reg = <0x0 0xfe200000 0x0 0x40000>;
131 interrupts = <0 65 4>, <0 69 4>;
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dkmcoge4.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Db4qds.dtsi51 reg = <0xf 0xfe124000 0 0x2000>;
52 ranges = <0 0 0xf 0xe8000000 0x08000000
53 2 0 0xf 0xff800000 0x00010000
54 3 0 0xf 0xffdf0000 0x00008000>;
56 nor@0,0 {
60 reg = <0x0 0x0 0x8000000>;
65 nand@2,0 {
69 reg = <0x2 0x0 0x10000>;
71 partition@0 {
74 reg = <0x0 0x00100000>;
[all …]
Dp2041rdb.dts67 size = <0 0x1000000>;
68 alignment = <0 0x1000000>;
71 size = <0 0x400000>;
72 alignment = <0 0x400000>;
75 size = <0 0x2000000>;
76 alignment = <0 0x2000000>;
81 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
85 ranges = <0x0 0xf 0xf4000000 0x200000>;
89 ranges = <0x0 0xf 0xf4200000 0x200000>;
93 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dp3041ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dp5020ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dp4080ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dp5040ds.dts80 size = <0 0x1000000>;
81 alignment = <0 0x1000000>;
84 size = <0 0x400000>;
85 alignment = <0 0x400000>;
88 size = <0 0x2000000>;
89 alignment = <0 0x2000000>;
94 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
98 ranges = <0x0 0xf 0xf4000000 0x200000>;
102 ranges = <0x0 0xf 0xf4200000 0x200000>;
106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/linux-6.14.4/arch/sh/drivers/pci/
Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
Dpci-sh7751.c26 if (((word >> area) & 1) == 0) { in __area_sdram_check()
27 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", in __area_sdram_check()
29 return 0; in __area_sdram_check()
35 if (((word >> (area << 1)) & 0x3) != 0x3) { in __area_sdram_check()
36 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", in __area_sdram_check()
38 return 0; in __area_sdram_check()
48 .start = 0x1000,
63 .mem_offset = 0x00000000,
64 .io_offset = 0x00000000,
71 .size = 0x04000000,
[all …]
Dpci-sh7780.c24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
Dpcie-sh7786.c44 .name = "PCIe0 MEM 0",
45 .start = 0xfd000000,
46 .end = 0xfd000000 + SZ_8M - 1,
50 .start = 0xc0000000,
51 .end = 0xc0000000 + SZ_512M - 1,
55 .start = 0x10000000,
56 .end = 0x10000000 + SZ_64M - 1,
60 .start = 0xfe100000,
61 .end = 0xfe100000 + SZ_1M - 1,
68 .name = "PCIe1 MEM 0",
[all …]
/linux-6.14.4/arch/arm64/boot/dts/lg/
Dlg1312.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
Dlg1313.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
Dr8a77980.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
Dr8a774a1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
Dr8a774b1.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
[all …]
/linux-6.14.4/arch/arm/boot/dts/renesas/
Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]

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