Searched full:armv7 (Results 1 – 25 of 258) sorted by relevance
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| /linux-6.14.4/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 26 - const: arm,armv7-timer
29 - arm,armv7-timer
33 - const: arm,armv7-timer
95 supported for 32-bit systems which follow the ARMv7 architected reset
120 "arm,armv7-timer";
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| D | arm,arch_timer_mmio.yaml | 23 - arm,armv7-timer-mem
52 supported for 32-bit systems which follow the ARMv7 architected reset
101 compatible = "arm,armv7-timer-mem";
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| /linux-6.14.4/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 110 Indicates that the ARMv7 Secure Debug Enable Register
112 any setup required that is only possible in ARMv7 secure
113 state. If not present the ARMv7 SDER will not be touched,
117 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
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| /linux-6.14.4/arch/arm/mach-mmp/ |
| D | Kconfig | 29 bool "Support MMP2 (ARMv7) platforms from device tree"
42 bool "Support MMP3 (ARMv7) platforms"
77 Select code specific to MMP2. MMP2 is ARMv7 compatible.
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| /linux-6.14.4/Documentation/arch/arm/ |
| D | marvell.rst | 133 Sheeva ARMv7 compatible PJ4B
152 Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP
304 Sheeva ARMv7 compatible Quad-core PJ4C
327 ARMv7 compatible
364 - Core: ARMv7 compatible Sheeva PJ4 core
402 - Core: ARMv7 compatible Sheeva PJ4 88sv581x core
406 - Core: Dual-core ARMv7 compatible Sheeva PJ4C core
409 - Core: ARMv7 compatible Sheeva PJ4 core
412 - Core: Dual-core ARMv7 compatible Sheeva PJ4B-MP core
415 - Core: quad-core ARMv7 Cortex-A7
[all …]
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| /linux-6.14.4/arch/arm/mach-mstar/ |
| D | Kconfig | 2 bool "MStar/Sigmastar Armv7 SoC Support"
12 based on Armv7 cores like the Cortex A7 and share the same
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| D | mstarv7.c | 3 * Device Tree support for MStar/Sigmastar Armv7 SoCs
125 DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
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| /linux-6.14.4/arch/arm/mach-stm32/ |
| D | Kconfig | 43 endif # ARMv7-M
60 endif # ARMv7-A
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| /linux-6.14.4/arch/arm/mm/ |
| D | proc-v7m.S | 8 * This is the "shell" of the ARMv7-M processor support.
105 * This should be able to cover all ARMv7-M cores.
179 string cpu_v7m_name "ARMv7-M"
248 * Match any ARMv7-M processor core.
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| D | cache-tauros2.c | 243 * not complying with all of the other ARMv7 requirements), in tauros2_internal_init()
251 * When Tauros2 is used in an ARMv7 system, the L2 in tauros2_internal_init()
254 * ARMv7 spec to contain fine-grained cache control bits). in tauros2_internal_init()
262 mode = "ARMv7"; in tauros2_internal_init()
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| D | tlb-v7.S | 6 * Modified for ARMv7 by Catalin Marinas
20 .arch armv7-a
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| D | Kconfig | 406 # ARMv7 and ARMv8 architectures
670 Say Y if you have an ARMv7 processor supporting the LPAE page
725 ARMv7 multiprocessing extensions introduce the ability to disable
774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
905 run on ARMv4 through to ARMv7 without modification.
1104 provide DMA coherent memory. With the advent of ARMv7, mapping
1116 On some of the beefier ARMv7-M machines (with DMA and write
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| D | proc-macros.S | 72 * on ARMv7.
90 * on ARMv7.
121 * The ARMv6 and ARMv7 set_pte_ext translation function.
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| /linux-6.14.4/Documentation/devicetree/bindings/arm/mstar/ |
| D | mstar,smpctrl.yaml | 8 title: MStar/SigmaStar Armv7 SoC SMP control registers
14 MStar/SigmaStar's Armv7 SoCs that have more than one processor
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| D | mstar,l3bridge.yaml | 8 title: MStar/SigmaStar Armv7 SoC l3bridge
14 MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
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| /linux-6.14.4/drivers/soc/samsung/ |
| D | Kconfig | 12 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
49 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
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| /linux-6.14.4/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
56 detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
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| /linux-6.14.4/arch/arm/ |
| D | Makefile | 63 arch-$(CONFIG_CPU_32v7M) :=-march=armv7-m
64 arch-$(CONFIG_CPU_32v7) :=-march=armv7-a
67 # always available in ARMv7
83 # always available in ARMv7
138 CC_FLAGS_FPU += -march=armv7-a -mfloat-abi=softfp -mfpu=neon
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| /linux-6.14.4/arch/arm/kernel/ |
| D | entry-v7m.S | 7 * Low-level vector interface routines for the ARMv7-M architecture
101 * Register switch for ARMv7-M processors.
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| D | cacheinfo.c | 88 /* CLIDR is not present before ARMv7/v7m */ in detect_cache_level()
157 /* CLIDR is not present before ARMv7/v7m */ in populate_cache_leaves()
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| /linux-6.14.4/arch/arm/mach-at91/ |
| D | Kconfig | 84 bool "ARMv7 based Microchip LAN966 SoC family"
90 This enables support for ARMv7 based Microchip LAN966 SoC family.
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| /linux-6.14.4/arch/arm64/kernel/ |
| D | compat_alignment.c | 39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
75 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ in do_alignment_ldrdstrd()
229 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
230 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
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| /linux-6.14.4/arch/arm/mach-sunxi/ |
| D | Makefile | 2 CFLAGS_mc_smp.o += -march=armv7-a
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| /linux-6.14.4/arch/arm/mach-rockchip/ |
| D | Makefile | 2 CFLAGS_platsmp.o := -march=armv7-a
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| /linux-6.14.4/arch/arm/mach-hisi/ |
| D | Makefile | 6 CFLAGS_platmcpm.o := -march=armv7-a
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