| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_audio.c | 1079 /* calculate DTO settings */ in dce_aud_wall_dto_setup()
1093 /* On TN/SI, Program DTO source select and DTO select before in dce_aud_wall_dto_setup()
1094 programming DTO modulo and DTO phase. These bits must be in dce_aud_wall_dto_setup()
1120 calculate DTO settings */ in dce_aud_wall_dto_setup()
1126 /* Program DTO select before programming DTO modulo and DTO in dce_aud_wall_dto_setup()
1171 /* calculate DTO settings */ in dce60_aud_wall_dto_setup()
1185 /* On TN/SI, Program DTO source select and DTO select before in dce60_aud_wall_dto_setup()
1186 programming DTO modulo and DTO phase. These bits must be in dce60_aud_wall_dto_setup()
1212 calculate DTO settings */ in dce60_aud_wall_dto_setup()
1218 /* Program DTO select before programming DTO modulo and DTO in dce60_aud_wall_dto_setup()
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| D | dce_clock_source.c | 909 /* Resync deep color DTO */ in dce110_program_pix_clk()
955 /* Resync deep color DTO */ in dce112_program_pix_clk()
987 /* Set DTO values: phase = target clock, modulo = reference clock*/ in dcn31_program_pix_clk()
991 /* Set DTO values: phase = target clock, modulo = reference clock*/ in dcn31_program_pix_clk()
995 /* Enable DTO */ in dcn31_program_pix_clk()
1055 /* Resync deep color DTO */ in dcn31_program_pix_clk()
1102 /* enable DP DTO */ in dcn401_program_pix_clk()
1111 /* disables DP DTO when provided with TMDS signal type */ in dcn401_program_pix_clk()
1157 /* Resync deep color DTO */ in dcn401_program_pix_clk()
1341 /* Set DTO values: phase = target clock, modulo = reference clock*/ in dcn3_program_pix_clk()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| D | dcn314_dccg.c | 210 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg314_set_dtbclk_dto()
233 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg314_set_dtbclk_dto()
234 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg314_set_dtbclk_dto()
235 * be set only after DTO is enabled in dccg314_set_dtbclk_dto()
340 /* turn off the DTO and leave phase/modulo at max */ in dccg314_dpp_root_clock_control()
346 /* turn on the DTO to generate a 0hz clock */ in dccg314_dpp_root_clock_control()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| D | dcn32_dccg.c | 209 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg32_set_dtbclk_dto()
232 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg32_set_dtbclk_dto()
233 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg32_set_dtbclk_dto()
234 * be set only after DTO is enabled in dccg32_set_dtbclk_dto()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| D | dcn35_dccg.c | 80 DPP_DCCG_DTO, // Functional clock selected is DTO tuned DPPCLK
132 DSC_DTO_TUNED_CK_GPU_DISCLK_3, // DTO divided clock selected as functional clock
1032 /* Switch DPP clock to DTO */ in dccg35_enable_dpp_clk_new()
1149 * Do not update the DPPCLK DTO if the clock is stopped. in dccg35_update_dpp_dto()
1355 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg35_set_dtbclk_dto()
1393 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg35_set_dtbclk_dto()
1394 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg35_set_dtbclk_dto()
1395 * be set only after DTO is enabled. in dccg35_set_dtbclk_dto()
1646 /* turn off the DTO and leave phase/modulo at max */ in dccg35_dpp_root_clock_control()
1653 /* turn on the DTO to generate a 0hz clock */ in dccg35_dpp_root_clock_control()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| D | dcn31_dccg.c | 52 * Do not update the DPPCLK DTO if the clock is stopped. in dccg31_update_dpp_dto()
360 //DTO must be enabled to generate a 0 Hz clock output in dccg31_disable_dscclk()
404 //Disable DTO in dccg31_enable_dscclk()
593 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg31_set_dtbclk_dto()
594 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg31_set_dtbclk_dto()
595 * be set only after DTO is enabled in dccg31_set_dtbclk_dto()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| D | dcn21_dccg.c | 57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
82 * DTO should be on to divide down un-used in dccg21_update_dpp_dto()
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| /linux-6.14.4/drivers/mmc/host/ |
| D | omap_hsmmc.c | 78 #define DTO 0xe macro
547 regval = regval | (clkdiv << 6) | (DTO << 16); in omap_hsmmc_set_clock()
938 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , in omap_hsmmc_dbg_report_irq()
1300 uint32_t reg, clkd, dto = 0; in set_data_timeout() local
1312 dto += 1; in set_data_timeout()
1315 dto = 31 - dto; in set_data_timeout()
1317 if (timeout && dto) in set_data_timeout()
1318 dto += 1; in set_data_timeout()
1319 if (dto >= 13) in set_data_timeout()
1320 dto -= 13; in set_data_timeout()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| D | dcn201_clk_mgr.c | 159 // if clock is being lowered, increase DTO before lowering refclk in dcn201_update_clocks()
163 // if clock is being raised, increase refclk before lowering DTO in dcn201_update_clocks()
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| /linux-6.14.4/drivers/infiniband/ulp/iser/ |
| D | iser_initiator.c | 44 * dto descriptor. Data size is stored in
85 * dto descriptor. Data size is stored in
355 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_command()
482 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_control()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/include/ |
| D | audio_types.h | 77 /* PLL information required for AZALIA DTO calculation */
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 278 /* use mask to program DTO once per tg */ in dcn32_update_clocks_update_dtb_dto()
292 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
295 * refclk and DPP DTO to not match up.
813 /* if clock is being lowered, increase DTO before lowering refclk */ in dcn32_update_clocks()
827 /* if clock is being raised, increase refclk before lowering DTO */ in dcn32_update_clocks()
831 * that we do not lower dto when it is not safe to lower. We do not need to in dcn32_update_clocks()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 302 /* if clock is being lowered, increase DTO before lowering refclk */ in dcn3_update_clocks()
306 /* if clock is being raised, increase refclk before lowering DTO */ in dcn3_update_clocks()
310 * that we do not lower dto when it is not safe to lower. We do not need to in dcn3_update_clocks()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 323 // if clock is being lowered, increase DTO before lowering refclk in dcn2_update_clocks()
327 // if clock is being raised, increase refclk before lowering DTO in dcn2_update_clocks()
387 * So take the higher value since the DPP DTO is typically programmed in dcn2_update_clocks_fpga()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr_vbios_smu.c | 155 /* TODO: add code for programing DP DTO, currently this is down by command table */ in rv1_vbios_smu_set_dprefclk()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.c | 102 * (DP DTO / DP Audio DTO and DP GTC)
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| /linux-6.14.4/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.yaml | 140 The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
145 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 214 // increase per DPP DTO before lowering global dppclk with requested dppclk in rn_update_clocks()
224 //update dpp dto with actual dpp clk. in rn_update_clocks()
232 // increase global DPPCLK before lowering per DPP DTO in rn_update_clocks()
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| D | rn_clk_mgr_vbios_smu.c | 176 /* TODO: add code for programing DP DTO, currently this is down by command table */ in rn_vbios_smu_set_dprefclk()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/bios/dce110/ |
| D | command_table_helper_dce110.c | 194 /* When programming DP DTO PLL ID should be invalid */ in clock_source_id_to_atom()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/bios/dce80/ |
| D | command_table_helper_dce80.c | 136 /* When programming DP DTO PLL ID should be invalid */ in clock_source_id_to_atom()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/bios/dce60/ |
| D | command_table_helper_dce60.c | 136 /* When programming DP DTO PLL ID should be invalid */ in clock_source_id_to_atom()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | dcn301_smu.c | 171 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn301_smu_set_dprefclk()
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| /linux-6.14.4/drivers/media/dvb-frontends/ |
| D | l64781.c | 227 l64781_readreg (state, 0x01); /* dto. */ in apply_frontend_param()
357 l64781_readreg (state, 0x01); /* dto. */ in l64781_read_status()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 225 // increase per DPP DTO before lowering global dppclk in dcn316_update_clocks()
229 // increase global DPPCLK before lowering per DPP DTO in dcn316_update_clocks()
|