| /linux-6.14.4/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gmu.c | 21 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
23 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
28 gmu->hung = true; in a6xx_gmu_fault()
39 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
42 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
43 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
46 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
48 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
52 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
55 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
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| D | a6xx_gmu.h | 35 * These define the different GMU wake up options - these define how both the
36 * CPU and the GMU bring up the hardware
39 /* THe GMU has already been booted and the rentention registers are active */
42 /* the GMU is coming up for the first time or back from a power collapse */
46 * These define the level of control that the GMU has - the higher the number
47 * the more things that the GMU hardware controls on its own.
50 /* The GMU does not do any idle state management */
53 /* The GMU manages SPTP power collapse */
56 /* The GMU does automatic IFPC (intra-frame power collapse) */
62 /* For serializing communication with the GMU: */
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| D | a6xx_hfi.c | 29 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
45 * If we are to assume that the GMU firmware is in fact a rational actor in a6xx_hfi_queue_read()
60 if (!gmu->legacy) in a6xx_hfi_queue_read()
67 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
91 if (!gmu->legacy) { in a6xx_hfi_queue_write()
99 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
103 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
106 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
111 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
115 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
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| D | a6xx_gpu.c | 24 /* Check that the GMU is idle */ in _a6xx_check_idle()
25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
221 * For PM4 the GMU register offsets are calculated from the base of the in a6xx_submit()
496 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
517 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a6xx_set_hwcg()
519 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a6xx_set_hwcg()
521 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a6xx_set_hwcg()
551 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
558 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1041 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
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| D | a6xx_gpu.h | 81 struct a6xx_gmu gmu; member
243 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
245 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
247 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
248 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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| D | a6xx_gpu_state.c | 155 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
1172 /* Read a block of GMU registers */
1181 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
1201 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
1203 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
1224 /* Get the CX GMU registers from AHB */ in a6xx_get_gmu_registers()
1230 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
1268 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
1271 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
1273 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
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| D | a6xx_hfi.h | 49 /* This is the outgoing queue to the GMU */
52 /* THis is the incoming response queue from the GMU */
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| D | a6xx_gpu_state.h | 345 /* GMU GX */
354 /* GMU CX */
364 /* GMU AO */
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| D | adreno_gpu.c | 540 /* Skip loading GMU firmware with GMU Wrapper */ in adreno_load_fw()
1107 /* Only handle the core clock when GMU is not in use (or is absent). */ in adreno_gpu_init()
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| /linux-6.14.4/Documentation/devicetree/bindings/display/msm/ |
| D | gmu.yaml | 6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
9 title: GMU attached to certain Adreno GPUs
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
49 - description: GMU HFI interrupt
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| D | gpu.yaml | 130 qcom,gmu:
133 For GMU attached devices a phandle to the GMU device that will
206 - const: gmu
207 description: CX GMU clock
227 then: # Starting with A6xx, the clocks are usually defined in the GMU node
291 // Example a6xx (with GMU):
328 qcom,gmu = <&gmu>;
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| /linux-6.14.4/arch/arm64/boot/dts/qcom/ |
| D | msm8992.dtsi | 31 gmu-sram@0 {
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| D | sdm670.dtsi | 1330 * controlled entirely by the GMU
1339 qcom,gmu = <&gmu>;
1446 gmu: gmu@506a000 { label
1447 compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";
1452 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1456 interrupt-names = "hfi", "gmu";
1462 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sar2130p.dtsi | 1647 qcom,gmu = <&gmu>;
1706 gmu: gmu@3d6a000 { label
1707 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
1711 reg-names = "gmu", "rscc", "gmu_pdc";
1715 interrupt-names = "hfi", "gmu";
1724 "gmu",
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| D | sm6350.dtsi | 1362 qcom,gmu = <&gmu>;
1446 gmu: gmu@3d6a000 { label
1447 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1451 reg-names = "gmu",
1458 "gmu";
1466 "gmu",
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| D | qcm2290.dtsi | 1451 "gmu",
1462 qcom,gmu = <&gmu_wrapper>;
1531 gmu_wrapper: gmu@596a000 {
1532 compatible = "qcom,adreno-gmu-wrapper";
1534 reg-names = "gmu";
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| D | sm8350.dtsi | 2045 qcom,gmu = <&gmu>;
2110 gmu: gmu@3d6a000 { label
2111 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2116 reg-names = "gmu", "rscc", "gmu_pdc";
2120 interrupt-names = "hfi", "gmu";
2129 clock-names = "gmu",
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| D | sc8180x.dtsi | 2277 qcom,gmu = <&gmu>;
2322 gmu: gmu@2c6a000 { label
2323 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2328 reg-names = "gmu",
2334 interrupt-names = "hfi", "gmu";
2341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sc7180.dtsi | 2171 qcom,gmu = <&gmu>;
2265 gmu: gmu@506a000 { label
2266 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2269 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2272 interrupt-names = "hfi", "gmu";
2277 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm6115.dtsi | 1711 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1722 "gmu",
1730 qcom,gmu = <&gmu_wrapper>;
1796 gmu_wrapper: gmu@596a000 {
1797 compatible = "qcom,adreno-gmu-wrapper";
1799 reg-names = "gmu";
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| /linux-6.14.4/Documentation/devicetree/bindings/sram/ |
| D | qcom,ocmem.yaml | 120 gmu-sram@0 {
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| /linux-6.14.4/drivers/clk/qcom/ |
| D | gdsc.c | 601 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
606 * the GMU crashes it could leave the GX on. In order to successfully bring back
615 * driver. During power up, nothing will happen from the CPU (and the GMU will
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| /linux-6.14.4/drivers/gpu/drm/ci/xfails/ |
| D | msm-sm8350-hdk-skips.txt | 29 # [ 200.950227] platform 3d6a000.gmu: [drm:a6xx_hfi_send_msg.constprop.0] *ERROR* Message HFI_H2F_…
34 # [ 204.213387] platform 3d6a000.gmu: GMU watchdog expired
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| /linux-6.14.4/Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 514 - const: gmu
523 - description: GMU clock
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| /linux-6.14.4/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-qcom.c | 38 { .compatible = "qcom,adreno-gmu",
355 { .compatible = "qcom,adreno-gmu" },
|