Searched full:harts (Results 1 – 25 of 27) sorted by relevance
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| /linux-6.14.4/arch/riscv/kernel/ |
| D | sbi.c | 80 * sbi_shutdown() - Remove all the harts from executing supervisor code.
324 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
325 * @cpu_mask: A cpu mask containing all the target harts.
338 * remote harts for a virtual address range belonging to a specific ASID or not.
340 * @cpu_mask: A cpu mask containing all the target harts.
364 * harts for the specified guest physical address range.
365 * @cpu_mask: A cpu mask containing all the target harts.
382 * remote harts for a guest physical address range belonging to a specific VMID.
384 * @cpu_mask: A cpu mask containing all the target harts.
403 * harts for the current guest virtual address range.
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| D | machine_kexec.c | 102 * harts and possibly devices etc) for a kexec reboot.
145 * executed. We assume at this point that all other harts are
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| D | cpu.c | 343 * denominator of extensions supported across all harts. A true list of in c_show()
367 * additional extensions not present across all harts. in c_show()
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| D | sys_hwprobe.c | 256 * extensions are supported on all harts, and only supports the in hwprobe_one_pair()
480 * all harts, then assume all CPUs are the same, and allow the vDSO to in init_hwprobe_vdso_data()
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| D | head.S | 175 * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT
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| D | process.c | 386 * Assume the supported PMLEN values are the same on all harts. in tagged_addr_init()
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| D | cpufeature.c | 876 * All "okay" harts should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_ext_list()
1003 pr_warn("Zicboz disabled as it is unavailable on some harts\n"); in riscv_user_isa_enable()
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| /linux-6.14.4/arch/riscv/mm/ |
| D | cacheflush.c | 37 * informs the remote harts they need to flush their local instruction caches.
40 * IPIs for harts that are not currently executing a MM context and instead
60 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
121 pr_warn("%s mismatched between harts %lu and %lu\n", in cbo_get_block_size()
169 * concurrently on different harts. in set_icache_stale_mask()
223 * across harts will not occur.
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| D | context.c | 211 * The mm_cpumask indicates which harts' TLBs contain the virtual in set_mm()
287 * shoot downs, so instead we send an IPI that informs the remote harts they
290 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /linux-6.14.4/drivers/acpi/riscv/ |
| D | rhct.c | 107 pr_warn("CBOM size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
114 pr_warn("CBOZ size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
121 pr_warn("CBOP size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
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| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,imsics.yaml | 22 which is same for given privilege level across CPUs (or HARTs).
26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).
73 This property represents the set of CPUs (or HARTs) for which given
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| D | riscv,aplic.yaml | 46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
114 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
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| D | thead,c900-aclint-sswi.yaml | 14 supervisor-level IPI functionality for a set of HARTs on a THEAD
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| D | riscv,cpu-intc.yaml | 31 present HARTs in the system.
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| D | sifive,plic-1.0.0.yaml | 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /linux-6.14.4/Documentation/arch/riscv/ |
| D | boot.rst | 68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
69 wins a lottery and executes the early boot code while the other harts are
73 initialization phase and then will start all other harts using the SBI HSM
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| D | uabi.rst | 49 RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
52 be present on all harts in the system.
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| /linux-6.14.4/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 24 having four harts.
115 thead systems where the vector register length is not identical on all harts, or
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| /linux-6.14.4/tools/testing/selftests/riscv/hwprobe/ |
| D | cbo.c | 152 ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n" in check_no_zicboz_cpus()
153 "Use taskset to select a set of harts where Zicboz\n" in check_no_zicboz_cpus()
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| /linux-6.14.4/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /linux-6.14.4/arch/csky/abiv2/ |
| D | cacheflush.c | 81 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
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| /linux-6.14.4/drivers/irqchip/ |
| D | irq-riscv-imsic-state.h | 49 /* Global configuration common for all HARTs */
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| /linux-6.14.4/Documentation/devicetree/bindings/iommu/ |
| D | riscv,iommu.yaml | 63 RISC-V HARTS. The cause to interrupt vector is software defined
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| /linux-6.14.4/drivers/clocksource/ |
| D | timer-riscv.c | 80 * It is guaranteed that all the timers across all the harts are synchronized
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| /linux-6.14.4/arch/riscv/kvm/ |
| D | aia.c | 633 * run on other HARTs in kvm_riscv_aia_disable()
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