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/aosp_15_r20/external/llvm/test/ObjectYAML/MachO/
H A Dlazy_bind_opcode.yaml66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h74 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
75 switch ((Imm >> 6) & 0x7) { in getShiftType()
86 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
87 return Imm & 0x3f; in getShiftValue()
91 /// imm: 6-bit shift amount
98 /// {5-0} = imm
100 unsigned Imm) { in getShifterImm() argument
101 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
111 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
119 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
/aosp_15_r20/external/virglrenderer/tests/
H A Dlarge_shader.h14 IMM[0] FLT32 {0x40000000, 0xbf800000, 0x00000000, 0x3f7fffff}
15 IMM[1] FLT32 {0xbf3504f4, 0x3f3504f4, 0x00000000, 0x3fb504f3}
16 IMM[2] FLT32 {0xbf87c3b7, 0x80000000, 0xbf733333, 0x41000000}
17 IMM[3] UINT32 {0, 4294967295, 0, 0}
18 IMM[4] INT32 {0, 32, 1, 0}
19 IMM[5] FLT32 {0x3f6e147b, 0x00000000, 0x40400000, 0x42e20000}
20 IMM[6] FLT32 {0x42640000, 0x3f000000, 0x472aee8c, 0x3f800000}
21 IMM[7] FLT32 {0x42680000, 0x42e40000, 0x432a0000, 0x432b0000}
22 IMM[8] FLT32 {0xbf19999a, 0xbef5c28f, 0x3f23d70a, 0x400147ae}
23 IMM[9] FLT32 {0xbf4ccccd, 0x3eb851ec, 0xbef5c28f, 0x3e800000}
[all …]
/aosp_15_r20/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
/aosp_15_r20/external/clang/lib/Headers/
H A Davx512bwintrin.h1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
[all …]
H A Davx2intrin.h498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-3289846/lib64/clang/3.8/include/
Davx512bwintrin.h1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
[all …]
Davx2intrin.h498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
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/aosp_15_r20/prebuilts/sdk/renderscript/clang-include/
H A Davx512bwintrin.h1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
[all …]
H A Davx2intrin.h498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm != 0);
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
44 int64_t Imm;
45 if (MCOp.evaluateAsConstantImm(Imm))
46 return isInt<6>(Imm);
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
32 int64_t Imm;
33 if (!MCOp.evaluateAsConstantImm(Imm))
36 return isUInt<6>(Imm) && (Imm != 0);
37 return isUInt<5>(Imm) && (Imm != 0);
41 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
48 int64_t Imm;
49 if (MCOp.evaluateAsConstantImm(Imm))
50 return isInt<6>(Imm);
[all …]
/aosp_15_r20/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrMemory.td83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
84 (LOAD_I32 imm:$off, $addr, 0)>;
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
86 (LOAD_I64 imm:$off, $addr, 0)>;
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
88 (LOAD_F32 imm:$off, $addr, 0)>;
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
90 (LOAD_F64 imm:$off, $addr, 0)>;
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
92 (LOAD_I32 imm:$off, $addr, 0)>;
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DARMInstrCDE.td16 let Name = "Imm"#width#"b";
21 ImmLeaf<i32, "{ return Imm >= 0 && Imm < (1 << "#width#"); }"> {
115 !con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
116 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
118 bits<13> imm;
122 let Inst{21-16} = imm{12-7};
124 let Inst{7} = imm{6};
125 let Inst{5-0} = imm{5-0};
131 !con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
[all …]
/aosp_15_r20/external/pcre/src/sljit/
H A DsljitNativePPC_64.c42 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
49 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
50 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
52 if (((sljit_uw)imm >> 16) == 0) in load_immediate()
53 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
55 if (imm <= 0x7fffffffl && imm >= -0x80000000l) { in load_immediate()
56 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
57 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
60 if (((sljit_uw)imm >> 32) == 0) { in load_immediate()
61 FAIL_IF(push_inst(compiler, ORIS | S(TMP_ZERO) | A(reg) | IMM(imm >> 16))); in load_immediate()
[all …]
/aosp_15_r20/external/mesa3d/src/gallium/auxiliary/postprocess/
H A Dpp_mlaa.h55 "IMM FLT32 { 0.0030, 0.0000, 1.0000, 0.0000}\n"
67 " 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx\n"
68 " 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz\n"
69 " 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy\n"
86 "IMM FLT32 { 0.2126, 0.7152, 0.0722, 0.1000}\n"
87 "IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000}\n"
89 " 1: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[0]\n"
91 " 3: DP3 TEMP[0].y, TEMP[1].xyzz, IMM[0].xyzz\n"
93 " 5: DP3 TEMP[0].z, TEMP[1].xyzz, IMM[0].xyzz\n"
95 " 7: DP3 TEMP[0].w, TEMP[1].xyzz, IMM[0].xyzz\n"
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td65 // b<cond> $imm
66 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
67 (BCOND brtarget:$imm, condVal)>;
69 // b<cond>,a $imm
70 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
71 (BCONDA brtarget:$imm, condVal)>;
73 // b<cond> %icc, $imm
74 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
75 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
77 // b<cond>,pt %icc, $imm
[all …]
/aosp_15_r20/external/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
[all …]
/aosp_15_r20/external/mesa3d/src/intel/compiler/elk/
H A Delk_fs_combine_constants.cpp834 struct imm { struct
893 struct imm *imm; member
952 * Comparator used for sorting an array of imm structures.
962 const struct imm *a = (const struct imm *)_a, in compare()
963 *b = (const struct imm *)_b; in compare()
977 build_imm_reg_for_copy(struct imm *imm) in build_imm_reg_for_copy() argument
979 switch (imm->size) { in build_imm_reg_for_copy()
981 return elk_imm_d(imm->d64); in build_imm_reg_for_copy()
983 return elk_imm_d(imm->d); in build_imm_reg_for_copy()
985 return elk_imm_w(imm->w); in build_imm_reg_for_copy()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td93 // b<cond> $imm
94 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
95 (BCOND brtarget:$imm, condVal)>;
97 // b<cond>,a $imm
98 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
99 (BCONDA brtarget:$imm, condVal)>;
101 // b<cond> %icc, $imm
102 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
103 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
105 // b<cond>,pt %icc, $imm
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp73 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand() local
74 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
75 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
126 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
127 if (Imm != 0) { in printOffset()
136 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printFlatOffset() local
137 if (Imm != 0) { in printFlatOffset()
206 auto Imm = MI->getOperand(OpNo).getImm(); in printCPol() local
207 if (Imm & CPol::GLC) in printCPol()
211 if (Imm & CPol::SLC) in printCPol()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td118 // Short jump targets have OtherVT type and are printed as pcrel imm values.
136 ImmLeaf<i8, [{return Imm == 0 || Imm == 1 || Imm == 2 ||
137 Imm == 4 || Imm == 8 || Imm == -1;}]> {
144 ImmLeaf<i16, [{return Imm == 0 || Imm == 1 || Imm == 2 ||
145 Imm == 4 || Imm == 8 || Imm == -1;}]> {
192 (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>;
196 (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
255 def Bi : I16ri<0b0100, (outs), (ins i16imm:$imm),
256 "br\t$imm",
257 [(brind tblockaddress:$imm)]>;
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td118 // Short jump targets have OtherVT type and are printed as pcrel imm values.
136 ImmLeaf<i8, [{return Imm == 0 || Imm == 1 || Imm == 2 ||
137 Imm == 4 || Imm == 8 || Imm == -1;}]> {
144 ImmLeaf<i16, [{return Imm == 0 || Imm == 1 || Imm == 2 ||
145 Imm == 4 || Imm == 8 || Imm == -1;}]> {
192 (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>;
196 (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
255 def Bi : I16ri<0b0100, (outs), (ins i16imm:$imm),
256 "br\t$imm",
257 [(brind tblockaddress:$imm)]>;
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp106 static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, in decodeCallOperand() argument
108 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeCallOperand()
109 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2))); in decodeCallOperand()
113 static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, in decodeJumpOperand() argument
115 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeJumpOperand()
116 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
120 static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, in decodeBranchOperand() argument
127 assert(isUInt<12>(Imm) && "Invalid immediate"); in decodeBranchOperand()
128 if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true, in decodeBranchOperand()
130 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeBranchOperand()
[all …]

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