| /linux-6.14.4/Documentation/PCI/ |
| D | msi-howto.rst | 15 This guide describes the basics of Message Signaled Interrupts (MSIs),
18 try if a device doesn't support MSIs.
21 What are MSIs?
36 Why use MSIs?
39 There are three reasons why using MSIs can give an advantage over
45 a whole. MSIs are never shared, so this problem cannot arise.
54 Using MSIs avoids this problem as the interrupt-generating write cannot
61 MSIs, a device can support more interrupts, allowing each interrupt
69 How to use MSIs
74 support MSIs correctly, and for those machines, the APIs described below
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| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 4 Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
7 MSIs were originally specified by PCI (and are used with PCIe), but may also be
12 MSIs are distinguished by some combination of:
57 MSI clients are devices which generate MSIs. For each MSI they wish to
67 This property is unordered, and MSIs may be allocated from any combination of
70 If a device has restrictions on the allocation of MSIs, these restrictions
75 and the set of MSIs they can potentially generate.
112 /* Can only generate MSIs to msi_a */
121 * Can generate MSIs to either A or B.
131 * Can generate MSIs to all of the MSI controllers.
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| D | riscv,imsics.yaml | 14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
20 space to receive MSIs from devices. Each IMSIC interrupt file supports a
21 fixed number of interrupt identities (to distinguish MSIs from devices)
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| D | riscv,aplic.yaml | 51 Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
151 // Example 2 (APLIC domains forwarding interrupts as MSIs):
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| D | marvell,sei.txt | 11 MSIs.
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| /linux-6.14.4/drivers/gpu/drm/radeon/ |
| D | radeon_irq_kms.c | 234 * MSIs should be enabled on a particular chip (all asics).
235 * Returns true if MSIs should be enabled, false if MSIs
244 /* MSIs don't work on AGP */ in radeon_msi_ok()
250 * of address for "64-bit" MSIs which breaks on some platforms, notably in radeon_msi_ok()
265 /* HP RS690 only seems to work with MSIs. */ in radeon_msi_ok()
271 /* Dell RS690 only seems to work with MSIs. */ in radeon_msi_ok()
277 /* Dell RS690 only seems to work with MSIs. */ in radeon_msi_ok()
283 /* Gateway RS690 only seems to work with MSIs. */ in radeon_msi_ok()
289 /* try and enable MSIs by default on all RS690s */ in radeon_msi_ok()
300 /* APUs work fine with MSIs */ in radeon_msi_ok()
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| /linux-6.14.4/Documentation/devicetree/bindings/pci/ |
| D | apple,pcie.yaml | 26 MSIs are handled by the PCIe controller and translated into regular
27 interrupts. A range of 32 MSIs is provided. These 32 MSIs can be
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| /linux-6.14.4/drivers/iommu/riscv/ |
| D | iommu-platform.c | 33 "uh oh, the IOMMU can't send MSIs to 0x%llx, sending to 0x%llx instead\n", in riscv_iommu_write_msi_msg()
90 dev_warn(dev, "failed to allocate MSIs\n"); in riscv_iommu_platform_probe()
103 dev_info(dev, "using MSIs\n"); in riscv_iommu_platform_probe()
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| D | iommu-pci.c | 67 /* The PCI driver only uses MSIs, make sure the IOMMU supports this */ in riscv_iommu_pci_probe()
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| /linux-6.14.4/arch/powerpc/platforms/pseries/ |
| D | msi.c | 90 pr_debug("rtas_msi: Setting MSIs to 0 failed!\n"); in rtas_disable_msi()
133 pr_debug("rtas_msi: %s requests < %d MSIs\n", prop_name, nvec); in check_req()
310 * use the remainder as spare MSIs for anyone that wants them. */ in msi_quota_for_device()
333 * fact that we using RTAS for MSIs, we don't have the 32 bit MSI RTAS in rtas_hack_32bit_msi_gen2()
650 pr_err("PCI: failed to find MSIs for bridge %pOF (domain %d)\n", in pseries_msi_allocate_domains()
670 /* No LSI -> leave MSIs (if any) configured */ in rtas_msi_pci_irq_fixup()
676 /* No MSI -> MSIs can't have been assigned by fw, leave LSI */ in rtas_msi_pci_irq_fixup()
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| /linux-6.14.4/Documentation/arch/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 24 partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
33 return all 1's value. MSIs are also blocked. There's a bit more state that
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
63 - For MSIs, we have two windows in the address space (one at the top of
91 reserved for MSIs but this is not a problem at this point; we just
152 "master PE" which is the one used for DMA, MSIs, etc., and "secondary
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| /linux-6.14.4/drivers/irqchip/ |
| D | irq-loongson-pch-msi.c | 26 u32 irq_first; /* The vector number that MSIs starts */
27 u32 num_irqs; /* The number of vectors for MSIs */
198 pr_debug("Registering %d MSIs, starting at %d\n", in pch_msi_init()
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| D | irq-gic-v3-its-msi-parent.c | 85 * minimum of 32 MSIs for DevID 0. If you want more because all in its_pci_msi_prepare()
154 /* Allocate at least 32 MSIs, and always as a power of 2 */ in its_pmsi_prepare()
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| D | irq-alpine-msi.c | 34 u32 spi_first; /* The SGI number that MSIs start */
35 u32 num_spis; /* The number of SGIs for MSIs */
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| /linux-6.14.4/Documentation/devicetree/bindings/iommu/ |
| D | riscv,iommu.yaml | 112 /* Example 3 (IOMMU device with MSIs) */
121 /* Example 4 (IOMMU PCIe device with MSIs) */
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| /linux-6.14.4/arch/x86/platform/uv/ |
| D | uv_irq.c | 120 * on the specified blade to allow the sending of MSIs to the specified CPU.
130 * Disable the specified MMR located on the specified blade so that MSIs are
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| /linux-6.14.4/include/asm-generic/ |
| D | msi.h | 34 /* Device generating MSIs is proxying for another device */
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| /linux-6.14.4/Documentation/virt/kvm/devices/ |
| D | mpic.rst | 30 MSIs may be signaled by using this attribute group to write
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| /linux-6.14.4/Documentation/accel/qaic/ |
| D | qaic.rst | 21 non-empty and generate MSIs at a rate equivalent to the speed of the
24 MSIs per second. It has been observed that most systems cannot tolerate this
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| /linux-6.14.4/Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 15 The FlexRM engine will send MSIs (instead of wired
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| /linux-6.14.4/include/uapi/linux/ |
| D | vfio_zdev.h | 50 __u16 noi; /* Maximum number of MSIs */
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| /linux-6.14.4/arch/x86/kernel/ |
| D | irq.c | 359 /* Posted Interrupt Descriptors for coalesced MSIs to be posted */
442 * For MSIs that are delivered as posted interrupts, the CPU notifications
443 * can be coalesced if the MSIs arrive in high frequency bursts.
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| /linux-6.14.4/drivers/pci/msi/ |
| D | msi.c | 23 * @nvec: how many MSIs have been requested?
41 * You can't ask to have 0 or less MSIs configured. in pci_msi_supported()
295 /* Lies, damned lies, and MSIs */ in msi_setup_msi_desc()
377 /* All MSIs are unmasked by default; mask them all */ in msi_capability_init()
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| /linux-6.14.4/drivers/iommu/intel/ |
| D | irq_remapping.c | 498 /* Block compatibility-format MSIs */ in iommu_enable_irq_remapping()
1290 * With posted MSIs, the MSI vectors are multiplexed into a single notification
1292 * MSIs are then dispatched in a demux loop that harvests the MSIs from the
1293 * CPU's Posted Interrupt Request bitmap. I.e. Posted MSIs never get sent to
1300 * For the example below, 3 MSIs are coalesced into one CPU notification. Only
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| /linux-6.14.4/arch/x86/include/asm/ |
| D | irq_vectors.h | 101 * Posted interrupt notification vector for all device MSIs delivered to
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