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/linux-6.14.4/Documentation/devicetree/bindings/arm/
Dpmu.yaml4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/samsung/
Dexynos-pmu.yaml4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
7 title: Samsung Exynos SoC series Power Management Unit (PMU)
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
23 - samsung,exynos5250-pmu
24 - samsung,exynos5260-pmu
25 - samsung,exynos5410-pmu
[all …]
/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dbase.c32 struct nvkm_pmu *pmu = device->pmu; in nvkm_pmu_fan_controlled() local
34 /* Internal PMU FW does not currently control fans in any way, in nvkm_pmu_fan_controlled()
37 if (pmu && pmu->func->code.size) in nvkm_pmu_fan_controlled()
40 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi in nvkm_pmu_fan_controlled()
48 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) in nvkm_pmu_pgob() argument
50 if (pmu && pmu->func->pgob) in nvkm_pmu_pgob()
51 pmu->func->pgob(pmu, enable); in nvkm_pmu_pgob()
57 struct nvkm_pmu *pmu = container_of(work, typeof(*pmu), recv.work); in nvkm_pmu_recv() local
58 return pmu->func->recv(pmu); in nvkm_pmu_recv()
62 nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in nvkm_pmu_send() argument
[all …]
Dgm20b.c28 #include <nvfw/pmu.h>
42 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); in gm20b_pmu_acr_bootstrap_falcon() local
52 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_bootstrap_falcon()
54 &pmu->subdev, msecs_to_jiffies(1000)); in gm20b_pmu_acr_bootstrap_falcon()
129 struct nvkm_pmu *pmu = priv; in gm20b_pmu_acr_init_wpr_callback() local
130 struct nvkm_subdev *subdev = &pmu->subdev; in gm20b_pmu_acr_init_wpr_callback()
139 complete_all(&pmu->wpr_ready); in gm20b_pmu_acr_init_wpr_callback()
144 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu) in gm20b_pmu_acr_init_wpr() argument
154 return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_init_wpr()
155 gm20b_pmu_acr_init_wpr_callback, pmu, 0); in gm20b_pmu_acr_init_wpr()
[all …]
Dgt215.c30 gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in gt215_pmu_send() argument
33 struct nvkm_subdev *subdev = &pmu->subdev; in gt215_pmu_send()
37 mutex_lock(&pmu->send.mutex); in gt215_pmu_send()
45 mutex_unlock(&pmu->send.mutex); in gt215_pmu_send()
50 * on a synchronous reply, take the PMU mutex and tell the in gt215_pmu_send()
54 pmu->recv.message = message; in gt215_pmu_send()
55 pmu->recv.process = process; in gt215_pmu_send()
65 pmu->send.base)); in gt215_pmu_send()
77 wait_event(pmu->recv.wait, (pmu->recv.process == 0)); in gt215_pmu_send()
78 reply[0] = pmu->recv.data[0]; in gt215_pmu_send()
[all …]
/linux-6.14.4/Documentation/admin-guide/perf/
Dmrvl-odyssey-ddr-pmu.rst2 Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)
16 The PMU driver exposes the available events and format options under sysfs::
24 mrvl_ddr_pmu_<>/ddr_act_bypass_access/ [Kernel PMU event]
25 mrvl_ddr_pmu_<>/ddr_bsm_alloc/ [Kernel PMU event]
26 mrvl_ddr_pmu_<>/ddr_bsm_starvation/ [Kernel PMU event]
27 mrvl_ddr_pmu_<>/ddr_cam_active_access/ [Kernel PMU event]
28 mrvl_ddr_pmu_<>/ddr_cam_mwr/ [Kernel PMU event]
29 mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
30 mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
31 mrvl_ddr_pmu_<>/ddr_cam_read/ [Kernel PMU event]
[all …]
Dmrvl-pem-pmu.rst2 Marvell Odyssey PEM Performance Monitoring Unit (PMU UNCORE)
20 The PMU driver exposes the available events and format options under sysfs,
27 mrvl_pcie_rc_pmu_<>/ats_inv/ [Kernel PMU event]
28 mrvl_pcie_rc_pmu_<>/ats_inv_latency/ [Kernel PMU event]
29 mrvl_pcie_rc_pmu_<>/ats_pri/ [Kernel PMU event]
30 mrvl_pcie_rc_pmu_<>/ats_pri_latency/ [Kernel PMU event]
31 mrvl_pcie_rc_pmu_<>/ats_trans/ [Kernel PMU event]
32 mrvl_pcie_rc_pmu_<>/ats_trans_latency/ [Kernel PMU event]
33 mrvl_pcie_rc_pmu_<>/ib_inflight/ [Kernel PMU event]
34 mrvl_pcie_rc_pmu_<>/ib_reads/ [Kernel PMU event]
[all …]
/linux-6.14.4/tools/perf/util/
Dpmus.c17 #include "pmu.h"
24 * core_pmus: A PMU belongs to core_pmus if it's name is "cpu" or it's sysfs
26 * must have pmu->is_core=1. If there are more than one PMU in
29 * homogeneous PMU, and thus they are treated as homogeneous
32 * matter whether PMU is present per SMT-thread or outside of the
36 * must have pmu->is_core=0 but pmu->is_uncore could be 0 or 1.
78 * that S390's cpum_cf PMU doesn't match. in pmu_name_len_no_suffix()
108 struct perf_pmu *pmu, *tmp; in perf_pmus__destroy() local
110 list_for_each_entry_safe(pmu, tmp, &core_pmus, list) { in perf_pmus__destroy()
111 list_del(&pmu->list); in perf_pmus__destroy()
[all …]
Dpmu.c21 #include "pmu.h"
25 #include <util/pmu-bison.h>
26 #include <util/pmu-flex.h>
39 /* An event loaded from /sys/bus/event_source/devices/<pmu>/events. */
44 * An event loaded from a /sys/bus/event_source/devices/<pmu>/identifier matched json
52 * pmu-events.c, created by parsing the pmu-events json files.
72 * differ from the PMU name as it won't have suffixes.
127 static int pmu_aliases_parse(struct perf_pmu *pmu);
170 static void perf_pmu_format__load(const struct perf_pmu *pmu, struct perf_pmu_format *format) in perf_pmu_format__load() argument
178 if (!perf_pmu__pathname_scnprintf(path, sizeof(path), pmu->name, "format")) in perf_pmu_format__load()
[all …]
Dpmu.h12 #include "pmu-events/pmu-events.h"
52 /** @name: The name of the PMU such as "cpu". */
55 * @alias_name: Optional alternate name for the PMU determined in
60 * @id: Optional PMU identifier read from
70 * @selectable: Can the PMU name be selected as if it were an event?
74 * @is_core: Is the PMU the core CPU PMU? Determined by the name being
77 * PMU on systems like Intel hybrid.
81 * @is_uncore: Is the PMU not within the CPU core? Determined by the
91 * @formats_checked: Only check PMU's formats are valid for
101 * PMU, read from
[all …]
/linux-6.14.4/drivers/soc/dove/
Dpmu.c3 * Marvell Dove PMU support
17 #include <linux/soc/dove/pmu.h>
42 * The PMU contains a register to reset various subsystems within the
50 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_reset() local
54 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_reset()
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
57 writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
58 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_reset()
65 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_assert() local
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/
Di915_pmu.c36 return container_of(event->pmu, struct i915_pmu, base); in event_to_pmu()
39 static struct drm_i915_private *pmu_to_i915(struct i915_pmu *pmu) in pmu_to_i915() argument
41 return container_of(pmu, struct drm_i915_private, pmu); in pmu_to_i915()
152 static bool pmu_needs_timer(struct i915_pmu *pmu) in pmu_needs_timer() argument
154 struct drm_i915_private *i915 = pmu_to_i915(pmu); in pmu_needs_timer()
162 enable = pmu->enable; in pmu_needs_timer()
204 static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample) in read_sample() argument
206 return pmu->sample[gt_id][sample].cur; in read_sample()
210 store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val) in store_sample() argument
212 pmu->sample[gt_id][sample].cur = val; in store_sample()
[all …]
/linux-6.14.4/drivers/perf/
Dfsl_imx8_ddr_perf.c52 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
66 const char *identifier; /* system PMU identifier for userspace */
101 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
102 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
103 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
104 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
105 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
106 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
107 { .compatible = "fsl,imx8dxl-ddr-pmu", .data = &imx8dxl_devtype_data},
113 struct pmu pmu; member
[all …]
Dfsl_imx9_ddr_perf.c59 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
79 const char *identifier; /* system PMU identifier for userspace */
84 struct pmu pmu; member
112 static inline bool axi_filter_v1(struct ddr_pmu *pmu) in axi_filter_v1() argument
114 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; in axi_filter_v1()
117 static inline bool axi_filter_v2(struct ddr_pmu *pmu) in axi_filter_v2() argument
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; in axi_filter_v2()
123 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
124 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
125 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
[all …]
Dmarvell_cn10k_ddr_pmu.c148 struct pmu pmu; member
161 void (*enable_read_freerun_counter)(struct cn10k_ddr_pmu *pmu,
163 void (*enable_write_freerun_counter)(struct cn10k_ddr_pmu *pmu,
165 void (*clear_read_freerun_counter)(struct cn10k_ddr_pmu *pmu);
166 void (*clear_write_freerun_counter)(struct cn10k_ddr_pmu *pmu);
167 void (*pmu_overflow_handler)(struct cn10k_ddr_pmu *pmu, int evt_idx);
170 #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
365 struct cn10k_ddr_pmu *pmu = dev_get_drvdata(dev); in cn10k_ddr_perf_cpumask_show() local
367 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in cn10k_ddr_perf_cpumask_show()
438 static int cn10k_ddr_perf_alloc_counter(struct cn10k_ddr_pmu *pmu, in cn10k_ddr_perf_alloc_counter() argument
[all …]
DKconfig10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
60 bool "ARM PMU framework"
80 bool "RISC-V PMU framework"
84 systems. This provides the core PMU framework that abstracts common
[all …]
Darm_pmu_platform.c25 static int probe_current_pmu(struct arm_pmu *pmu, in probe_current_pmu() argument
32 pr_info("probing PMU on CPU %d\n", cpu); in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
45 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq) in pmu_parse_percpu_irq() argument
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
95 static int pmu_parse_irqs(struct arm_pmu *pmu) in pmu_parse_irqs() argument
98 struct platform_device *pdev = pmu->plat_device; in pmu_parse_irqs()
99 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_irqs()
[all …]
/linux-6.14.4/drivers/pmdomain/starfive/
Djh71xx-pmu.c3 * StarFive JH71XX PMU (Power Management Unit) Controller Driver
15 #include <dt-bindings/power/starfive,jh7110-pmu.h>
26 /* aon pmu register offset */
36 /* pmu int status */
64 struct jh71xx_pmu *pmu);
76 spinlock_t lock; /* protects pmu reg */
81 struct jh71xx_pmu *pmu; member
87 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state() local
92 *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; in jh71xx_pmu_get_state()
99 struct jh71xx_pmu *pmu = pmd->pmu; in jh7110_pmu_set_state() local
[all …]
/linux-6.14.4/arch/x86/kvm/svm/
Dpmu.c3 * KVM PMU support for AMD
20 #include "pmu.h"
28 static struct kvm_pmc *amd_pmu_get_pmc(struct kvm_pmu *pmu, int pmc_idx) in amd_pmu_get_pmc() argument
30 unsigned int num_counters = pmu->nr_arch_gp_counters; in amd_pmu_get_pmc()
35 return &pmu->gp_counters[array_index_nospec(pmc_idx, num_counters)]; in amd_pmu_get_pmc()
38 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr, in get_gp_pmc_amd() argument
41 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); in get_gp_pmc_amd()
52 * Each PMU counter has a pair of CTL and CTR MSRs. CTLn in get_gp_pmc_amd()
73 return amd_pmu_get_pmc(pmu, idx); in get_gp_pmc_amd()
78 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); in amd_check_rdpmc_early() local
[all …]
/linux-6.14.4/drivers/perf/amlogic/
Dmeson_ddr_pmu_core.c21 struct pmu pmu; member
35 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
38 static void dmc_pmu_enable(struct ddr_pmu *pmu) in dmc_pmu_enable() argument
40 if (!pmu->pmu_enabled) in dmc_pmu_enable()
41 pmu->info.hw_info->enable(&pmu->info); in dmc_pmu_enable()
43 pmu->pmu_enabled = true; in dmc_pmu_enable()
46 static void dmc_pmu_disable(struct ddr_pmu *pmu) in dmc_pmu_disable() argument
48 if (pmu->pmu_enabled) in dmc_pmu_disable()
49 pmu->info.hw_info->disable(&pmu->info); in dmc_pmu_disable()
51 pmu->pmu_enabled = false; in dmc_pmu_disable()
[all …]
/linux-6.14.4/arch/x86/kvm/vmx/
Dpmu_intel.c3 * KVM PMU support for Intel CPUs
21 #include "pmu.h"
37 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) in reprogram_fixed_counters() argument
40 u64 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; in reprogram_fixed_counters()
43 pmu->fixed_ctr_ctrl = data; in reprogram_fixed_counters()
44 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { in reprogram_fixed_counters()
51 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); in reprogram_fixed_counters()
53 __set_bit(KVM_FIXED_PMC_BASE_IDX + i, pmu->pmc_in_use); in reprogram_fixed_counters()
62 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); in intel_rdpmc_ecx_to_pmc() local
74 * Yell and reject attempts to read PMCs for a non-architectural PMU, in intel_rdpmc_ecx_to_pmc()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/rockchip/
Dpmu.yaml4 $id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
7 title: Rockchip Power Management Unit (PMU)
14 The PMU is used to turn on and off different power domains of the SoCs.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
24 - rockchip,rk3128-pmu
25 - rockchip,rk3288-pmu
26 - rockchip,rk3368-pmu
27 - rockchip,rk3399-pmu
28 - rockchip,rk3568-pmu
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
14 Note: pmu* also allows for Power Management functions listed below
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
21 uart1(rts), pmu*
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
[all …]
/linux-6.14.4/arch/x86/events/amd/
Duncore.c51 struct pmu pmu; member
88 return container_of(event->pmu, struct amd_uncore_pmu, pmu); in event_to_amd_uncore_pmu()
139 event->pmu->read(event); in amd_uncore_stop()
147 struct amd_uncore_pmu *pmu = event_to_amd_uncore_pmu(event); in amd_uncore_add() local
148 struct amd_uncore_ctx *ctx = *per_cpu_ptr(pmu->ctx, event->cpu); in amd_uncore_add()
155 for (i = 0; i < pmu->num_counters; i++) { in amd_uncore_add()
164 for (i = 0; i < pmu->num_counters; i++) { in amd_uncore_add()
177 hwc->config_base = pmu->msr_base + (2 * hwc->idx); in amd_uncore_add()
178 hwc->event_base = pmu->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
179 hwc->event_base_rdpmc = pmu->rdpmc_base + hwc->idx; in amd_uncore_add()
[all …]
/linux-6.14.4/tools/perf/arch/arm/util/
Dpmu.c8 #include <linux/coresight-pmu.h>
15 #include "../../../util/pmu.h"
19 void perf_pmu__arch_init(struct perf_pmu *pmu) in perf_pmu__arch_init() argument
24 if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { in perf_pmu__arch_init()
26 pmu->auxtrace = true; in perf_pmu__arch_init()
27 pmu->selectable = true; in perf_pmu__arch_init()
28 pmu->perf_event_attr_init_default = cs_etm_get_default_config; in perf_pmu__arch_init()
30 } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { in perf_pmu__arch_init()
31 pmu->auxtrace = true; in perf_pmu__arch_init()
32 pmu->selectable = true; in perf_pmu__arch_init()
[all …]

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