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/linux-6.14.4/arch/mips/include/asm/
Dpgtable.h45 extern void __update_cache(unsigned long address, pte_t pte);
111 # define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL)) argument
113 # define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) argument
116 #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) argument
117 #define pte_no_exec(pte) ((pte).pte_low & _PAGE_NO_EXEC) argument
119 static inline void set_pte(pte_t *ptep, pte_t pte) argument
121 ptep->pte_high = pte.pte_high;
123 ptep->pte_low = pte.pte_low;
126 if (pte.pte_high & _PAGE_GLOBAL) {
128 if (pte.pte_low & _PAGE_GLOBAL) {
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/linux-6.14.4/arch/m68k/include/asm/
Dmcf_pgtable.h10 * after masking from the pte.
105 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
107 pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
108 return pte; in pte_modify()
118 #define __pte_page(pte) ((void *) (pte_val(pte) & PAGE_MASK)) argument
121 static inline int pte_none(pte_t pte) in pte_none() argument
123 return !pte_val(pte); in pte_none()
126 static inline int pte_present(pte_t pte) in pte_present() argument
128 return pte_val(pte) & CF_PAGE_VALID; in pte_present()
137 #define pte_page(pte) virt_to_page(__pte_page(pte)) argument
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Dsun3_pgtable.h29 /* Page protection values within PTE. */
85 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
87 pte_val(pte) = (pte_val(pte) & SUN3_PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
88 return pte; in pte_modify()
93 #define __pte_page(pte) \ argument
94 (__va ((pte_val (pte) & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT))
101 static inline int pte_none (pte_t pte) { return !pte_val (pte); } in pte_none() argument
102 static inline int pte_present (pte_t pte) { return pte_val (pte) & SUN3_PAGE_VALID; } in pte_present() argument
109 #define pte_pfn(pte) (pte_val(pte) & SUN3_PAGE_PGNUM_MASK) argument
113 #define pte_page(pte) virt_to_page(__pte_page(pte)) argument
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Dmotorola_pgtable.h90 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
92 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
93 return pte; in pte_modify()
106 #define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK)) argument
111 #define pte_none(pte) (!pte_val(pte)) argument
112 #define pte_present(pte) (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE)) argument
116 #define pte_page(pte) virt_to_page(__va(pte_val(pte))) argument
117 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) argument
141 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
152 static inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); } in pte_write() argument
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/linux-6.14.4/arch/hexagon/include/asm/
Dpgtable.h21 * The PTE model described here is that of the Hexagon Virtual Machine,
30 * To maximize the comfort level for the PTE manipulation macros,
39 * We have a total of 4 "soft" bits available in the abstract PTE.
43 * the PTE describes MMU programming or swap space.
99 /* Any bigger and the PTE disappears. */
136 #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE) argument
143 extern void sync_icache_dcache(pte_t pte);
145 #define pte_present_exec_user(pte) \ argument
146 ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \
160 * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE
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/linux-6.14.4/arch/powerpc/include/asm/nohash/
Dpgtable.h35 static inline unsigned long pte_huge_size(pte_t pte) in pte_huge_size() argument
42 * PTE updates. This function is called whenever an existing
43 * valid PTE is updated. This does -not- include set_pte_at()
44 * which nowadays only sets a new PTE.
47 * and the PTE may be either 32 or 64 bit wide. In the later case,
48 * when using atomic updates, only the low part of the PTE is
134 /* Set the dirty and/or accessed bits atomically in a linux PTE */
151 /* Generic accessors to PTE bits */
153 static inline pte_t pte_mkwrite_novma(pte_t pte) in pte_mkwrite_novma() argument
158 return __pte(pte_val(pte) | _PAGE_RW); in pte_mkwrite_novma()
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/linux-6.14.4/arch/powerpc/kvm/
Dbook3s_mmu_hpte.c56 void kvmppc_mmu_hpte_cache_map(struct kvm_vcpu *vcpu, struct hpte_cache *pte) in kvmppc_mmu_hpte_cache_map() argument
61 trace_kvm_book3s_mmu_map(pte); in kvmppc_mmu_hpte_cache_map()
66 index = kvmppc_mmu_hash_pte(pte->pte.eaddr); in kvmppc_mmu_hpte_cache_map()
67 hlist_add_head_rcu(&pte->list_pte, &vcpu3s->hpte_hash_pte[index]); in kvmppc_mmu_hpte_cache_map()
70 index = kvmppc_mmu_hash_pte_long(pte->pte.eaddr); in kvmppc_mmu_hpte_cache_map()
71 hlist_add_head_rcu(&pte->list_pte_long, in kvmppc_mmu_hpte_cache_map()
75 index = kvmppc_mmu_hash_vpte(pte->pte.vpage); in kvmppc_mmu_hpte_cache_map()
76 hlist_add_head_rcu(&pte->list_vpte, &vcpu3s->hpte_hash_vpte[index]); in kvmppc_mmu_hpte_cache_map()
79 index = kvmppc_mmu_hash_vpte_long(pte->pte.vpage); in kvmppc_mmu_hpte_cache_map()
80 hlist_add_head_rcu(&pte->list_vpte_long, in kvmppc_mmu_hpte_cache_map()
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/linux-6.14.4/arch/arm64/include/asm/
Dpgtable.h69 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
76 static inline phys_addr_t __pte_to_phys(pte_t pte) in __pte_to_phys() argument
78 pte_val(pte) &= ~PTE_MAYBE_SHARED; in __pte_to_phys()
79 return (pte_val(pte) & PTE_ADDR_LOW) | in __pte_to_phys()
80 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); in __pte_to_phys()
87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) argument
91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) argument
95 #define pte_none(pte) (!pte_val(pte)) argument
98 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) argument
103 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) argument
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/linux-6.14.4/arch/arm/include/asm/
Dpgtable.h61 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) argument
168 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) argument
171 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) argument
176 #define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \ argument
177 : !!(pte_val(pte) & (val)))
178 #define pte_isclear(pte, val) (!(pte_val(pte) & (val))) argument
180 #define pte_none(pte) (!pte_val(pte)) argument
181 #define pte_present(pte) (pte_isset((pte), L_PTE_PRESENT)) argument
182 #define pte_valid(pte) (pte_isset((pte), L_PTE_VALID)) argument
183 #define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) argument
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/linux-6.14.4/arch/csky/include/asm/
Dpgtable.h27 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
36 #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) argument
37 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) argument
42 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) argument
85 static inline void set_pte(pte_t *p, pte_t pte) in set_pte() argument
87 *p = pte; in set_pte()
141 static inline int pte_read(pte_t pte) in pte_read() argument
143 return pte.pte_low & _PAGE_READ; in pte_read()
146 static inline int pte_write(pte_t pte) in pte_write() argument
148 return (pte).pte_low & _PAGE_WRITE; in pte_write()
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/linux-6.14.4/arch/um/include/asm/
Dpgtable.h111 static inline int pte_none(pte_t pte) in pte_none() argument
113 return pte_is_zero(pte); in pte_none()
120 static inline int pte_read(pte_t pte) in pte_read() argument
122 return((pte_get_bits(pte, _PAGE_USER)) && in pte_read()
123 !(pte_get_bits(pte, _PAGE_PROTNONE))); in pte_read()
126 static inline int pte_exec(pte_t pte){ in pte_exec() argument
127 return((pte_get_bits(pte, _PAGE_USER)) && in pte_exec()
128 !(pte_get_bits(pte, _PAGE_PROTNONE))); in pte_exec()
131 static inline int pte_write(pte_t pte) in pte_write() argument
133 return((pte_get_bits(pte, _PAGE_RW)) && in pte_write()
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/linux-6.14.4/arch/microblaze/include/asm/
Dpgtable.h84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
108 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
115 * Bits in a linux-style PTE. These match the bits in the
116 * (hardware-defined) PTE as closely as possible.
125 * Where possible we make the Linux PTE bits match up with this
138 * - All other bits of the PTE are loaded into TLBLO without
140 * software PTE bits. We actually use bits 21, 24, 25, and
147 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
181 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
182 * to have it in the Linux PTE, and in fact the bit could be reused for
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/linux-6.14.4/arch/openrisc/include/asm/
Dpgtable.h44 /* Certain architectures need to do special things when pte's
102 * An OR32 PTE looks like this:
117 * PTE as per above
120 #define _PAGE_CC 0x001 /* software: pte contains a translation */
217 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } in pte_read() argument
218 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } in pte_write() argument
219 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } in pte_exec() argument
220 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty() argument
221 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young() argument
223 static inline pte_t pte_wrprotect(pte_t pte) in pte_wrprotect() argument
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/linux-6.14.4/arch/nios2/include/asm/
Dpgtable.h87 static inline int pte_write(pte_t pte) \ in pte_write() argument
88 { return pte_val(pte) & _PAGE_WRITE; } in pte_write()
89 static inline int pte_dirty(pte_t pte) \ in pte_dirty() argument
90 { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty()
91 static inline int pte_young(pte_t pte) \ in pte_young() argument
92 { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young()
105 static inline int pte_none(pte_t pte) in pte_none() argument
107 return !(pte_val(pte) & ~(_PAGE_GLOBAL|0xf)); in pte_none()
110 static inline int pte_present(pte_t pte) \ in pte_present() argument
111 { return pte_val(pte) & _PAGE_PRESENT; } in pte_present()
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/linux-6.14.4/drivers/iommu/amd/
Dio_pgtable_v2.c44 static inline bool is_large_pte(u64 pte) in is_large_pte() argument
46 return (pte & IOMMU_PAGE_PSE); in is_large_pte()
59 static inline void *get_pgtable_pte(u64 pte) in get_pgtable_pte() argument
61 return iommu_phys_to_virt(pte & PM_ADDR_MASK); in get_pgtable_pte()
66 u64 pte; in set_pte_attr() local
68 pte = __sme_set(paddr & PM_ADDR_MASK); in set_pte_attr()
69 pte |= IOMMU_PAGE_PRESENT | IOMMU_PAGE_USER; in set_pte_attr()
70 pte |= IOMMU_PAGE_ACCESS | IOMMU_PAGE_DIRTY; in set_pte_attr()
73 pte |= IOMMU_PAGE_RW; in set_pte_attr()
77 pte |= IOMMU_PAGE_PSE; in set_pte_attr()
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Dio_pgtable.c28 * Helper function to get the first pte of a large mapping
30 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size, in first_pte_l7() argument
36 pg_size = PTE_PAGE_SIZE(*pte); in first_pte_l7()
39 fpte = (u64 *)(((unsigned long)pte) & pte_mask); in first_pte_l7()
70 /* PTE present? */ in free_pt_lvl()
74 /* Large PTE? */ in free_pt_lvl()
129 u64 *pte; in increase_address_space() local
131 pte = iommu_alloc_page_node(cfg->amd.nid, gfp); in increase_address_space()
132 if (!pte) in increase_address_space()
145 *pte = PM_LEVEL_PDE(pgtable->mode, iommu_virt_to_phys(pgtable->root)); in increase_address_space()
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/linux-6.14.4/drivers/iommu/intel/
Dpasid.c242 struct pasid_entry *pte; in intel_pasid_tear_down_entry() local
246 pte = intel_pasid_get_entry(dev, pasid); in intel_pasid_tear_down_entry()
247 if (WARN_ON(!pte)) { in intel_pasid_tear_down_entry()
252 if (!pasid_pte_is_present(pte)) { in intel_pasid_tear_down_entry()
253 if (!pasid_pte_is_fault_disabled(pte)) { in intel_pasid_tear_down_entry()
254 WARN_ON(READ_ONCE(pte->val[0]) != 0); in intel_pasid_tear_down_entry()
265 pasid_clear_entry(pte); in intel_pasid_tear_down_entry()
272 did = pasid_get_domain_id(pte); in intel_pasid_tear_down_entry()
273 pgtt = pasid_pte_get_pgtt(pte); in intel_pasid_tear_down_entry()
278 clflush_cache_range(pte, sizeof(*pte)); in intel_pasid_tear_down_entry()
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/linux-6.14.4/include/asm-generic/
Dhugetlb.h13 static inline unsigned long huge_pte_write(pte_t pte) in huge_pte_write() argument
15 return pte_write(pte); in huge_pte_write()
18 static inline unsigned long huge_pte_dirty(pte_t pte) in huge_pte_dirty() argument
20 return pte_dirty(pte); in huge_pte_dirty()
23 static inline pte_t huge_pte_mkwrite(pte_t pte) in huge_pte_mkwrite() argument
25 return pte_mkwrite_novma(pte); in huge_pte_mkwrite()
29 static inline pte_t huge_pte_wrprotect(pte_t pte) in huge_pte_wrprotect() argument
31 return pte_wrprotect(pte); in huge_pte_wrprotect()
35 static inline pte_t huge_pte_mkdirty(pte_t pte) in huge_pte_mkdirty() argument
37 return pte_mkdirty(pte); in huge_pte_mkdirty()
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/linux-6.14.4/arch/powerpc/include/asm/book3s/32/
Dpgtable.h21 #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
22 #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
35 /* We never clear the high word of the pte */
53 * Location of the PFN in the PTE. Most 32-bit platforms use the same
111 /* Bits to mask out from a PMD to get to the PTE page */
120 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
125 * level has 2048 entries and the second level has 512 64-bit PTE entries.
212 * Bits in a linux-style PTE. These match the bits in the
213 * (hardware-defined) PowerPC PTE as closely as possible.
250 * PTE updates. This function is called whenever an existing
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/linux-6.14.4/arch/powerpc/mm/
Dpgtable.c29 #include <asm/pte-walk.h>
45 * reasonably "normal" PTEs. We currently require a PTE to be present
46 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
49 static inline int pte_looks_normal(pte_t pte, unsigned long addr) in pte_looks_normal() argument
52 if (pte_present(pte) && !pte_special(pte)) { in pte_looks_normal()
53 if (pte_ci(pte)) in pte_looks_normal()
61 static struct folio *maybe_pte_to_folio(pte_t pte) in maybe_pte_to_folio() argument
63 unsigned long pfn = pte_pfn(pte); in maybe_pte_to_folio()
82 static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr) in set_pte_filter_hash() argument
84 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); in set_pte_filter_hash()
[all …]
/linux-6.14.4/arch/sparc/include/asm/
Dpgtable_64.h111 /* PTE bits which are the same in SUN4U and SUN4V format. */
118 /* SUN4U pte bits... */
149 /* SUN4V pte bits... */
233 pte_t pte = pfn_pte(page_nr, pgprot); in pfn_pmd() local
235 return __pmd(pte_val(pte)); in pfn_pmd()
241 static inline unsigned long pte_pfn(pte_t pte) in pte_pfn() argument
254 : "r" (pte_val(pte)), in pte_pfn()
262 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) in pte_modify() argument
317 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); in pte_modify()
323 pte_t pte = __pte(pmd_val(pmd)); in pmd_modify() local
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/linux-6.14.4/arch/riscv/mm/
Dhugetlbpage.c18 pte_t pte = ptep_get(ptep); in huge_ptep_get() local
20 if (pte_dirty(pte)) in huge_ptep_get()
23 if (pte_young(pte)) in huge_ptep_get()
36 pte_t *pte = NULL; in huge_pte_alloc() local
52 pte = (pte_t *)pud; in huge_pte_alloc()
58 pte = huge_pmd_share(mm, vma, addr, pud); in huge_pte_alloc()
60 pte = (pte_t *)pmd_alloc(mm, pud, addr); in huge_pte_alloc()
70 pte = pte_alloc_huge(mm, pmd, addr & napot_cont_mask(order)); in huge_pte_alloc()
76 if (pte) { in huge_pte_alloc()
77 pte_t pteval = ptep_get_lockless(pte); in huge_pte_alloc()
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/linux-6.14.4/arch/x86/include/asm/
Dpgtable.h68 #define set_pte(ptep, pte) native_set_pte(ptep, pte) argument
70 #define set_pte_atomic(ptep, pte) \ argument
71 native_set_pte_atomic(ptep, pte)
155 static inline bool pte_dirty(pte_t pte) in pte_dirty() argument
157 return pte_flags(pte) & _PAGE_DIRTY_BITS; in pte_dirty()
160 static inline bool pte_shstk(pte_t pte) in pte_shstk() argument
163 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; in pte_shstk()
166 static inline int pte_young(pte_t pte) in pte_young() argument
168 return pte_flags(pte) & _PAGE_ACCESSED; in pte_young()
171 static inline bool pte_decrypted(pte_t pte) in pte_decrypted() argument
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/linux-6.14.4/arch/parisc/include/asm/
Dpgtable.h64 extern void __update_cache(pte_t pte);
79 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
104 * done to get usable bits out of the PTE) */
182 /* this defines the shift to the usable bits in the PTE it is set so
187 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
315 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty() argument
316 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young() argument
317 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } in pte_write() argument
318 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } in pte_special() argument
320 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } in pte_mkclean() argument
[all …]
/linux-6.14.4/arch/loongarch/include/asm/
Dpgtable.h113 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
262 #define pte_pfn(x) ((unsigned long)(((x).pte & _PFN_MASK) >> PFN_PTE_SHIFT))
295 { pte_t pte; pte_val(pte) = ((type & 0x7f) << 16) | (offset << 24); return pte; } in mk_swap_pte() local
300 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) argument
305 static inline int pte_swp_exclusive(pte_t pte) in pte_swp_exclusive() argument
307 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; in pte_swp_exclusive()
310 static inline pte_t pte_swp_mkexclusive(pte_t pte) in pte_swp_mkexclusive() argument
312 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; in pte_swp_mkexclusive()
313 return pte; in pte_swp_mkexclusive()
316 static inline pte_t pte_swp_clear_exclusive(pte_t pte) in pte_swp_clear_exclusive() argument
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