Home
last modified time | relevance | path

Searched +full:a +full:- +full:f0 +full:- +full:9 (Results 1 – 25 of 197) sorted by relevance

12345678

/linux-6.14.4/scripts/
Dmarkup_oops.pl2 # SPDX-License-Identifier: GPL-2.0-only
22 'cross-compile|c=s' => \$cross_compile,
28 my $kerver = `uname -r`;
49 if ($line =~ /EAX: ([0-9a-f]+) EBX: ([0-9a-f]+) ECX: ([0-9a-f]+) EDX: ([0-9a-f]+)/) {
55 if ($line =~ /ESI: ([0-9a-f]+) EDI: ([0-9a-f]+) EBP: ([0-9a-f]+) ESP: ([0-9a-f]+)/) {
60 if ($line =~ /RAX: ([0-9a-f]+) RBX: ([0-9a-f]+) RCX: ([0-9a-f]+)/) {
65 if ($line =~ /RDX: ([0-9a-f]+) RSI: ([0-9a-f]+) RDI: ([0-9a-f]+)/) {
70 if ($line =~ /RBP: ([0-9a-f]+) R08: ([0-9a-f]+) R09: ([0-9a-f]+)/) {
74 if ($line =~ /R10: ([0-9a-f]+) R11: ([0-9a-f]+) R12: ([0-9a-f]+)/) {
79 if ($line =~ /R13: ([0-9a-f]+) R14: ([0-9a-f]+) R15: ([0-9a-f]+)/) {
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <[email protected]>
11 - Florian Fainelli <[email protected]>
12 - Heiner Kallweit <[email protected]>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
[all …]
Dethernet-phy-package.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <[email protected]>
13 PHY packages are multi-port Ethernet PHY of the same family
23 pattern: "^ethernet-phy-package@[a-f0-9]+$"
35 to a not attached PHY (offset 0).
37 '#address-cells':
40 '#size-cells':
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Dbrcm,cru.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <[email protected]>
13 Broadcom CRU ("Clock and Reset Unit" or "Central Resource Unit") is a hardware
20 - enum:
21 - brcm,ns-cru
22 - const: simple-mfd
29 "#address-cells":
32 "#size-cells":
[all …]
Dbrcm,twd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom's Timer-Watchdog (aka TWD)
10 - Rafał Miłecki <[email protected]>
13 Broadcom has a Timer-Watchdog block used in multiple SoCs (e.g., BCM4908,
15 registers layout). This block consists of: timers, watchdog and optionally a
21 - enum:
22 - brcm,bcm4908-twd
23 - brcm,bcm7038-twd
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-[email protected]>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,ifc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <[email protected]>
17 SRAM and other memories where address and data are shared on a bus.
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
32 "#size-cells":
49 little-endian:
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Ddenali,nand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <[email protected]>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
19 reg-names:
25 - const: nand_data
26 - const: denali_reg
[all …]
Dmediatek,mtk-nfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xiangsheng Hou <[email protected]>
15 - mediatek,mt2701-nfc
16 - mediatek,mt2712-nfc
17 - mediatek,mt7622-nfc
21 - description: Base physical address and size of NFI.
25 - description: NFI interrupt
[all …]
Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <[email protected]>
11 - Kamal Dasu <[email protected]>
12 - William Zhang <[email protected]>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
22 available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
18 Basically, it is a bus of devices, that could act more or less
19 as a complete entity (UCC, USB etc ). All of them should be siblings on
27 - const: fsl,qe
28 - const: simple-bus
40 bus-frequency:
44 fsl,qe-num-riscs:
[all …]
/linux-6.14.4/arch/sparc/lib/
Dcopy_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
16 /* What we used to do was lock a TLB entry into a specific
20 * we had to keep interrupts disabled for a long time.
23 * and this makes the cpu choose a slot all by itself.
24 * Then we do a normal TLB flush on exit. We need only
63 and %o2, %o3, %o0 ! vaddr D-cache alias bit
91 ba,pt %xcc, 9f
97 sethi %hi((PAGE_SIZE/64)-2), %o2
100 or %o2, %lo((PAGE_SIZE/64)-2), %o2
104 ldd [%o1 + 0x000], %f0
[all …]
/linux-6.14.4/tools/perf/
Dperf-iostat.sh2 # SPDX-License-Identifier: GPL-2.0
6 if [[ "$1" == "list" ]] || [[ "$1" =~ ([a-f0-9A-F]{1,}):([a-f0-9A-F]{1,2})(,)? ]]; then
12 perf stat --iostat$DELIMITER$*
/linux-6.14.4/arch/sparc/crypto/
Dcamellia_asm.S1 /* SPDX-License-Identifier: GPL-2.0 */
36 ld [%o0 + 0x00], %f0 ! i0, k[0]
40 std %f0, [%o1 + 0x00] ! k[0, 1]
41 fsrc2 %f0, %f28
47 ld [%o0 + 0x10], %f0
49 std %f0, [%o1 + 0x20] ! k[8, 9]
52 be,a 1f
53 fxor %f10, %f0, %f2
58 fxor %f28, %f0, %f0
72 fxor %f28, %f0, %f0
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
15 multiple phase locked loops (PLL) to create a variety of frequencies
16 which can then be passed to a variety of internal logic, including
24 --------------- -------------
30 The clockgen node should act as a clock provider, though in older device
36 - items:
[all …]
Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
11 typically includes a variety of PLLs, multiplexers, dividers & gates in order
16 - Paul Cercueil <[email protected]>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/timer/
Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 For a description of the TCU hardware and drivers, have a look at
11 Documentation/arch/mips/ingenic-tcu.rst.
14 - Paul Cercueil <[email protected]>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
24 - ingenic,jz4760b-tcu
[all …]
/linux-6.14.4/arch/powerpc/crypto/
Daes-tab-4k.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
16 * For the safety-conscious it has to be noted that they might be vulnerable
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
32 /* encryption table, same as crypto_ft_tab in crypto/aes-generic.c */
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
41 .long R(8f, ca, ca, 45), R(1f, 82, 82, 9d)
[all …]
/linux-6.14.4/arch/mips/kernel/
Dr2300_fpu.S8 * Multi-arch abstraction and asm macros for easier reading:
20 #include <asm/asm-offsets.h>
23 #define EX(a,b) \ argument
24 9: a,##b; \
25 .section __ex_table,"a"; \
26 PTR_WD 9b,fault; \
29 #define EX2(a,b) \ argument
30 9: a,##b; \
31 .section __ex_table,"a"; \
32 PTR_WD 9b,fault; \
[all …]
/linux-6.14.4/drivers/media/dvb-frontends/
Dm88ds3103.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1); in m88ds3103_update_bits()
30 return regmap_bulk_write(dev->regmap, reg, &val, 1); in m88ds3103_update_bits()
37 struct i2c_client *client = dev->client; in m88ds3103_wr_reg_val_tab()
41 dev_dbg(&client->dev, "tab_len=%d\n", tab_len); in m88ds3103_wr_reg_val_tab()
44 ret = -EINVAL; in m88ds3103_wr_reg_val_tab()
51 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || in m88ds3103_wr_reg_val_tab()
52 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) { in m88ds3103_wr_reg_val_tab()
53 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1); in m88ds3103_wr_reg_val_tab()
57 j = -1; in m88ds3103_wr_reg_val_tab()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <[email protected]>
11 - Maxime Ripard <[email protected]>
15 by a regular node for the SRAM controller itself, with sub-nodes
19 "#address-cells":
22 "#size-cells":
27 - enum:
[all …]
/linux-6.14.4/arch/arm/include/asm/
Dkgdb.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 * GDB assumes that we're a user process being debugged, so
23 * we would loose the kernel's LR, which is a bad thing. This
26 * By doing this as an undefined instruction trap, we force a mode
29 * We also define a KGDB_COMPILED_BREAK which can be used to compile
30 * in breakpoints. This is important for things like sysrq-G and for
59 * r0-r15: 1 long word each
60 * f0-f7: unused, 3 long words each !!
64 * Even though f0-f7 and fps are not used, they need to be
66 * the host-side gdb.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mailbox/
Dfsl,mu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <[email protected]>
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
31 - const: fsl,imx8-mu-seco
[all …]
/linux-6.14.4/tools/testing/selftests/bpf/progs/
Dverifier_array_access.c1 // SPDX-License-Identifier: GPL-2.0
53 __description("valid map access into an array with a constant")
60 *(u64*)(r10 - 8) = r1; \ in an_array_with_a_constant_1()
62 r2 += -8; \ in an_array_with_a_constant_1()
77 __description("valid map access into an array with a register")
84 *(u64*)(r10 - 8) = r1; \ in __flag()
86 r2 += -8; \ in __flag()
104 __description("valid map access into an array with a variable")
111 *(u64*)(r10 - 8) = r1; \ in __flag()
113 r2 += -8; \ in __flag()
[all …]

12345678