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/linux-6.14.4/drivers/gpu/drm/msm/adreno/
Da3xx_gpu.h16 #include "a3xx.xml.h"
Da3xx_catalog.c87 DECLARE_ADRENO_GPULIST(a3xx);
Da3xx_gpu.c316 * for a2xx and a3xx.. we could possibly push that part down to in a3xx_hw_init()
553 DRM_DEV_ERROR(dev->dev, "no a3xx device\n"); in a3xx_gpu_init()
Da2xx_gpu.c222 * for a2xx and a3xx.. we could possibly push that part down to in a2xx_hw_init()
/linux-6.14.4/drivers/gpu/drm/msm/registers/adreno/
Dadreno_common.xml9 <value name="A3XX" value="3"/>
113 <brief>Registers in common between a2xx and a3xx</brief>
282 Common between A3xx and A4xx:
333 TODO check if that 256 size is same for all a3xx
Dadreno_pm4.xml21 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
45 <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
152 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
159 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
370 <!-- for a3xx -->
372 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
377 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
657 <doc>Load state, a3xx (and later?)</doc>
1126 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1128 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
[all …]
Da4xx.xml70 <!-- hmm, shifted one compared to a3xx?!? -->
337 on a3xx the countable #'s from AMD_performance_monitor disagreed with
342 <!-- first ctr at least seems same as a3xx, so we can measure freq -->
936 common value is 2, like on a3xx..
1661 <!-- TODO double check.. for now assume same as a3xx -->
2032 <!-- I guess same as a3xx, but so far only seen 08000050 -->
2368 like a3xx we seem to have two LAYERSZ's.. although this one
Da6xx.xml3024 <!-- guess based on a3xx and meaning of bits 8 and 9
3170 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for
3177 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
3183 <!-- I'm guessing this is the same as a3xx -->
4701 Seems to be the same as a3xx. The maximum stack
4705 size of the PC? a3xx docs say it's 16 bits
4758 a3xx. The ldp/stp offset formula above isn't affected by
5186 This enum is probably similar in purpose to SNORMMODE on a3xx,
5493 A3xx field, except that it's not necessary to set it to anything but the maximum, since
Da3xx.xml558 <domain name="A3XX" width="32">
633 to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
Da2xx.xml1050 any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where
1052 register on a3xx.. so moving this back into A2XX domain:
Da5xx.xml2021 not sure if there is a separate COLOR_SWAP field like on a3xx/a4xx,
2024 field, it doesn't seem to have the same encoding as a3xx/a4xx.
2528 <doc>Guessing that this is the same as a3xx/a6xx.</doc>
/linux-6.14.4/drivers/gpu/drm/msm/registers/
Dfreedreno_copyright.xml13 many a3xx/a4xx contributions
/linux-6.14.4/Documentation/devicetree/bindings/display/msm/
Dgpu.yaml94 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
242 // Example a3xx/4xx:
/linux-6.14.4/drivers/gpu/drm/msm/
Dmsm_ringbuffer.h126 /* ringbuffer helpers (the parts that are same for a3xx/a2xx/z180..) */
DNOTES16 + and either a2xx or a3xx 3d core.
DMakefile195 generated/a3xx.xml.h \
Dmsm_gpu.h34 * + a3xx or a2xx 3d core, which share a common CP (the firmware