Searched full:a5xx (Results 1 – 11 of 11) sorted by relevance
27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->52 <!-- a5xx events -->53 <value name="WT_DONE_TS" value="8" variants="A5XX-"/>54 <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>55 <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>56 <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>57 <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>58 <value name="FLUSH_SO_0" value="17" variants="A5XX-"/>59 <value name="FLUSH_SO_1" value="18" variants="A5XX-"/>60 <value name="FLUSH_SO_2" value="19" variants="A5XX-"/>[all …]
11 <value name="A5XX" value="5"/>365 <doc>Address mode for a5xx+</doc>372 Line mode for a5xx+
23 <!-- these might be same as a5xx -->188 <!-- probably same as a5xx -->2965 Compared to a5xx and earlier, we just program the address of the first3664 Compared to a5xx and before, we configure both a GMEM base and3838 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->3983 <!-- unlike a5xx, these are per channel values rather than packed -->4680 Starting with a5xx, position/psize outputs from shader end up in the5322 <!-- looks to work in the same way as a5xx: -->5335 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either5812 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
815 <domain name="A5XX" width="32">2504 Starting with a5xx, position/psize outputs from shader end up in the
152 DECLARE_ADRENO_GPULIST(a5xx);
13 #include "a5xx.xml.h"
300 /* Not all A5xx chips have a GPMU */ in a5xx_power_init()
635 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
1635 /* Dump the additional a5xx HLSQ registers */ in a5xx_show()1799 /* a5xx only supports UBWC 1.0, these are not configurable */ in a5xx_gpu_init()
197 generated/a5xx.xml.h \
109 For a5xx and a6xx devices this node contains a memory-region that